| LSI Corporation Patent applications |
| Patent application number | Title | Published |
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| 20120137065 | Virtual Port Mapped RAID Volumes - Embodiments of the invention provide a method associated with a RAID configuration, wherein RAID storage volumes are created by RAID controllers from a shared pool of disk drives. A specified RAID volume is mapped to a virtual target port, and is accessed by each of one or more servers via the virtual target address. One embodiment of the invention is directed to a method associated with multiple RAID controllers, and a pool of disk drives that comprises multiple storage disks. The method comprises operating one or more of the RAID controllers to each configure one or more RAID volumes from selected storage disks. A unique identifier is assigned to each of the RAID volumes, wherein a specified RAID volume is assigned a specified unique identifier, and a particular RAID controller is provided with ownership of the specified RAID volume at a particular time. The method further comprises using the specified unique identifier in an address to route an I/O message at the particular time between a selected host and the specified RAID volume, wherein the unique identifier includes no information that identifies the particular RAID controller. | 05-31-2012 |
| 20120126387 | ENHANCED HEAT SPREADER FOR USE IN AN ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device includes an integrated circuit (IC) die attached to a substrate, and electrical conductors connecting the IC die to the substrate. The electronic device also includes a heat spreader located over the IC die and having a concaved portion located over the IC die along with a lateral portion extending from the concaved portion. The lateral portion has a surface area greater than a surface area of the concaved portion. A support member is further included that extends from the lateral portion to and contacts the substrate. An encapsulant covers the support member leaving the lateral and concaved portions exposed on outer sides thereof. In another aspect, a method of manufacturing an electronic device is also included. | 05-24-2012 |
| 20120126364 | MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK - An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. | 05-24-2012 |
| 20120124319 | METHODS AND STRUCTURE FOR TUNING STORAGE SYSTEM PERFORMANCE BASED ON DETECTED PATTERNS OF BLOCK LEVEL USAGE - Methods and structure within a storage system for tuning performance of the storage system based on monitored block level access within the storage system. Block level access, either in cache memory or on the storage devices of the storage system, is monitored to detect patterns of access and/or data that correspond to an identified host system program. Based on the identified host system program, a profile of desired storage device configuration information is selected by the storage system. The profile comprises information identifying optimal configuration of a logical volume used by the corresponding host system program. Reconfiguration options are identified from the profile information and used either to automatically reconfigure the logical volume or are presented to a user to permit the user to select desired options from the reconfiguration options. | 05-17-2012 |
| 20120124295 | METHODS AND STRUCTURE FOR DETERMINING CACHE SIZE IN A STORAGE SYSTEM - Methods and structure for automated determination and reconfiguration of the size of a cache memory in a storage system. Features and aspects hereof generate historical information regarding frequency of hits on cache lines in the cache memory. The history maintained is then analyzed to determine a desired cache memory size. The historical information regarding cache memory usage may be communicated to a user who may then direct the storage system to reconfigure its cache memory to a desired cache memory size. In other embodiments, the storage system may automatically determine the desired cache memory size and reconfigure its cache memory. The method may be performed automatically periodically, and/or in response to a user's request, and/or in response to detecting thrashing caused by least recently used (LRU) cache replacement algorithms in the storage system. | 05-17-2012 |
| 20120124256 | METHOD FOR DETERMINISTIC SAS DISCOVERY AND CONFIGURATION - The present invention is directed to a method for deterministic Serial Attached Small Computer System Interface (SAS) discovery and configuration. The method includes transmitting a Serial Management Protocol (SMP) DISCOVER Request from a node of a SAS domain to each expander of the SAS domain. The method further includes receiving SMP DISCOVER Responses at the node from each expander of the SAS domain. The method further includes comparing BROADCAST (CHANGE) RECEIVED (BCR) counts provided in each of the received SMP DISCOVER Responses to stored BCR counts, said stored BCR counts having been recorded and stored by the node prior to said transmitting of said SMP DISCOVER Request. The method further includes updating the stored BCR counts based upon said received BCR counts. The method further includes selectively transmitting a second SMP DISCOVER Request from the node to at least one, but not all of the expanders of the SAS domain. | 05-17-2012 |
| 20120121097 | UTILIZING INFORMATION FROM A NUMBER OF SENSORS TO SUPPRESS ACOUSTIC NOISE THROUGH AN AUDIO PROCESSING SYSTEM - A method includes associating a spatially separate audio sensor and/or a vibration sensor with an audio processing system having one or more audio sensor(s) associated therewith. The spatially separate audio sensor is on a remote location distinct from that of the one or more audio sensor(s). The method also includes capturing information uniquely associated with an external environment of the audio processing system through the spatially separate audio sensor and/or the vibration sensor and the one or more audio sensor(s), and adapting an audio output of the audio processing system based on the captured information uniquely associated with the external environment thereof. | 05-17-2012 |
| 20120121018 | Generating Single-Slice Pictures Using Paralellel Processors - A video encoding system generates (e.g., H.264) single-slice pictures using parallel processors. Each picture is divided horizontally into multiple segments, where each different parallel processor processes a different segment. Each parallel processor (other than the first parallel processor of the uppermost segment) only partially processes the macroblocks in the first row of its segment. Subsequently, a final processor completes the processing of the partially encoded, first-row macroblocks based on the encoding results for the macroblocks in the last row of the segment above and across the segment boundary. The encoding of the first-row macroblocks is constrained to enable the encoding of all other rows of macroblocks to be completed by the parallel processors, without relying on the final processor. | 05-17-2012 |
| 20120119789 | Peak Detector Extension System - The different illustrative embodiments provide a method and apparatus for managing peak detector circuits. A first number of voltages for a first number of signals detected by a peak detector circuit connected to a wire in a bus system is identified. The first number of signals is used to send data over the wire. The first number of voltages is for a first number of transmission speeds for the first number of signals. A second number of voltages for a second number of signals detected by the peak detector circuit is identified. The second number of signals is present in the wire in an absence of the data being sent over the wire. The second number of voltages is for a second number of transmission speeds for the second number of signals. A number of settings are selected for the peak detector circuit based on the first number of voltages and the second number of voltages. | 05-17-2012 |
| 20120119785 | INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR - One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides. | 05-17-2012 |
| 20120117562 | METHODS AND STRUCTURE FOR NEAR-LIVE REPROGRAMMING OF FIRMWARE IN STORAGE SYSTEMS USING A HYPERVISOR - Methods and structure for reprogramming firmware in a storage controller using a virtual machine management (VMM) environment. A storage process (current firmware) in the storage controller operates in a current virtual machine (VM) under control of a hypervisor. Reprogrammed (new) firmware is loaded into a new virtual machine under control of the hypervisor. The new firmware initializes and directs the current firmware to quiesce its processing. The new firmware also requests the hypervisor to map data in the memory space of the current virtual machine into the memory space of the new virtual machine and to transfer ownership/control of devices and network addresses from the current virtual machine to the new virtual machine. The new firmware operating on the new virtual machine then takes control of the storage controller and resumes processing of requests. | 05-10-2012 |
| 20120117555 | METHOD AND SYSTEM FOR FIRMWARE ROLLBACK OF A STORAGE DEVICE IN A STORAGE VIRTUALIZATION ENVIRONMENT - A method and controller device for upgrading the firmware in a virtualized storage environment having a first storage controller and a second storage controller, wherein each storage controller includes a first virtual machine, at least one second virtual machine and a storage device. The method includes upgrading the current firmware of the first virtual machine in the first storage controller to a new firmware version, upgrading the current firmware of the second virtual machine in the first storage controller to a new firmware version, upgrading the current firmware of the first virtual machine in the second storage controller, upgrading the current firmware of the second virtual machine in the second storage controller, and rolling back the firmware version of all virtual machines in the first and second storage controllers if the firmware upgrade of any of the virtual machines in the first and second storage controllers is not successful. | 05-10-2012 |
| 20120117332 | SYNCHRONIZING COMMANDS FOR PREVENTING DATA CORRUPTION - A method and apparatus for synchronizing input/output commands is provided. An incoming command mask representing an incoming input/output command associated with a memory region is created. In response to a determination that a pending input/output command associated with the memory region is pending, a bitwise inversion operation is performed on the incoming command mask to form a modified incoming command mask. A bitwise AND operation is performed on the modified incoming command mask and the pending command mask to form a pending command locking mask associated with the pending input/output command. A bitwise OR operation is performed between an existing memory lock for a same type of commands and incoming command bit mask to form a new memory region lock. | 05-10-2012 |
| 20120117328 | Managing a Storage Cache Utilizing Externally Assigned Cache Priority Tags - A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium. | 05-10-2012 |
| 20120117320 | LATENCY REDUCTION ASSOCIATED WITH A RESPONSE TO A REQUEST IN A STORAGE SYSTEM - A method includes segmenting a virtual volume into an active area configured to map to a first type of storage and a non-active area configured to map to a second type of storage through a storage virtualization engine. The second type of storage includes data associated with a host device and the first type of storage includes point-in-time images corresponding to the data associated with the host device. The first type of storage offers a higher performance than that of the second type of storage. The method also includes allocating a portion of space in the first type of storage to serve as a cache memory during a write operation and/or a read operation, and reducing a latency associated with the response to a write request and/or a read request through performing the corresponding write operation and/or the read operation through the first type of storage. | 05-10-2012 |
| 20120117295 | MULTI-STAGE INTERCONNECTION NETWORKS HAVING FIXED MAPPINGS - In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages. | 05-10-2012 |
| 20120113984 | MULTI-STAGE INTERCONNECTION NETWORKS HAVING SMALLER MEMORY REQUIREMENTS - In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages. | 05-10-2012 |
| 20120111927 | ALUMINUM BOND PADS WITH ENHANCED WIRE BOND STABILITY - A method of forming an electronic device bond pad includes providing an electronic device substrate having an Al bond pad located thereover. An aluminum layer is formed over the Al bond pad. A metal layer is formed located between the Al bond pad and the aluminum layer. The metal layer comprises one or more of Ni, Pd and Pt and has a total concentration of Ni, Pd and/or Pt of at least about 50 wt. %. A gold bond wire may be attached to the aluminum layer. | 05-10-2012 |
| 20120110377 | PERFORMING DATA WRITES IN PARITY PROTECTED REDUNDANT STORAGE ARRAYS - A first and a second physical disk identifier, a physical Logical Block Address (LBA), a data length, and a span identifier are calculated from a data write operation. A first request command frame is created for retrieving the existing data block from the storage array, the first request command frame including at least one of the calculated parameters. At least one second request command frame is created for retrieving the at least one existing parity data block from the storage array, the at least one second request command frame including the calculated at least one second physical disk identifier and at least one of the calculated parameters. At least one new parity data block is calculated utilizing the existing data block, the new data block, and the at least one existing parity data block. | 05-03-2012 |
| 20120110211 | MANAGEMENT OF DETECTED DEVICES COUPLED TO A HOST MACHINE - In one embodiment, a method includes detecting a coupling of a device to an interface of the host machine. The method also includes determining, through an operating system of the host machine whether the device coupled to the interface of the host machine is same as another device that is formerly coupled to the interface of the host machine as indicated in a topology file of the operating system. In addition, the method includes modifying the topology file maintained in the operating system to remove a mapping information of the other device that is formerly coupled with the interface of the host machine in the topology file to logically decouple the other device from the interface of the host machine and to add a mapping information of the device coupled with the interface in the topology file to logically couple the device with the interface of the host machine. | 05-03-2012 |
| 20120106642 | Motion Estimation for a Video Transcoder - A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein motion-vector dispersion observed at the higher spatial resolution is quantified and used to configure the motion-vector search at the lower spatial resolution. For example, for video-frame areas characterized by relatively low motion-vector dispersion values, the motion-vector search may be performed over a relatively small vector space and with the use of fewer search patterns and/or hierarchical search levels. These constraints enable the transcoder to find appropriate motion vectors for inter-prediction coding without having to perform an exhaustive motion-vector search for these video-frame areas, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder. | 05-03-2012 |
| 20120105719 | SPEECH SUBSTITUTION OF A REAL-TIME MULTIMEDIA PRESENTATION - Disclosed are a method, an apparatus and/or system of speech substitution of a real-time multimedia presentation on an output device. In one embodiment, a method includes processing a multimedia signal of a multimedia presentation, using a processor. The multimedia signal includes a video signal and an audio signal, such that the audio signal is substitutable with another audio signal based on a preference of a user. The method also includes substituting the audio signal with another audio signal based on the preference of the user. Additionally, the method includes permitting a selection of a voice profile during a real-time event based on a response to a request through a client device of the user. | 05-03-2012 |
| 20120102491 | VIRTUAL FUNCTION BOOT IN SINGLE-ROOT AND MULTI-ROOT I/O VIRTUALIZATION ENVIRONMENTS - A method for virtual function boot in a system including a single-root I/O virtualization (SR-IOV) enabled server includes loading a PF driver of the PF of a storage adapter onto the server utilizing the virtual machine manager of the server; creating a plurality of virtual functions utilizing the PF driver, detecting each of the virtual functions on an interconnection bus, maintaining a boot list associated with the plurality of virtual functions, querying the storage adapter for the boot list utilizing a VMBIOS associated with the plurality of VMs, presenting the detected boot list to a VM boot manager of the VMM, and booting each of the plurality of virtual machines utilizing each of the virtual functions, wherein each VF of the plurality of VFs is assigned to a VM of the plurality of VMs via an interconnect passthrough between the VMM and the plurality of VMs. | 04-26-2012 |
| 20120102455 | SYSTEM AND APPARATUS FOR HOSTING APPLICATIONS ON A STORAGE ARRAY VIA AN APPLICATION INTEGRATION FRAMEWORK - A storage array is disclosed. The storage array may comprise a plurality of storage units configured for providing data storage; a processing module configured for hosting a virtual machine; and an application integration framework provided by the virtual machine. The application integration framework may comprise an application interface configured for interfacing with at least one application running on an application server, where the application server is communicatively connected with the storage array. The application integration framework may further comprise a software development kit (SDK) communicatively coupled to the application interface via a communication module, the SDK being configured for providing a programmatic interface to the at least one application and enabling the at least one application for delegating at least a portion of data processing operations to the storage array. | 04-26-2012 |
| 20120102268 | METHODS AND SYSTEMS USING SOLID-STATE DRIVES AS STORAGE CONTROLLER CACHE MEMORY - Methods and systems for using one or more solid-state drives (SSDs) as a shared cache memory for a plurality of storage controllers coupled with the SSDs and coupled with a plurality of storage devices through a common switched fabric communication medium. All controllers share access to the SSDs through the switched fabric and thus can assume control for a failed controller by, in part, accessing cached data of the failed controller in the shared SSDs. | 04-26-2012 |
| 20120102251 | SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE (SAS) DOMAIN ACCESS THROUGH A UNIVERSAL SERIAL BUS INTERFACE OF A DATA PROCESSING DEVICE - A method, an apparatus and/or a system of serial attached small computer system interface (SAS) domain access through a universal serial bus (USB) interface of a data processing device. A method includes communicatively coupling a serial attached small computer system interface (SAS) domain to the data processing device through the universal serial bus (USB) interface of the data processing device via an expander device. The method also includes accessing a SAS device of the SAS domain and/or the SAS domain through the USB interface of the data processing device via the expander device. The method further includes bridging through a firmware of the expander device between a USB command of the data processing device and a SAS command of the SAS domain to communicate between the data processing device and the SAS domain. | 04-26-2012 |
| 20120099670 | COMMUNICATIONS SYSTEM SUPPORTING MULTIPLE SECTOR SIZES - In one embodiment, a configurable communications system accommodates a plurality of different transmission word sizes. In a transmit path, the system inserts a number of padding bits corresponding to missing user-data bits onto the end of an input data sequence to generate a set of data having N bits. The N bits are interleaved and error-correction (EC) encoded to generate parity bits corresponding to an EC codeword. The parity bits are de-interleaved and multiplexed with the input data stream to generate a transmission word. In a receive path, a channel detector recovers channel values corresponding to the transmission word. Padding values, corresponding to the missing-bit locations, are inserted among the channel values. The resulting channel values are interleaved and EC decoded to recover the EC codeword. The data bits of the codeword are de-interleaved, and the padding bits corresponding to the missing channel values are discarded. | 04-26-2012 |
| 20120098571 | METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS - Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed. | 04-26-2012 |
| 20120095746 | NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW - A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget. | 04-19-2012 |
| 20120089782 | METHOD FOR MANAGING AND TUNING DATA MOVEMENT BETWEEN CACHES IN A MULTI-LEVEL STORAGE CONTROLLER CACHE - A method for managing data movement in a multi-level cache system having a primary cache and a secondary cache. The method includes determining whether an unallocated space of the primary cache has reached a minimum threshold; selecting at least one outgoing data block from the primary cache when the primary cache reached the minimum threshold; initiating a de-stage process for de-staging the outgoing data block from the primary cache; and terminating the de-stage process when the unallocated space of the primary cache has reached an upper threshold. The de-stage process further includes determining whether a cache hit has occurred in the secondary cache before; storing the outgoing data block in the secondary cache when the cache hit has occurred in the secondary cache before; generating and storing metadata regarding the outgoing data block; and deleting the outgoing data block from the primary cache. | 04-12-2012 |
| 20120084600 | METHOD AND SYSTEM FOR DATA RECONSTRUCTION AFTER DRIVE FAILURES - Methods and systems for data reconstruction following drive failures may include: storing data across two or more drives in one or more data stripes, each data stripe including two or more drive extents; detecting a degradation of a drive containing a drive extent associated with a first data stripe; assigning a reconstruction priority to the drive extent associated with the first data stripe; detecting a degradation of a drive containing a drive extent associated with a second data stripe; and assigning a reconstruction priority to the drive extent associated with the second data stripe. | 04-05-2012 |
| 20120084590 | IMPLEMENTING SLEEP LINES IN COMMODITY ETHERNET HARDWARE - A first Network Interface Controller operates in a low power mode. The first Network Interface Controller transitions from low power mode to a power-up sequence if a sleep packet in not received from a second Network Interface Controller at the first Network Interface Controller within a predetermined time threshold. | 04-05-2012 |
| 20120082220 | INTRA-MODE PREDICTION FOR A VIDEO TRANSCODER - A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein learned statistics of intra-mode transcoding are used to constrain the search of intra modes for the output video bit-stream. The statistics of intra-mode transcoding can be gathered, e.g., by applying brute-force downsizing to a training set of video frames and then analyzing the observed intra-mode transcoding patterns to determine a transition-probability matrix for use during normal operation of the transcoder. The transition-probability matrix enables the transcoder to select appropriate intra modes for the output video bit-stream without performing a corresponding exhaustive full search, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder. | 04-05-2012 |
| 20120079345 | SYSTEM AND METHOD FOR ASSIGNING CODE BLOCKS TO CONSTITUENT DECODER UNITS IN A TURBO DECODING SYSTEM HAVING PARALLEL DECODING UNITS - A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the method includes: (1) representing the turbo decoding system as a resource diagram rectangle, (2) representing the code blocks as code block rectangles, (3) mapping the code block rectangles into the resource diagram rectangle and (4) assigning the code blocks to the constituent decoding units based on the mapping. | 03-29-2012 |
| 20120079340 | COMMUNICATIONS SYSTEM EMPLOYING LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING - In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path. | 03-29-2012 |
| 20120079324 | FIRMWARE TRACING IN A STORAGE DATA COMMUNICATION SYSTEM - A method includes generating trace data at a device associated with data communication to and from a computer storage device through an appropriate communication link therefor and transmitting the trace data through the appropriate communication link. The trace data is configured to enable debugging of a set of instructions associated with the device. The method also includes capturing the trace data transmitted through the appropriate communication link through a protocol analyzer, a host system or the protocol analyzer coupled to the host system and analyzing the trace data therein to obtain information associated with the set of instructions associated with the device. The protocol analyzer, the host system or the protocol analyzer coupled to the host system is configured to be external to the device associated with the data communication to and from the computer storage device. | 03-29-2012 |
| 20120072924 | SAS SMP TUNNELING USING SCSI COMMANDS - A storage system comprising: a SCSI initiator being configured for receiving a data request and providing a SMP request corresponding to the data request, the SCSI initiator being further configured for encapsulating the SMP request into a first SCSI command; a SCSI target being configured for receiving the first SCSI command, the SCSI target being further configured for recognizing encapsulation of the SMP request and obtaining the SMP request from the first SCSI command; and an SMP target being configured for processing the SMP request and providing an SMP response to the SCSI target. The SCSI target being further configured for acknowledging the SCSI initiator upon reception of the SMP response; and the SCSI initiator being further configured for sending a second SCSI command to the SCSI target to retrieve the SMP response. | 03-22-2012 |
| 20120072797 | DESIGN-FOR-TEST TECHNIQUE TO REDUCE TEST VOLUME INCLUDING A CLOCK GATE CONTROLLER - Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell. | 03-22-2012 |
| 20120072772 | METHOD FOR DETECTING A FAILURE IN A SAS/SATA TOPOLOGY - A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure. | 03-22-2012 |
| 20120072670 | METHOD FOR COUPLING SUB-LUN LOAD MEASURING METADATA SIZE TO STORAGE TIER UTILIZATION IN DYNAMIC STORAGE TIERING - A method for metadata management in a storage system configured for supporting sub-LUN tiering. The method may comprise providing a metadata queue of a specific size; determining whether the metadata for a particular sub-LUN is cached in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is cached in the metadata queue; inserting the metadata for the particular sub-LUN to the metadata queue when the metadata queue is not full and the metadata is not cached; replacing an entry in the metadata queue with the metadata for the particular sub-LUN when the metadata queue is full and the metadata is not cached; and identifying at least one frequently accessed sub-LUN for moving to a higher performing tier in the storage system, the at least one frequently accessed sub-LUN being identified based on the metadata cached in the metadata queue. | 03-22-2012 |
| 20120072662 | ANALYZING SUB-LUN GRANULARITY FOR DYNAMIC STORAGE TIERING - A method for metadata management in a storage system may include providing a metadata queue of a maximum size; determining whether the metadata for a particular sub-LUN is held in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is held in the metadata queue; inserting the metadata for the particular sub-LUN at the head of the metadata queue when the metadata queue is not full and the metadata is not held in the metadata queue; replacing an entry in the metadata queue with the metadata for the particular sub-LUN and moving the metadata to the head of the metadata queue when the metadata queue is full and the metadata is not held in the metadata queue; and controlling the number of sub-LUNs in the storage system to manage data accessed with respect to an amount of available data storage. | 03-22-2012 |
| 20120066429 | Peripheral Device, Program and Methods for Responding to a Warm Reboot Condition - A computing system peripheral device compatible with the peripheral component interconnect express (PCI-E) protocol responds to a DL_DOWN command primitive by configuring a general-purpose input/output (GPIO) port into a known state without invoking a GPIO module reset. In addition, select resources are excluded from resources on the peripheral device that are issued a reset command. The select resources can include a GPIO module, a memory element and a PCI-E SERDES module. After the remaining reset resources have completed their individual initialization processes, the central processor core on the peripheral device is reset. The described response to the DL_DOWN command primitive avoids cache data loss, masks signal transitions on I/O ports and timing problems that prevent some peripheral devices from being recognized in a computer's basic input/output system (BIOS). | 03-15-2012 |
| 20120065919 | BUILT-IN SELF-TEST CIRCUIT-BASED RADIATION SENSOR, RADIATION SENSING METHOD AND INTEGRATED CIRCUIT INCORPORATING THE SAME - A radiation sensor for an integrated circuit (IC), a radiation sensing method and an IC incorporating the sensor or the method. In one embodiment, the radiation sensor includes: (1) a built-in self-test (BIST) controller configured to provide BIST with respect to main IC circuitry of the IC and (2) a radiation sensor controller coupled to the main IC circuitry and the BIST controller and configured to identify temporarily inactive portions of the main IC circuitry and cause the BIST controller to perform at least one BIST with respect to at least one of the portions, the at least one of the portions acting as a radiation target. | 03-15-2012 |
| 20120063248 | LOW COST COMPARATOR DESIGN FOR MEMORY BIST - A comparator determines the fidelity of a response vector received from a memory under test. The comparator includes a first logic gate configured to output a first value that is the logical OR of a first proper subset of bits of the response vector. A second logic gate is configured to output a second value that is the logical NAND of the proper subset of bits. A first multiplexer is configured to select between the first and second values based on the value of a first bit of a check vector corresponding to the response vector. | 03-15-2012 |
| 20120047494 | APPLICATION PROGRAMMING INTERFACE (API) ROUTER IMPLEMENTATION AND METHOD - An application programming interface (API) implementation that can interface between an application and a programming library. The implementation includes a Function Router Wrapper that receives a formatted string from the application. The formatted string includes a function name element filled with a function name, an input element filled with function input parameters, and an unfilled output element. The Function Router Wrapper converts the formatted string and passes it to a Function Router, which parses the converted formatted string to access the function name and the function input parameters. The Function Router calls a library function based on the accessed information. When the called library function is completed, the Function Router collects generated function outputs and embeds them into the formatted string output element. The Function Router passes the formatted string back up to the Function Router Wrapper, which converts the formatted string and passes it back up to the application. | 02-23-2012 |
| 20120042220 | LOW-COST DESIGN FOR REGISTER FILE TESTABILITY - A self-test module for use in an electronic device includes a test controller and a memory. The memory is configured to receive test vectors from the test controller. A comparator is configured to receive the test data from the memory via an output data path. A strobing buffer is located in the output data path between an output from the memory and an input to the comparator. The strobing buffer is configured to selectively enable the test vectors to propagate from the memory output to the comparator input. | 02-16-2012 |
| 20120042115 | APPARATUS AND METHODS FOR LOOK-AHEAD VIRTUAL VOLUME META-DATA PROCESSING IN A STORAGE CONTROLLER - Apparatus and methods for improved efficiency in accessing meta-data in a storage controller of a virtualized storage system. Features and aspects hereof walk/retrieve meta-data for one or more other I/O requests when retrieving meta-data for a first I/O request. The meta-data may include mapping information for mapping logical addresses of the virtual volume. Meta-data may also include meta-data associated with higher level, enhanced data services provide by or in conjunction with the storage system. Enhanced data services may include features for synchronous mirroring of a volume and/or management of time-based snapshots of the content of a virtual volume. | 02-16-2012 |
| 20120042114 | APPARATUS AND METHODS FOR MANAGING EXPANDED CAPACITY OF VIRTUAL VOLUMES IN A STORAGE SYSTEM - Methods and apparatus for expanded capacity virtual volumes in a virtualized storage system. A storage controller of the storage system parses a SCSI command block as it is received to generate a tag value indicating a segment of a virtual volume to which the command block is directed. The tag value is used to select one of a plurality of mapping segment objects stored in a memory of the controller. Each mapping segment objects maps logical block addresses of a corresponding segment of a corresponding virtual volume to physical storage addresses on the physical storage devices that comprise the virtual volume. An I/O processing circuit of the controller then processes the SCSI command block in accordance with the mapping information in the selected mapping segment object. In one exemplary embodiment, each segment of a virtual volume comprises 2 terabytes of storage capacity of the virtual volume. | 02-16-2012 |
| 20120042101 | APPARATUS AND METHODS FOR REAL-TIME ROUTING OF RECEIVED COMMANDS IN A SPLIT-PATH ARCHITECTURE STORAGE CONTROLLER - Apparatus and methods for real-time routing of received frames in a split-path architecture storage controller. In one exemplary embodiment, a split-path storage controller comprises a soft-path I/O processor for processing of any received frames and comprises a fast-path I/O processor for efficient processing of common read and write command. A content parsing circuit of the storage controller parses each frame substantially concurrent with reception of the frame and selects an I/O processor for processing of an initial frame and subsequent related frames. Received frames are then routed concurrently as they are received for processing by the selected I/O processor of the multiple I/O processors of the split-path storage controller. | 02-16-2012 |
| 20120038896 | Maskless Vortex Phase Shift Optical Direct Write Lithography - The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns. | 02-16-2012 |
| 20120036321 | SYSTEM AND METHOD FOR PROVIDING IMPLICIT UNMAPS IN THINLY PROVISIONED VIRTUAL TAPE LIBRARY SYSTEMS - The present invention is a system and method which allows for a VTL system that supports thin provisioning to implicitly unmap unused storage. Such unmap operations may occur even though the VTL system does not receive any explicit unmap requests from its initiators. For example, if a system administrator knows that once a virtual tape drive of the VTL system has been partially overwritten, all previously written data sets on that virtual tape drive will never again be accessed, the system administrator may configure the VTL system so that it unmaps the entire remainder of the virtual tape drive on the first data overwrite. | 02-09-2012 |
| 20120033925 | MODIFICATION OF SEMICONDUCTOR OPTICAL PATHS BY MORPHOLOGICAL MANIPULATION - An optical device includes a substrate and a semiconductor layer located over the substrate. The optical path includes a semiconductor layer that further includes a waveguide core region. The core region includes a first semiconductor region with a morphology of a first type and a first refractive index. The first semiconductor region is located adjacent a second semiconductor region that has a morphology of a second type and a second refractive index that is different from the first refractive index. | 02-09-2012 |
| 20120033479 | MODIFICATION OF LOGIC BY MORPHOLOGICAL MANIPULATION OF A SEMICONDUCTOR RESISTIVE ELEMENT - An electronic device includes a substrate with a resistive element located thereover. The resistive element includes a semiconductor region. A read module is configured to determine a resistance of the resistive element. A programming module is configured to cause a current to flow through the semiconductor region. The current is sufficient to induce a change of morphology of at least a portion of the semiconductor region. | 02-09-2012 |
| 20120026623 | DIBIT EXTRACTION FOR ESTIMATION OF CHANNEL PARAMETERS - In one embodiment, a storage-device-implemented method for estimating one or more channel parameters of a storage device including a read channel and a storage medium with a bit sequence stored on the storage medium. The method includes: (a) the storage device reading at least a portion of the bit sequence from the storage medium to generate a bit response; (b) the storage device convolving the bit response to compute an impulse response of the read channel; and (c) the storage device estimating one or more channel parameters based on the computed impulse response. | 02-02-2012 |
| 20120021599 | Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package - An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board. | 01-26-2012 |
| 20120020028 | STACKED INTERCONNECT HEAT SINK - An electronic device includes an integrated circuit and a heat spreader. The integrated circuit includes a substrate with an active via located therein. The heat spreader includes a thermally conductive core. The active via is connected to a corresponding heat spreader via that passes through the thermally conductive core. | 01-26-2012 |
| 20120018901 | FLIP-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME USING ABLATION - A method of manufacturing a flip-chip package and a flip-chip package manufactured by such method. In one embodiment, the method includes: (1) mounting a die to a first die, (2) encapsulating the second die with a molding compound and (3) selectively ablating the molding compound based on an expected heat generation of portions of the second die to reduce a thickness of the molding compound proximate the portions. | 01-26-2012 |
| 20120017190 | IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME - An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit. | 01-19-2012 |
| 20120017132 | LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING - In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing. | 01-19-2012 |
| 20120017041 | MANAGING EXTENDED RAID CACHES USING COUNTING BLOOM FILTERS - Contentual metadata of an extended cache is stored within the extended cache. The contentual metadata of the extended cache is approximated utilizing a counting Bloom filter. The counting Bloom filter is stored within a primary cache. Contentual metadata of the primary cache is stored within the primary cache. One of a data read or a data write is executed without accessing the contentual metadata of the extended cache stored within the extended cache. | 01-19-2012 |
| 20120016992 | ARCHITECTURE FOR IMPROVED CLOUD COMPUTING - The present invention is directed to an architecture for promoting improved cloud computing. The architecture includes a plurality of diskless server nodes. The architecture further includes a plurality of Serial Attached Small Computer System Interface (SAS) switches, the plurality of SAS switches being connected to the plurality of diskless server nodes. The architecture further includes a storage system, the storage system configured for being communicatively coupled to the plurality of servers via the plurality of SAS switches. Further, the storage system is configured for implementing Controlled Replication Under Scalable Hashing (CRUSH) redundancy. Still further, the architecture is configured for dynamically mapping data stores of the storage system to the diskless server nodes. | 01-19-2012 |
| 20120011484 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED TIMING-REALIZABLE CLOCK-INSERTION DELAYS AND INTEGRATED CIRCUIT DESIGN TOOLS - A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool. | 01-12-2012 |
| 20120011483 | METHOD OF CHARACTERIZING REGULAR ELECTRONIC CIRCUITS - A methods of characterizing a regular electronic circuit and using a parameterized model of an electronic circuit to create a model for another electronic circuit. In one embodiment, the method of characterizing includes: (1) characterizing fewer than all sub-circuits associated with input and output pins of the circuit to yield data regarding the sub-circuits, (2) generating a data file containing the data, the data file constituting an expandable parameterized model of the circuit. | 01-12-2012 |
| 20120008450 | FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD OF IMPLEMENTING THE SAME IN AN INTEGRATED CIRCUIT - A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least one data and bit enable merging block and at least one merged data register block, (2) one of: (2a) at least one address input register block and at least one binary to one-hot address decode block and (2b) at least one binary to one-hot address decode block and at least one one-hot address register block and (3) a memory array, at least one of the blocks having a timing selected to match at least some timing margins outside of the memory. | 01-12-2012 |
| 20120005669 | MANAGING PROTECTED AND UNPROTECTED DATA SIMULTANEOUSLY - A first virtual device is created including every logically addressable unit of a data storage server that utilizes data protection. A second virtual device is created including no logically addressable unit of the data storage server that utilizes data protection. Data transfers are disabled within all command phases of the first virtual device. | 01-05-2012 |
| 20120005552 | ON-LINE DISCOVERY AND FILTERING OF TRAPPING SETS - A communication system (e.g., a hard drive) having a random-access memory (RAM) for storing trapping-set (TS) information that the communication system generates on-line during a special operating mode, in which low-density parity-check (LDPC)-encoded test codewords are written to a storage medium and then read and decoded to discover trapping sets that appear in candidate codewords produced by an LDPC decoder during decoding iterations. The discovered trapping sets are filtered to select a subset of trapping sets that satisfy specified criteria. The discovery and filtering of trapping sets is performed based on error vectors that are calculated using the a priori knowledge of original test codewords. The TS information corresponding to the selected subset is stored in the RAM and accessed as may be necessary to break the trapping sets that appear in candidate codewords produced by the LDPC decoder during normal operation of the communication system. | 01-05-2012 |
| 20120005551 | BREAKING TRAPPING SETS USING TARGETED BIT ADJUSTMENT - In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if the number of unsatisfied check nodes exceeds a specified threshold, then a second stage is performed. The post processor initializes the decoder by saturating the LLR values output by the decoder during the last (i.e., failed) iteration of the first stage to a relatively small value. The second stage then performs single-bit adjustment trials, wherein one LLR value corresponding to one bit of the codeword is adjusted in each trial. | 01-05-2012 |
| 20110320997 | Delay-Cell Footprint-Compatible Buffers - A method for creating a design for an integrated circuit, by developing a set of delay cells where each of the cells in the set has a different delay time from the other cells in the set, and where each of the cells in the set has the same surface area, has the same pin-outs, has the same drive strength, and has the same input capacitance, where an originally-used cell in the set can be swapped out for a different replacement cell in the set without any impact on the design of the integrated circuit besides a change in delay time from the originally-used cell to the replacement cell. | 12-29-2011 |
| 20110320902 | CONDITIONAL SKIP-LAYER DECODING - In one embodiment, a turbo equalizer is selectively operable in either first or second modes. In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft-output values generated by a channel detector, where, for each full local decoder iteration, the updates of one or more layers of the corresponding H-matrix are skipped. If decoding fails to converge on a valid LDPC-encoded codeword and a specified condition is met, then LDPC decoding is performed in a second mode, where the updates of all of the layers of the H-matrix are performed for each full local decoder iteration, including the one or more layers that were previously skipped in the first mode. Skipping one or more layers in the first mode increases throughput of the decoder, while updating all layers in the second mode increases error correction capabilities of the decoder. | 12-29-2011 |
| 20110316504 | Power Supply Noise Injection - A method for reducing noise in an output of a voltage regulator at frequencies above a closed loop bandwidth, by providing a noise injection path for injecting external noise into the voltage regulator, where the noise injection path becomes active at the frequencies above the closed loop bandwidth, where the noise injection path reduces the noise in the output of the voltage regulator. | 12-29-2011 |
| 20110314218 | PARITY-BASED RAID SYSTEM CONFIGURED TO PROTECT AGAINST DATA CORRUPTION CAUSED BY THE OCCURRENCE OF WRITE HOLES - A RAID system is provided in which the RAID controller of the system causes a predetermined number, N, of IO commands to be queued in a memory element, where N is a positive integer. After the N IO commands have been queued, the RAID controller writes N locks associated with the N IO commands in parallel to a service memory device. The RAID controller then writes N stripes of data and parity bits associated with the N IO commands to the PDs of the system to perform striping and parity distribution. If a catastrophic event, such as a power failure, occurs, the RAID controller reads the locks from the service memory device and causes parity to be reconstructed for the stripes associated with the locks. These features improve write performance while preventing the occurrence of data corruption caused by write holes. | 12-22-2011 |
| 20110314209 | DIGITAL SIGNAL PROCESSING ARCHITECTURE SUPPORTING EFFICIENT CODING OF MEMORY ACCESS INFORMATION - A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value register to store an initial adjustment value and a succeeding adjustment value. The digital signal processor may also include an address generator circuit to retrieve an instruction including a memory address value that is greater than N, and a further instruction including a further memory address value that is less than or equal to N. In addition, the digital signal processor may include a memory, which includes a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N. The address generator circuit may access the high bank address space, using initial adjustment value and the memory address value, or using the succeeding adjustment value and the further memory address value. | 12-22-2011 |
| 20110311853 | ELECTROCHEMICAL CELL SYSTEM AND APPARATUS TO PROVIDE ENERGY TO A PORTABLE ELECTRONIC DEVICE - A planar galvanic cell arrangement for portable electronic device is provided. In one embodiment, a galvanic cell arrangement may include a flexible substrate including a surface area that forms a plane. The galvanic cell arrangement also includes a plurality of galvanic cells coupled with the flexible substrate within the surface area that forms the plane, and electrically connected with one another in series, each of the plurality of galvanic cells including a negative electrode and a positive electrode. Furthermore, the galvanic cell arrangement includes a first terminal coupled with the negative electrode at one end of the series, and second terminal coupled with the positive electrode at an opposite end of the series. The plurality of galvanic cells being configured to provide electrical power to the portable electronic device via the first and second terminal, based on the plurality of galvanic cells being exposed to an aqueous electrolyte. | 12-22-2011 |
| 20110311002 | Turbo-Equalization Methods For Iterative Decoders - Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (L | 12-22-2011 |
| 20110310691 | Multi-Port Memory Using Single-Port Memory Cells - A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle. | 12-22-2011 |
| 20110298502 | Switching Clock Sources - A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output. | 12-08-2011 |
| 20110298026 | LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS - An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included. | 12-08-2011 |
| 20110292612 | ELECTRONIC DEVICE HAVING ELECTRICALLY GROUNDED HEAT SINK AND METHOD OF MANUFACTURING THE SAME - An electronic device includes an integrated circuit (IC) package attached to a substrate and a heat sink attached to the IC package. Additionally, the electronic device also includes a film having an electric conductivity and contacting the heat sink and the IC package and extending to the substrate to provide a grounding connection for the heat sink. A method of manufacturing an electronic device includes connecting an IC package to a substrate, coupling a heat sink to the IC package and depositing a film having an electric conductivity and contacting the heat sink and the IC package and extending to the substrate to provide a grounding connection for the heat sink. | 12-01-2011 |
| 20110286511 | DATA LATCH CIRCUIT AND METHOD OF A LOW POWER DECISION FEEDBACK EQUALIZATION (DFE) SYSTEM - Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback. | 11-24-2011 |
| 20110283075 | METHOD AND SYSTEM FOR DYNAMIC STORAGE TIERING USING ALLOCATE-ON-WRITE SNAPSHOTS - A method for dynamic storage tiering may comprise: detecting a storage hot-spot located in a first storage pool; and creating a first point-in-time copy of a virtual volume including the storage hot-spot located in the first storage pool in a second storage pool according to the detecting. | 11-17-2011 |
| 20110282842 | DATA PROTECTION IN A DATA STORAGE SYSTEM - Systems and methods herein provide for protecting data using snapshots and images of those snapshots to quickly recreate data upon request. For example, a storage controller of a data storage system allocates a period of time between creating snapshots of data in a first storage volume of the data storage system. The controller then logs received write requests to the first storage volume and generates snapshot of data in the first storage volume based on the allocated period of time. Thereafter, the controller may receive a request to recreate data. The controller locates the snapshot in the first storage volume based on that request to recreate the data. In doing so, the controller generates a snapshot image in a second storage volume. The controller then retrieves logged write requests and applies them to the snapshot image to recreate the data in the second storage volume. | 11-17-2011 |
| 20110279171 | ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT IDENTIFICATION, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT INCORPORATING THE SAME - An electrically programmable fuse controller, a method of controlling a drive voltage of an integrated circuit (IC) and an IC incorporating the controller or the method. In one embodiment, the controller includes a VID eFuse controller configured to receive and write a voltage identifier to an associated eFuse and thereafter allow the voltage identifier to be read from the eFuse and employed to set a drive voltage of an integrated circuit associated with the VID eFuse controller. | 11-17-2011 |
| 20110267946 | WINDOWING TECHNIQUE FOR ADAPTIVE CLOCK RECOVERY AND OTHER SIGNAL-PROCESSING APPLICATIONS - In one embodiment, an adaptive clock recovery (ACR) system generates a current delay-offset estimate value (D | 11-03-2011 |
| 20110264979 | ERROR-CORRECTION DECODER EMPLOYING EXTRINSIC MESSAGE AVERAGING - In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets. | 10-27-2011 |
| 20110261917 | Time Synchronization Using Packet-Layer and Physical-Layer Protocols - In certain embodiments, a slave node in a packet network achieves time synchronization with a master node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure. The packet-layer synchronization procedure may be selectively employed to adjust the slave's local time (if needed) after significant periods of time (e.g., substantially greater than one second). Both the packet-layer synchronization procedure and the physical-layer syntonization procedure are traceable to a common reference timescale (e.g., UTC). Depending on the implementation, the packet-layer synchronization procedure can be, but does not have to be, terminated when not being employed to adjust the slave's local time. | 10-27-2011 |
| 20110260324 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE - A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers. | 10-27-2011 |
| 20110258587 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist. | 10-20-2011 |
| 20110258480 | METHODS AND APPARATUS FOR MANAGING ASYNCHRONOUS DEPENDENT I/O FOR A VIRTUAL FIBRE CHANNEL TARGET - Methods and apparatus for managing exchange IDs for multiple asynchronous dependent I/O operations generated for virtual Fibre Channel (FC) target volumes. Features and aspects hereof allocate a range of exchange identifier (X_ID) values used in issuing a plurality of physical I/O operations to a plurality of physical FC target devices that comprise the virtual FC target volume. The plurality of physical I/O operations are dependent upon one another for completion of the original request to the virtual FC target volume and allow substantially parallel operation of the plurality of physical FC target devices. A primary X_ID is selected from the range of allocated X_ID values for communications with the attached host system that generated the original request to the virtual FC target volume. | 10-20-2011 |
| 20110258376 | METHODS AND APPARATUS FOR CUT-THROUGH CACHE MANAGEMENT FOR A MIRRORED VIRTUAL VOLUME OF A VIRTUALIZED STORAGE SYSTEM - Methods and apparatus for cut-through cache memory management in write command processing on a mirrored virtual volume of a virtualized storage system, the virtual volume comprising a plurality of physical storage devices coupled with the storage system. Features and aspects hereof within the storage system provide for receipt of a write command and associated write data from an attached host. Using a cut-through cache technique, the write data is stored in a cache memory and transmitted to a first of the plurality of storage devices as the write data is stored in the cache memory thus eliminating one read-back of the write data for transfer to a first physical storage device. Following receipt of the write data and storage in the cache memory, the write data is transmitted from the cache memory to the other physical storage devices. | 10-20-2011 |
| 20110255689 | MULTIPLE-MODE CRYPTOGRAPHIC MODULE USABLE WITH MEMORY CONTROLLERS - In one embodiment, a multi-mode Advanced Encryption Standard (MM-AES) module for a storage controller is adapted to perform interleaved processing of multiple data streams, i.e., concurrently encrypt and/or decrypt string-data blocks from multiple data streams using, for each data stream, a corresponding cipher mode that is any one of a plurality of AES cipher modes. The MM-AES module receives a string-data block with (a) a corresponding key identifier that identifies the corresponding module-cached key and (b) a corresponding control command that indicates to the MM-AES module what AES-mode-related processing steps to perform on the data block. The MM-AES module generates, updates, and caches masks to preserve inter-block information and allow the interleaved processing. The MM-AES module uses an unrolled and pipelined architecture where each processed data block moves through its processing pipeline in step with correspondingly moving key, auxiliary data, and instructions in parallel pipelines. | 10-20-2011 |
| 20110249361 | FLY-HEIGHT CONTROL USING ASYNCHRONOUS SAMPLING - In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed. | 10-13-2011 |
| 20110246423 | METHOD FOR IMPLEMENTING MULTI-ARRAY CONSISTENCY GROUPS USING A WRITE QUEUING MECHANISM - A method for implementing multi-array consistency groups includes applying a write Input/Output (I/O) queue interval to a Logical Unit (LU) member of a consistency group (CG). The method also includes marking each write I/O with a timestamp and suspending I/O from the participating storage array to the LU member of the CG upon the participating storage array receiving a snapshot request from a master storage array. The method further includes determining whether the snapshot request timestamp is within the write I/O queue interval of the participating storage array. | 10-06-2011 |
| 20110239171 | Staged Scenario Generation - A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage. | 09-29-2011 |
| 20110238938 | EFFICIENT MIRRORING OF DATA ACROSS STORAGE CONTROLLERS - A method includes multicasting an Input/Output (I/O) data associated with a host computing device through a multicast device associated with a storage controller coupled to another storage controller in a redundant configuration, and minoring, through the multicasting, the I/O data across the storage controller and the another storage controller through a bus utilized to couple the storage controller and the another storage controller. The method also includes transmitting an early write status message to the host computing device following the minoring of the I/O data across the storage controller and the another storage controller. The early write status message is associated with a successful completion of the mirroring of the I/O data across the storage controller and the another storage controller prior to the I/O data being written to a storage device associated therewith. | 09-29-2011 |
| 20110235490 | AMPLITUDE-BASED APPROACH FOR DETECTION AND CLASSIFICATION OF HARD-DISC DEFECT REGIONS - In a hard-disc drive, a defect region on the hard disc is classified as corresponding to either thermal asperity (TA) or media defect (MD) by generating two statistical measures. A first measure (e.g., ∝ | 09-29-2011 |
| 20110235204 | DETECTION OF HARD-DISC DEFECT REGIONS USING SOFT DECISIONS - In a hard-disc drive, a defect region on the hard disc is detected by generating two statistical measures (e.g., β | 09-29-2011 |
| 20110231673 | CRYPTOGRAPHIC PROCESSING USING A PROCESSOR - In one embodiment, a cryptography processor compatible with the Advanced Encryption Standard (AES) for encrypting and decrypting has a memory storing each element of an AES State, normally 8-bit long, in a corresponding memory space that is at least 9 bits long. Using the larger memory spaces, the processor performs modified AES transformations on the State. A modified column-mixing transformation uses bit-shifting and XOR operations, thereby avoiding some multiplications and modulo reductions and resulting in some 9-bit State elements. A modified byte-substitution transformation uses a 512-element look-up table to accommodate 9-bit inputs. The modified byte-substitution transformation is combined with a modified row-shifting transformation. The memory has data registers each holding four State elements. A modified expanded key schedule is used in a modified round-key-adding transformation that is combined with the modified column-mixing transformation, wherein all four elements stored in a single data register are processed together in some operations. | 09-22-2011 |
| 20110231571 | SAS DOMAIN MANAGEMENT AND SSP DATA HANDLING OVER ETHERNET - A server application is executed on an active device within the SAS domain, the active device connected to a remote client via an Ethernet connection. At least one command is received from the remote client via the Ethernet connection. An Ethernet frame of the at least one command is converted to at least one SAS frame. The at least one SAS frame is routed via a SAS data path to a SAS target device connected to the active device, the SAS target device corresponding to a field of the command. | 09-22-2011 |
| 20110225589 | EXCEPTION DETECTION AND THREAD RESCHEDULING IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR - Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor. | 09-15-2011 |
| 20110225453 | SYSTEM AND METHOD FOR OPTIMIZING REDUNDANCY RESTORATION IN DISTRIBUTED DATA LAYOUT ENVIRONMENTS - The present disclosure is directed to a system and a method for optimizing redundancy restoration in distributed data layout environments. The system may include a plurality of storage devices configured for providing data storage. The system may include a prioritization module communicatively coupled to the plurality of storage devices. The prioritization module may be configured for determining a restoration order of at least a first data portion and a second data portion when a critical data failure occurs. The system may include a restoration module communicatively coupled to the plurality of storage devices and the prioritization module, the restoration module configured for restoring at least the first data portion and the second data portion based upon the restoration order. | 09-15-2011 |
| 20110225391 | HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table. | 09-15-2011 |
| 20110225371 | DATA PREFETCH FOR SCSI REFERRALS - A method for communication between an initiator system and a storage cluster. The method comprises receiving an initial I/O request from the initiator system to a first storage system; providing a referral response from the first storage system to the initiator system, the referral response providing information for directing the initiator system to a second storage system; notifying the second storage system regarding the referral response via a prefetch notice, the prefetch notice including an operation type and address information for accessing requested data; when the initial I/O request is a read request, prefetching at least a portion of the requested data stored in the second storage system in to a cache; receiving a second I/O request from the initiator system to the second storage system; and providing to the initiator system the portion of the prefetched data from the cache of the second storage system. | 09-15-2011 |
| 20110225168 | HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide coherent processing of hash operations of a network processor having a plurality of processing modules. A hash processor of the network processor receives hash operation requests from the plurality of processing modules. A hash table identifier and bucket index corresponding to the received hash operation request are determined. An active index list is maintained for active hash operations for each hash table identifier and bucket index. If the hash table identifier and bucket index of the received hash operation request are in the active index list, the received hash operation request is deferred until the hash table identifier and bucket index corresponding to the received hash operation request clear from the active index list. Otherwise, the active index list is updated with the hash table identifier and bucket index of the received hash operation request and the received hash operation request is processed. | 09-15-2011 |
| 20110219161 | SYSTEM AND METHOD FOR PROVIDING ADDRESS DECODE AND VIRTUAL FUNCTION (VF) MIGRATION SUPPORT IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) MULTI-ROOT INPUT/OUTPUT VIRTUALIZATION (IOV) ENVIRONMENT - The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value. The method may further include constructing a requestor ID for the VF associated with the matching base address value, the requestor ID being based upon the output matching base address value and a bus number for a PF which owns the CAM. | 09-08-2011 |
| 20110215410 | I/O and Power ESD Protection Circuits By Enhancing Substrate-Bias in Deep-Submicron CMOS Process - A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps. | 09-08-2011 |
| 20110211582 | Interconnects using Self-timed Time-Division Multiplexed Bus - A method of sending signals, including data and timing information, between transportation units on a communication bus of an integrated circuit, by generating clock triggers for every transportation unit on the bus, thereby initiating each preceding one of the transportation units to start sending the signals in a wave-front to an adjacent succeeding one of the transportation units, where the wave-front is initiated at each of the transportation units at a common point in time, and every transportation unit applying a timing adjustment to at least one of the data and timing information that it receives in the signals from the preceding transportation unit, to at least one of (1) capture the data from the preceding transportation unit, (2) relay the data without modification from the preceding transportation unit to the succeeding transportation unit on the communication bus, and (3) load new data to the communication bus, with updated timing information in a succeeding wave-front. | 09-01-2011 |
| 20110202728 | METHODS AND APPARATUS FOR MANAGING CACHE PERSISTENCE IN A STORAGE SYSTEM USING MULTIPLE VIRTUAL MACHINES - Methods and systems for assuring persistence of battery backed cache memory in a storage system comprising multiple virtual machines. In one exemplary embodiment, an additional process is added to the storage controller that senses the loss of power and copies the entire content of the cache memory including portions used by each of the multiple virtual machines to a nonvolatile persistent storage that does not rely on the battery capacity of the storage system. In another exemplary embodiment, the additional process calls a plug-in procedure associated with each of the virtual machines to permit the virtual machine to assure that the content of its portion of the cache memory is consistent before the additional process copies the cache memory to nonvolatile memory. The additional process may be integrated with the hypervisor or may be operable as a separate process in yet another virtual machine. | 08-18-2011 |
| 20110202721 | REDUNDANT ARRAY OF INDEPENDENT STORAGE - A data storage system includes three or more storage devices, each associated with a unique data volume. A first one of the data storage devices at least has two or more data storage areas but can have more storage areas, which can be either data storage areas or parity storage areas. A second data storage device at least has two storage areas, one of which is a data storage area. A third data storage device at least has a parity storage area but can have more storage areas, which can be either data storage areas or parity storage areas. A first group of corresponding storage areas is defined by at least the data storage areas of the first and second storage devices and the parity storage area of the third storage device. A second group of corresponding storage areas is defined by at least the storage areas of the first and second storage devices. When a data segment is written to one of the data storage areas of a storage device, parity information can be updated using information read from one or more storage areas of the group of corresponding storage areas having the data storage area to which the data segment is written. | 08-18-2011 |
| 20110200147 | HIGH-PERFORMANCE TONE DETECTION USING A DIGITAL SIGNAL PROCESSOR (DSP) HAVING MULTIPLE ARITHMETIC LOGIC UNITS (ALUS) - In one embodiment, a DSP having four arithmetic logic units (ALUs) and able to have two read/write operations per clock cycle performs silence detection and tone detection for data frames containing samples of an audio signal. The ALUs are used together in parallel to process the samples in the data frames received by the DSP. A received data frame is filtered by the silence detection so that substantially silent frames are dropped and non-silent frames are further processed. In the tone detection, a filtered data frame is processed, four samples at a time, to determine the power of the signal at a given frequency, where the power determination is used to determine whether a given tone (i.e., a signal at a given frequency) is present in the data frame. | 08-18-2011 |
| 20110199699 | FREQUENCY-BASED APPROACH FOR DETECTION AND CLASSIFICATION OF HARD-DISC DEFECT REGIONS - In a hard-disc drive read channel, frequency-based measures are generated at two different data frequencies (e.g., 2T and DC) by applying a transform, such as a discrete Fourier transform (DFT), to signal values, such as ADC or equalizer output values, corresponding to, e.g., a 2T data pattern stored on the hard disc. The frequency-based measures are used to detect defect regions on the hard disc and/or to classify defect regions as being due to either thermal asperity (TA) or drop-out media defect (MD). | 08-18-2011 |
| 20110197027 | SYSTEM AND METHOD FOR QoS-BASED STORAGE TIERING AND MIGRATION TECHNIQUE - The present invention is directed to a method for providing Quality Of Service (QoS)-based storage tiering and migration in a storage system. The method allows for configurable application data latency thresholds to be set on a per user basis and/or a per application basis so that a storage tiering mechanism and/or a storage migrating mechanism may be triggered for moving application data to a different class of storage. | 08-11-2011 |
| 20110185156 | EXECUTING WATCHPOINT EVENTS FOR DEBUGGING IN A "BREAK BEFORE MAKE" MANNER - A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the instruction in which the watchpoint event occurred, while the instruction and subsequent instructions are cancelled, keeping the hardware components associated with executing the program in their previous states, prior to the watchpoint. The rewind is such that the program is refetched to enable execution to continue from the instruction in which the watchpoint event occurred. The watchpoint event is executed in a “break before make” manner. | 07-28-2011 |
| 20110185120 | METHOD FOR PLACEMENT OF VIRTUAL VOLUME HOT-SPOTS IN STORAGE POOLS USING ONGOING LOAD MEASUREMENTS AND RANKING - The present invention is directed to a method for providing data element placement in a storage system via a Dynamic Storage Tiering (DST) mechanism, such that improved system efficiency is promoted. For example, the DST mechanism may implement an algorithm for providing data element placement. The data elements (ex.—virtual volume hot-spots) may be placed into storage pools, such that usage of higher performing storage pools is maximized. Hot-spots may be detected by dynamically measuring load on LBA ranges. Performance of the storage pools may be measured on an ongoing basis. Further, the hot-spots may be ranked according to load, while storage pools may be ranked according to measured performance. If a hot-spot's load decreases, the hot-spot may be moved to a lower performing storage pool. If a hot-spot's load increases, the hot-spot may be moved to a higher performing storage pool. | 07-28-2011 |
| 20110185099 | Modular and Redundant Data-Storage Controller And a Method for Providing a Hot-Swappable and Field-Serviceable Data-Storage Controller - A modular and redundant storage controller system includes management modules, controller modules and an interconnect module. The management modules provide direct-current power and signals to respective controller modules. The controller modules include respective signal interfaces, direct-current interfaces, and interconnect interfaces. The signal interfaces couple the controllers to a respective management module. The direct-current interfaces couple the controllers to a respective management module. The interconnect module includes a pair of connectors arranged to couple a pair of the controller modules via the respective interconnect module interfaces. | 07-28-2011 |
| 20110176278 | INTEGRATED HEAT SINK - An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate. | 07-21-2011 |
| 20110173510 | Parallel LDPC Decoder - An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations. | 07-14-2011 |
| 20110169254 | ACTIVE-ACTIVE FAILOVER FOR A DIRECT-ATTACHED STORAGE SYSTEM - Airbag inflators employ gas generating compositions formed from a mixture of fuels and a mixture of oxidizers and preferably mica at levels of 1 to 5% by weight. The gas generant composition contains a primary and secondary fuel. The primary fuel is a guanidine compound, preferably guanidine nitrate. The secondary fuel is selected from tetrazoles, triazoles and mixtures thereof at levels of 5% by weight or less of the total gas generant composition. The oxidizer system is a mixture of at least two components selected from the group consisting of transition metal oxides, alkali metal nitrates and alkaline earth metal nitrates. The novel gas generants yield inflating gases having a reduced content of undesirable gases such as nitrous oxides and carbon monoxide. | 07-14-2011 |
| 20110164630 | ADAPTIVE CLOCK RECOVERY WITH STEP-DELAY PRE-COMPENSATION - An adaptive clock recovery (ACR) subsystem processes an input phase signal indicative of jittery packet arrival times to generate a relatively smooth and bounded output phase signal that can be used to generate a relatively stable recovered clock signal. The input phase signal is also processed to detect and measure step-delays corresponding, for example, to path changes in the network routing of the packets. Step-delay pre-compensation is performed, in which the input phase signal is phase-adjusted, upstream of the ACR subsystem, based on the sign and magnitude of each detected step-delay. As a result, the ACR subsystem is substantially oblivious to the existence of such step-delays. | 07-07-2011 |
| 20110164627 | THREE-STAGE ARCHITECTURE FOR ADAPTIVE CLOCK RECOVERY - An adaptive clock recovery (ACR) system has a first closed-loop control processor (e.g., a first proportional-integral (PI) processor) that processes an input phase signal indicative of jittery packet arrival times to generate a mean phase reference. The input phase signal is compared to the mean phase reference to generate delay-offset values that are indicative of the delay-floor corresponding to the packet arrival times. The mean phase reference and the delay-offset values are used to generate offset-compensated phase values corresponding to the delay-floor. The ACR system also has a second closed-loop control processor (e.g., a second PI processor) that smoothes the offset-compensated phase values to generate an output phase signal that can be used to generate a relatively phase stable recovered clock signal, even during periods of varying network load that adversely affect the uniformity of the packet arrival times. | 07-07-2011 |
| 20110161649 | SYSTEMS AND METHODS FOR BOOTING A BOOTABLE VIRTUAL STORAGE APPLIANCE ON A VIRTUALIZED SERVER PLATFORM - One embodiment is a method for booting a bootable virtual storage appliance on a virtualized server platform. One such method comprises: providing a virtual storage appliance on a server platform, the virtual storage appliance configured to manage a disk array comprising a plurality of disks, and wherein at least one of the disks comprises a hidden boot partition having a boot console; powering up the server platform; loading boot code on the server platform; loading the boot console from the hidden boot partition; and the boot console loading boot components for a virtualization environment. | 06-30-2011 |
| 20110145487 | Methods and Apparatus for Soft Demapping and Intercell Interference Mitigation in Flash Memories - Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step. | 06-16-2011 |
| 20110145452 | METHODS AND APPARATUS FOR DISTRIBUTION OF RAID STORAGE MANAGEMENT OVER A SAS DOMAIN - Methods and apparatus for distributing Redundant Array of Independent Disks (RAID) storage management to one or more Serial Attached SCSI (SAS) expanders in a SAS domain. A RAID set comprises a set of one or more SAS expanders coupled to communicate with one another to process I/O requests directed to a RAID logical volume of the RAID set. The RAID logical volume is distributed over portions of each of multiple storage devices. Each SAS expander of the RAID set is coupled to one or more of the multiple storage devices. Each SAS expander of the RAID set processes a corresponding portion of a received I/O request directed to the RAID logical volume. A master SAS expander of the RAID set receives and aggregates the status information from each of the SAS expanders of the RAID set and returns a completion status to the requesting SAS initiator. | 06-16-2011 |
| 20110141808 | Methods and Apparatus for Programming Multiple Program Values Per Signal Level in Flash Memories - Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance. | 06-16-2011 |
| 20110131463 | FORWARD SUBSTITUTION FOR ERROR-CORRECTION ENCODING AND THE LIKE - In one embodiment, a forward substitution component performs forward substitution based on a lower-triangular matrix and an input vector to generate an output vector. The forward substitution component has memory, a first permuter, an XOR gate array, and a second permuter. The memory stores output sub-vectors of the output vector. The first permuter permutates one or more previously generated output sub-vectors stored in the memory based on one or more permutation coefficients corresponding to a current block row of the lower-triangular matrix to generate one or more permuted sub-vectors. The XOR gate array performs exclusive disjunction on (i) the one or more permuted sub-vectors and (ii) a current input sub-vector of the input vector to generate an intermediate sub-vector. The second permuter permutates the intermediate sub-vector based on a permutation coefficient corresponding to another block in the current block row to generate a current output sub-vector of the output vector. | 06-02-2011 |
| 20110131462 | MATRIX-VECTOR MULTIPLICATION FOR ERROR-CORRECTION ENCODING AND THE LIKE - In one embodiment, a matrix-vector multiplication (MVM) component generates a product vector based on (i) an input matrix and (ii) an input vector. The MVM component has a permuter, memory, and an XOR gate array. The permuter permutates, for each input sub-vector of the input vector, the input sub-vector based on a set of permutation coefficients to generate a set of permuted input sub-vectors. The memory stores a set of intermediate product sub-vectors corresponding to the product vector. The XOR gate array performs, for each input sub-vector, exclusive disjunction on (i) the set of permuted input sub-vectors and (ii) the set of intermediate product sub-vectors to update the set of intermediate product subvectors, such that all of the intermediate product sub-vectors in the set are updated based on a current input sub-vector before updating any of the intermediate product sub-vectors in the set based on a subsequent input sub-vector. | 06-02-2011 |
| 20110126075 | ROM LIST-DECODING OF NEAR CODEWORDS - Certain embodiments of the present invention are methods for the organization of trapping-set profiles in ROM and for the searching of those profiles during (LDPC) list decoding. Profiles are ranked by dominance, i.e., by their impact on the error-floor characteristics of a decoder. More-dominant trapping-set profiles contain information about both unsatisfied check nodes (USCs) and mis-satisfied check nodes (MSCs), while less-dominant trapping-set profiles contain information about only USCs. Trapping-set profile information is organized into a number of linked, hierarchical data tables which allow for the rapid location and retrieval of most-dominant matching trapping-set profiles using a pointer-chase search. | 05-26-2011 |
| 20110123012 | CONTROLLING A CALL SETUP PROCESS - A call setup process ( | 05-26-2011 |
| 20110119553 | SUBWORDS CODING USING DIFFERENT ENCODING/DECODING MATRICES - In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices. | 05-19-2011 |
| 20110119056 | SUBWORDS CODING USING DIFFERENT INTERLEAVING SCHEMES - In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding interleavers/deinterleavers in the different subword-processing paths use different interleaving/deinterleaving algorithms. | 05-19-2011 |
| 20110113176 | BACK-OFF RETRY WITH PRIORITY ROUTING - A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander. | 05-12-2011 |
| 20110107129 | METHODS AND APPARATUS FOR LOAD-BASED POWER MANAGEMENT IN A STORAGE SYSTEM - Apparatus and method for managing power consumption of circuits within a Serial Attached SCSI (SAS) device. A SAS device having a plurality of PHY logic circuits includes a queue manager and a power manager. The queue manager is operable to determine a current workload based on queued entries for the plurality of PHY logic circuits. Based on the current workload, the power manager is operable to set identified ones of the plurality of PHY logic circuits into a low power mode. In some embodiments, PHY logic circuits may be restored to full power operation responsive to changes in the current workload and/or responsive to receipt of a signal from another SAS device coupled to the SAS device. In other embodiments the power manager is further operable to manage power consumption of link and/or DMA logic circuits of the SAS device. | 05-05-2011 |
| 20110106997 | METHODS AND APPARATUS FOR INTERCONNECTING SAS/SATA DEVICES USING EITHER ELECTRICAL OR OPTICAL TRANSCEIVERS - Methods and apparatus for interconnecting Serial Attached SCSI (SAS) or Serial Advanced Technology Attachment (SATA) devices using either an electrical communication medium or an optical communication medium. Each device includes an out of band (OOB) encoder/decoder (endec) logic component to translate between standard OOB signals used by the devices and digitally encoded OOB signals exchanged over the communication medium. Thus the devices may be coupled using either optical or electrical cabling. The digitally encoded OOB signals may also be scrambled to reduce electromagnetic interference (EMI) generated during OOB communications using the digitally encoded OOB signals. The scrambled digitally encoded OOB signals may comprise information regarding capabilities of the device that generated the underlying OOB signal. Such information may indicate to the other high speed device certain capabilities of the transmitting device—the information to be used in establishing logical connections between devices. | 05-05-2011 |
| 20110103527 | Phase Detector For Timing Recovery Loop - In one embodiment, a (hard-drive) read channel has a phase detector used in a timing recovery loop. The phase detector utilizes the sign bit and confidence value from a received log-likelihood ratio (LLR) signal to generate a mean value. The mean value is convolved with a partial response target to generate an estimated timing error signal. When implemented in a hard-drive read channel, the phase detector allows for timing recovery with lower loss-of-lock rates. | 05-05-2011 |
| 20110103439 | APPARATUS AND METHODS FOR IMPROVED HIGH-SPEED COMMUNICATION SYSTEMS - Apparatus and methods for improved high-speed communication by exchanging low-speed information regarding the high-speed exchanges over the same communication medium. In one exemplary embodiment, a communication device includes a high-speed transceiver adapted to exchange high-speed data with another device via a communication medium using high-frequency signals. The device also includes a low-speed component adapted to exchange low-speed information over the same communication medium as low-frequency signals. The low-frequency signals may be applied as common mode signals to a differential communication path so as to not interfere with the high-speed data exchanges. In another embodiment, a high-pass filter may be included in the device to remove the low-frequency signals before the high-speed data is applied to the high-speed transceiver. Responsive to receipt of the low-speed information, a device may adjust parameters of the transceiver to improve the high-speed data exchanges. | 05-05-2011 |
| 20110102048 | BIAS VOLTAGE GENERATION TO PROTECT INPUT/OUTPUT (IO) CIRCUITS DURING A FAILSAFE OPERATION AND A TOLERANT OPERATION - A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation. | 05-05-2011 |
| 20110099454 | Low Complexity LDPC Encoding Algorithm - A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form | 04-28-2011 |
| 20110084726 | ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS - A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value. | 04-14-2011 |
| 20110083992 | METHOD AND SYSTEM FOR PROVIDING A CUSTOMIZED STORAGE CONTAINER - A method and system for providing a customized storage container includes a generally rectangular housing and at least one printed circuit board contained within the rectangular housing. The customized storage container encloses a first row of interconnector modules that are positioned adjacent to a first, open end of the rectangular housing. The customized storage container also encloses a second row of interconnector modules positioned adjacent to the first, open end of the rectangular housing. At least one air vent is positioned along a side of the rectangular housing and adjacent to a second, closed end of the rectangular housing. According to one exemplary embodiment, the storage container can comprise a single printed circuit board for supporting the first and second row of interconnector modules. In another exemplary embodiment, the storage container can comprise two printed circuit boards for supporting the first and second rows interconnector modules. | 04-14-2011 |
| 20110078433 | SYSTEMS AND METHODS FOR INSTALLING A BOOTABLE VIRTUAL STORAGE APPLIANCE ON A VIRTUALIZED SERVER PLATFORM - One embodiment is a method for installing a virtual storage appliance on a host server platform. One such method comprises: providing an installation package to a host server platform, the installation package comprising an installation script for installing an I/O virtual machine (IOVM), an IOVM boot console, and an IOVM management module; running the installation script to create a hidden boot partition on a boot disk and copy the IOVM boot console and the IOVM management module to the hidden boot partition; rebooting the host server platform; loading the IOVM boot console and the IOVM management module from the hidden boot partition; configuring a disk array via the IOVM management module; for each disk in the array, creating a hidden boot partition and replicating the IOVM boot console and the IOVM management module; and installing a virtual storage environment using the IOVM boot console as a storage driver. | 03-31-2011 |
| 20110078398 | METHOD AND SYSTEM FOR DYNAMIC STORAGE TIERING USING ALLOCATE-ON-WRITE SNAPSHOTS - The present disclosure describes a systems and methods for dynamic storage tiering | 03-31-2011 |
| 20110075718 | Automatic Filter-Reset Mechanism - In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive. | 03-31-2011 |
| 20110072335 | BRANCH-METRIC CALIBRATION USING VARYING BANDWIDTH VALUES - In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another. | 03-24-2011 |
| 20110072224 | SNAPSHOT METADATA MANAGEMENT IN A STORAGE SYSTEM - Methods and systems for improving performance in a storage system utilizing snapshots are disclosed by using metadata management of snapshot data. Specifically, various metadata structures associated with snapshots are utilized to reduce the number of IO operations required to locate data within any specific snapshot. The number of IO operations are reduced by allowing the various metadata structures associated with the temporally current snapshot to locate data directly within any temporally earlier snapshot or on the original root volume. | 03-24-2011 |
| 20110066905 | Test Pin Gating for Dynamic Optimization - An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced. | 03-17-2011 |
| 20110063926 | Write Through Speed Up for Memory Circuit - A method of performing a write-through operation with a memory circuit having a write enable line, a write address line, a data in line, a read address line, a data out line, a bit array, a comparator, and a mux. A write address is received on the write address line, a read address is received on the read address line, data is received on the data in line. The comparator determines as a first condition whether the write address is identical to the read address, and determines as a second condition whether the write enable line is enabled. When both the first condition and the second condition are met, the comparator signals the mux to directly output the data receiving on the data in line on the data out line without writing the data to the bit array. In this manner, the memory circuit checks to determine whether a write-through operation is called for. If it is, then the mux sends the data on the data in line directly to the data out line, instead of retrieving data from the bit array of the memory, such as through the read decoder, which would take much longer. | 03-17-2011 |
| 20110058619 | SIGNAL PROCESSING USING MODIFIED BLOCKWISE ANALYTIC MATRIX INVERSION - In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M | 03-10-2011 |
| 20110055624 | METHOD FOR IMPLEMENTING CONTINUOUS DATA PROTECTION UTILIZING ALLOCATE-ON-WRITE SNAPSHOTS - The present disclosure is directed to a method for providing continuous data protection for a virtual volume (VV). The method may comprise conceptually dividing the VV into a plurality of same sized chunks; preserving contents of the VV at a specified time; creating a Point in Time (PiT) instance for the VV at the specified time, comprising: a PiT Temporary Virtual Volume (PTVV) for storing modifications to the VV subsequent to the specified time, wherein data stored in the PTVV is prohibited from been overwritten; a re-allocation table for providing read access to a most recent version of each of the plurality of chunks of the VV; and a Continuous Data Protection (CDP) log for providing read access to a historic version of a chunk stored in the PTVV; and updating the PiT instance when a chunk of the plurality of chunks of the VV is being modified. | 03-03-2011 |
| 20110055174 | STORAGE SYSTEM DATA COMPRESSION ENHANCEMENT - Data segments are logically organized in clusters in a data repository of a data storage system. Each clusters contains compressed data segments and data common to the compression of the segments, such as a dictionary. In association with a write request, it is determined in which of the clusters would the data segment most efficiently be compressed, and the data segment is stored in that data cluster. | 03-03-2011 |
| 20110051304 | DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING CAPACITORS - An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail. | 03-03-2011 |
| 20110040903 | METHODS AND APPARATUS FOR AUTOMATED PERFORMANCE LIMITING OF AN I/O CONTROL DEVICE - Methods and apparatus for configurably limiting performance of an I/O controller device in processing of I/O requests. A performance monitor and control module in the I/O controller device monitors performance of the I/O request processing module and limits its processing to assure that maximum performance threshold values are not exceeded. In one embodiment, the performance monitoring may average performance over one or more periods of time and may provide a moving average window to determine the performance of the I/O controller device. The measured performance may determine a variety of performance measures each of which may be compared against one or more corresponding maximum performance threshold values. Requests that cannot be processed during a present period of time are delayed until a subsequent period of time to thereby limit performance of the I/O controller device. | 02-17-2011 |
| 20110039398 | EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A NANOTUBE STRUCTURE - Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semiconductor substrate. The transistor layer above the semiconductor substrate may comprise a plurality of transistors. The method also includes supplying power to the plurality of transistors through one or more power sources. In addition, the method includes coupling the plurality of transistors in the transistor layer to the one or more power sources based on a state of the nanotube structure. | 02-17-2011 |
| 20110033037 | ADAPTIVE FILTERING WITH FLEXIBLE SELECTION OF ALGORITHM COMPLEXITY AND PERFORMANCE - An adaptive filter configured to use multiple algorithm species that differ in the quality of echo suppression and respective burdens imposed on the computational resources of the host communication device. Depending on the available computational budget, the adaptive filter selects an algorithm species that, while supporting a relatively high quality of echo suppression, involves a relatively low risk of overwhelming the computational resources. The adaptive filter monitors changes in the available computational budget and, if appropriate or necessary, can change the algorithm species to maintain a quality of echo suppression that is optimal for the current computational budget. If a change of the algorithm species is initiated, then at least a portion of internal algorithm data from the previously running algorithm species might be transferred for use in the subsequent algorithm species. | 02-10-2011 |
| 20110029787 | METHODS AND APPARATUS FOR POWER ALLOCATION IN A STORAGE SYSTEM - Methods and systems for improved management of power allocation among a plurality of devices coupled to a controller. The controller and devices exchange messages to request, grant, and release allocations of power from a common power supply. In some embodiments, the controller may be a SAS/SATA controller and the messages exchanged may be SAS/SATA frames and/or primitives. In exemplary embodiments, the messages may request/grant a particular amount of power for each of one or more voltage levels provided by the power supply. In other exemplary embodiments, the messages may designate the duration of time during which the requesting device may utilize the allocated power. A power status message from the device to the controller may indicate a change in the power consumption by the device. Responsive to the power status message the controller may re-allocate power previously allocated to a device that has completed use thereof. | 02-03-2011 |
| 20110029729 | ERASURE CODED DATA STORAGE CAPACITY AND POWER MANAGEMENT - A set of data is allocated into a plurality of data chunks, wherein the plurality of data chunks is thinly provisioned and erasure coded. A plurality of storage devices is divided into a first and a second set of storage devices, wherein the first set of storage devices is powered up and the second set of storage devices is powered down. The data chunks are distributed on the first set of storage devices to equally load each of the first set of storage devices. A storage device from the second set of storage devices is powered up to reassign the storage device from the second set of storage devices to the first set of storage devices. Data chunks are migrated to a reassigned storage device until the data chunks are evenly distributed on the first set of storage devices and the reassigned storage device. | 02-03-2011 |
| 20110029728 | METHODS AND APPARATUS FOR REDUCING INPUT/OUTPUT OPERATIONS IN A RAID STORAGE SYSTEM - Methods and systems for managing RAID volumes are disclosed. Metadata is associated with storage devices that comprise a RAID volume. The metadata identifies each of a plurality of portions as being either initialized or non-initialized. The number of I/O operations performed by a storage controller coupled with the storage devices is reduced in response to a request for the RAID volume based on the metadata. | 02-03-2011 |
| 20110029580 | METHODS AND APPARATUS FOR METADATA MANAGEMENT IN A STORAGE SYSTEM - Methods and systems for metadata management in a storage system are disclosed. First level metadata is associated with a plurality of storage devices in a storage system. Entries in the first level metadata identify storage related attributes of corresponding portions on the plurality of storage devices. Entries in a second level metadata are associated with a corresponding plurality of entries in the first level metadata, where the second level metadata identifies metadata related attributes of the corresponding first level metadata entries. Responsive to receiving a request for a storage related attribute in the first level metadata table, the storage related attribute is derived from the second level metadata table, which reduces the first level metadata processing requirements and increases the performance of the storage system. | 02-03-2011 |
| 20110025393 | Leakage Power Optimized Structure - A digital latch circuit substantially reduces leakage current in output stages of edge-triggered digital switching devices. The circuit comprises first and second NAND gates for receiving first and second input signals and providing first and second output signals. The first NAND gate includes a first A input for receiving the first input signal, a first B input connected to a second NAND gate output, a first leakage current control input connected to a second A input of the second NAND gate, and a first NAND gate output for providing the first output signal. The second NAND gate includes the second A input for receiving the second input signal, a second B input connected to the first NAND gate output, a second leakage current control input connected to the first A input of the first NAND gate, and the second NAND gate output for providing the second output signal. The leakage current through the first NAND gate is substantially reduced based on application of the second input signal to the first leakage current control input. Similarly, the leakage current through the second NAND gate is substantially reduced based on application of the first input signal to the second leakage current control input. This circuit may comprise a set-reset latch in an output stage of an edge-triggered sequential switching device, such as a D flip-flop or a JK master-slave flip-flop. | 02-03-2011 |
| 20110023004 | ESTABLISHING BENCHMARKS FOR ANALYZING BENEFITS ASSOCIATED WITH VOLTAGE SCALING, ANALYZING THE BENEFITS AND AN APPARATUS THEREFOR - Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining. | 01-27-2011 |
| 20110023000 | GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS - A method of generating a floorplan layout of an integrated circuit (IC) that is amenable to implementation in a computer-aided design tool. The method is capable of performing placement and routing processing for the IC while requiring very little information about the specific circuitry used in various functional blocks of the IC. For example, at the time of the placement and routing processing, one or more functional blocks of the IC can be specified as empty functional blocks and/or functional blocks that are only partially rendered in gates. | 01-27-2011 |
| 20110022998 | METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD - Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor. | 01-27-2011 |
| 20110022736 | METHODS AND APPARATUS DYNAMIC MANAGEMENT OF MULTIPLEXED PHYS IN A SERIAL ATTACHED SCSI DOMAIN - Methods and systems for automatically, dynamically reconfiguring multiplexing functions of a PHY of a SAS device in response to monitored performance of the PHY and/or in response to changes in configuration of devices in the SAS domain. A SAS device such as a SAS initiator or a SAS expander in a SAS domain may monitor performance of PHYs of the device to detect bandwidth utilization and may reconfigure multiplexing functions of a PHY to improve bandwidth utilization of the PHYs of the device. The device may also detect changes in the topology of the SAS domain such as addition of new devices or removal of device and adjust multiplexing functions of its PHYs accordingly to improve performance of communications in the SAS domain. | 01-27-2011 |
| 20110016436 | Digitally Obtaining Contours of Fabricated Polygons - The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons. | 01-20-2011 |
| 20110016272 | VIRTUALIZED DATA STORAGE IN A NETWORK COMPUTING ENVIRONMENT - Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device. | 01-20-2011 |
| 20110016260 | MANAGING BACKUP DEVICE METADATA IN A HIGH AVAILABILITY DISK SUBSYSTEM - A system includes a data storage device, a controller coupled with the data storage device, a backup device coupled with the controller for backing up a modified portion of data and volatile memory metadata stored by the controller, and a backup power source for powering the controller. The controller includes a pre-specified region of volatile memory for storing backup device metadata for managing a modified portion of data, the metadata comprising one or more intents corresponding to modified data written back to the data storage device. The controller is configured to invalidate the one or more intents. During a restore operation, the controller is configured to store the backup device metadata in the pre-specified region of volatile memory when a charge on the backup power source is at least a minimum threshold charge and to store the updated backup device metadata in the backup device during an interruption of power. | 01-20-2011 |
| 20110016152 | BLOCK-LEVEL DATA DE-DUPLICATION USING THINLY PROVISIONED DATA STORAGE VOLUMES - Data segments are logically organized in groups in a data repository. Each segment is stored at an index in the data repository. In association with a write request, a hash algorithm is applied to the data segment to generate a group identifier. Each group is identifiable by a corresponding group identifier. The group identifier is applied to a hash tree to determine whether a corresponding group in the data repository exists. Each existing group in the data repository corresponds to a leaf of the hash tree. If no corresponding group exists in the data repository, the data segment is stored in a new group in the data repository. However, if a corresponding group exists, the group is further searched to determine if a data segment matching the data segment to be stored is already stored. The data segment can be stored in accordance with the results of the search. | 01-20-2011 |
| 20110007618 | PREVENTING UNAUTHORIZED USE OF OPTICAL DISCS - An optical-disc writer writes extrinsic data to an optical disc. Extrinsic data can be written as (i) embedded marks (e.g., pits and lands) located outside the conventional readable area of a disc and/or (ii) alternative marks, such as surface marks located on a surface of the disc. In an optical-disc player having a disc-reading subsystem and a read controller, the disc-reading subsystem reads and relays the extrinsic data to the read controller, which controls the operations of the player based on the extrinsic data. For example, the writer prints extrinsic data, e.g., a barcode, on the surface of a software installation disc. The disc is inserted in the player and installation is commenced. The read controller instructs the disc-reading subsystem to read the extrinsic information. If the read controller determines that the extrinsic data was successfully read, then installation proceeds; otherwise, installation is halted. | 01-13-2011 |
| 20110006415 | SOLDER INTERCONNECT BY ADDITION OF COPPER - A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process. | 01-13-2011 |
| 20110006389 | SUPPRESSING FRACTURES IN DICED INTEGRATED CIRCUITS - A semiconductor device has a singulated die having a substrate and a die edge. An interconnect dielectric layer is located on the substrate, and integrated circuit has interconnections located within the interconnect dielectric layer. A trench is located in the interconnect dielectric layer and between a seal ring and a remnant of the interconnect dielectric layer. The seal ring is located within the interconnect dielectric layer and between the trench and the integrated circuit, with the remnant of the interconnect dielectric layer being located between the trench and the edge of the die. | 01-13-2011 |
| 20110004707 | LOAD BALANCING WITH SCSI I/O REFERRALS - A method and/or system may be configured to receive an input/output (I/O) request from an initiator system, add priority information to a multiple path referral for each port on which data can be accessed, selectively omit ports on which data may be accessed, transmit the multiple path referral from the target to the initiator, and/or choose a path on the initiator with the highest performance. | 01-06-2011 |
| 20110002186 | SECURE ELECTRICALLY PROGRAMMABLE FUSE AND METHOD OF OPERATING THE SAME - An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element. | 01-06-2011 |
| 20100325909 | AUTO-CALCULATED LENGTH DETERMINATION AND DISPLAY - In one embodiment, a tape measure having a tape, housing, and an input, has an OLED strip overlaid on top of the tape. The housing contains a programmable controller and a rolled-up portion of the tape. A specified fraction of the length of the linear target is provided to the controller using the input. The tape may be extracted from the housing to generate an exposed portion of the tape corresponding to the total length of a linear target. The controller receives information indicative of the total length of the linear target. The controller controls the OLED strip to show, i.e., light up along the tape, a fractional portion corresponding to the specified fraction of the linear target. | 12-30-2010 |
| 20100319987 | LEAD FRAME DESIGN TO IMPROVE RELIABILITY - An electronic device package | 12-23-2010 |
| 20100318340 | METHOD OF GENERATING A LEADFRAME IC PACKAGE MODEL, A LEADFRAME MODELER AND AN IC DESIGN SYSTEM - A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die. | 12-16-2010 |
| 20100316062 | SCALABLE PACKET-SWITCH - A scalable packet switch possessing a multiport memory, a multiport memory manager, two or more input/output (I/O) ports, and two or more switch engines. Each switch engine is associated with one or more I/O ports, and is adapted to receive inbound packets and transmit outbound packets via the associated I/O ports. Inbound packets are stored in a shared packet buffer. Each switch engine is further adapted to (i) determine (i.e., bridge) the outbound I/O port(s) for received inbound packets by consulting a shared bridging table and (ii) schedule outbound packets for transmission, independently and in parallel with other switch engines. The shared packet buffer and shared bridging table are stored in the multiport memory and shared by all switch engines. The multiport memory manager allocates/de-allocates memory blocks within the multiport memory. | 12-16-2010 |
| 20100314747 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE - A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers. | 12-16-2010 |
| 20100312960 | METHOD AND APPARATUS FOR PROTECTING THE INTEGRITY OF CACHED DATA IN A DIRECT-ATTACHED STORAGE (DAS) SYSTEM - A DAS system that implements RAID technology is provided in which an array of solid state disks (SSDs) that is external to the DAS controllers of the DAS system is used by the DAS controllers as WB cache memory for performing WB caching operations. Using the external SSD array as WB cache memory allows the DAS system to be fully cache coherent without significantly increasing the complexity of the DAS system and without increasing the amount of bandwidth that is utilized for performing caching operations. In addition, using the external SSD array as WB cache memory obviates the need to mirror DAS controllers. | 12-09-2010 |
| 20100306519 | SYSTEM AND METHOD FOR MAINTAINING THE SECURITY OF MEMORY CONTENTS AND COMPUTER ARCHITECTURE EMPLOYING THE SAME - A secure memory system and a method of maintaining the security of memory contents. One embodiment of the system includes: (1) a security control module configured to transmit a system memory secure mode signal and processor secure mode signal to place the system in a secure mode, (2) a secure memory bridge coupled to the security control and system memory and configured to encrypt and decrypt data associated with the system memory based on a state of the system memory secure mode signal and (3) a boot processor coupled to the security control module and the secure memory bridge and configured to transmit requests to the secure memory bridge in the secure mode and an unsecure mode. | 12-02-2010 |
| 20100306420 | FAST PATH SCSI IO - A hardware automated IO path, comprising a message transport unit for transporting an IO request to a local memory via a DMA operation and determining a LMID for associating with a request descriptor of the IO request; a fastpath engine for validating the request descriptor and creating a fastpath descriptor based on the request descriptor; a data access module for performing an IO operation based on the fastpath descriptor and posting a completion message into the fastpath completion queue upon a successful completion of the IO operation. The fastpath engine is further configured for: receiving the completion message, releasing the IO request stored in the local memory, and providing a reply message based on the completion message. The message transport unit is further configured for providing the reply message in response to the IO request. | 12-02-2010 |
| 20100304711 | TRANSMITTING DATA OVER A MOBILE TELECOMMUNICATION NETWORK - A network is configured to charge fees at a first rate for transmitting data of a first type and fees at a second, less expensive, rate for transmitting data of a second type. In a first embodiment, at least a portion of the original data transmitted is converted from the first type into the second type before sending the processed data to the network. A corresponding conversion from the second type into the first type is performed at the receiver's side to obtain re-created data from the received data. In a second embodiment, the original data is processed to obtain at least a first portion of data having the first type and a second portion of data having the second type. The at least two portions are sent to the network via different channels ensuring that at least the second portion will be billed at the second, lower rate. | 12-02-2010 |
| 20100303085 | BRIDGE APPARATUS AND METHODS FOR COUPLING MULTIPLE NON-FIBRE CHANNEL DEVICES TO A FIBRE CHANNEL ARBITRATED LOOP - Apparatus and methods for an enhanced bridge device for coupling multiple non-Fibre Channel storage devices to a Fibre Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device. | 12-02-2010 |
| 20100303084 | APPARATUS AND METHODS FOR ACCESS FAIRNESS FOR A MULTIPLE TARGET BRIDGE/ROUTER IN A FIBRE CHANNEL ARBITRATED LOOP SYSTEM - Apparatus and methods improved fair access to a Fibre Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window. | 12-02-2010 |
| 20100300741 | ALUMINUM BOND PADS WITH ENHANCED WIRE BOND STABILITY - An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein. | 12-02-2010 |
| 20100299549 | POWER MANAGMENT FOR STORAGE DEVICES - Methods and systems are provided for managing power allocation to a SAS target coupled with a SAS initiator through a SAS expander. The expander exchanges messages with the target to manage the power allocation to the target. The target transmits a power request message through the expander to the initiator. In some embodiments, the initiator transmits a power request received message to the expander. The expander may then transmit a power grant message to the target in response to receiving the power request received message. In other embodiments, the expander monitors the messages transmitted from the target to the initiator. The expander may then transmit a power grant message to the target in response to the expander monitoring the power request message. | 11-25-2010 |
| 20100296815 | METHODS AND APPARATUS FOR INTERCONNECTING SAS DEVICES USING EITHER ELECTRICAL OR OPTICAL TRANSCEIVERS - Methods and systems for encoding and/or decoding digital signals representing serial attached SCSI (SAS) out of band (OOB) signals exchanged over an optical communication between two SAS devices. A SAS OOB signal to be transmitted from a first SAS device to a second SAS device is first encoded as a digitally encoded signal representing the analog SAS OOB signal and then transmitted over an optical communication medium to another SAS device. A receiving SAS device coupled to an optical communication medium decodes a received digitally encoded signal to detect a received, encoded SAS OOB signal and processes the received SAS OOB signal when receipt is detected. The digitally encoded signal may comprise an idle word portion and a burst word portion to represent various SAS OOB signals. Further, the digitally encoded signal may be precomputed in a variety of disparity forms and stored in a memory for lookup and retrieval. | 11-25-2010 |
| 20100293326 | MEMORY DEVICE CONTROL FOR SELF-REFRESH MODE - To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE input and (2) a power island for driving a clock enable signal CKE_prime onto that same input. To power down the memory controller, the normal-mode output buffer drives signal CKE low, then the power island drives signal CKE_prime low, then the memory controller (except for the power island) is powered down. The power island continues to drive the memory device's CKE input low to ensure that the memory device stays in self-refresh mode while the memory controller is powered substantially off. To resume normal operations, the power module powers up the memory controller, then the normal-mode output buffer drives signal CKE low, then the power island is disabled, then the memory controller resumes normal operations of the memory device. | 11-18-2010 |
| 20100293304 | CONTROLLER AND METHOD FOR STATISTICAL ALLOCATION OF MULTICHANNEL DIRECT MEMORY ACCESS BANDWIDTH - A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: ( | 11-18-2010 |
| 20100289112 | METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER - A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic. | 11-18-2010 |
| 20100288048 | ELECTRONIC PRESSURE-SENSING DEVICE - An electronic pressure-sensing device | 11-18-2010 |
| 20100283711 | AN INTEGRATED COMPUTATION AND COMMUNICATION SYSTEM, A FRAMED INTERFACE THEREFOR AND A METHOD OF OPERATING THEREOF - An integrated computational and communication system having modular components, a framed user interface and a method of operation an integrated computational and communication system are provided. In one embodiment, the integrated computational and communication system includes: (1) an input component configured to receive input data from a user, (2) an output component configured to provide output data to the user, (3) a controller configured to provide computational functionality and telephone communication for the system and (4) a communication base station configured to provide bi-directional communication channels between the input and output components, the communication base station and the controller, wherein the communication base station and the controller are adapted to be worn by the user. | 11-11-2010 |
| 20100281101 | UNIFIED SUPPORT FOR WEB BASED ENTERPRISE MANAGEMENT ("WBEM") SOLUTIONS - Methods and systems for support a unified Web Based Enterprise Management (“WBEM”) solution is provided. A first processing element for generating first HTTP content data is provided such that a response to a non-Common Information Model (“CIM”) request is based on the first HTTP content data. A second processing element for generating second HTTP content data is also provided such that another response to a CIM request is based on the second HTTP content data. At least one of the first processing element and the second processing element is accessible directly only from within the system to unify access to the two elements. | 11-04-2010 |
| 20100278021 | CONTROLLING AN OPTICAL-DISC READER USING SURFACE MARKS - An optical-disc player having a reader and a controller. The reader derives out-of-band information from surface marks of an optical disc, where the controller controls operations of the reader based on the derived information. The controlled operations may involve the reading and rendering of embedded data of the optical disc. For example, a person writes the words “Spanish” and “widescreen” on the surface of a DVD with a marker and inserts the DVD in a DVD player. The DVD player scans the surface of the DVD and sends the resulting image data to an optical character recognition (OCR) module. The OCR module outputs a text file containing the words “Spanish” and “widescreen” to a controller (e.g., Microsoft HDi runtime). In response, the controller sets the playback language to Spanish and the screen format to widescreen. | 11-04-2010 |
| 20100278000 | MEMORY DEVICE CONTROL FOR SELF-REFRESH MODE - In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off. | 11-04-2010 |
| 20100274969 | ACTIVE-ACTIVE SUPPORT OF VIRTUAL STORAGE MANAGEMENT IN A STORAGE AREA NETWORK ("SAN") - Methods and apparatuses are provided for active-active support of virtual storage management in a storage area network (“SAN”). When a storage manager (that manages virtual storage volumes) of the SAN receives data to be written to a virtual storage volume from a computer server, the storage manager determines whether the writing request may result in updating a mapping of the virtual storage volume to a storage system. When the writing request does not involve updating the mapping, which happens most of the time, the storage manager simply writes the data to the storage system based on the existing mapping. Otherwise, the storage manager sends an updating request to another storage manager for updating a mapping of the virtual storage volume to a storage volume. Subsequently, the storage manager writes the data to the corresponding storage system based on the mapping that has been updated by the another storage manager. | 10-28-2010 |
| 20100274967 | MANAGING STORAGE ARRAY OPERATIONS THAT CAUSE LOSS OF ACCESS TO MIRRORED DATA - Storage array operations, such as code downloads and other operations of the type that cause loss of access to portions of the storage array, are managed in a manner that preserves access to other portions of the storage array so that other storage array operations, such as data synchronization, can continue. | 10-28-2010 |
| 20100270671 | MANIPULATING FILL PATTERNS DURING ROUTING - A CAD tool that supports an overlay-enabling operating mode. After the overlay-enabling operating mode is entered, the layout-editing facility permits modifications to the interconnect structure of an integrated circuit that is being designed regardless of whether a particular modification interferes with an existing pattern of metal fill. For example, a new signal wire can be added to electrically connect two specified points in the layout in a manner that causes the wire to cross over one or more metal-fill tiles. The CAD tool then modifies the fill pattern to get rid of any design-rule violations caused by the modifications to the interconnect structure by removing and/or modifying one or more fill tiles. | 10-28-2010 |
| 20100262941 | Automated Timing Optimization - A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path. | 10-14-2010 |
| 20100262939 | SYSTEM AND METHOD FOR CLOCK OPTIMIZATION TO ACHIEVE TIMING SIGNOFF IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME - A system and method for clock optimization to achieve timing signoff in an electronic circuit and an EDA tool that embodies the system or the method. In one embodiment, the system includes: (1) a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort the cells according to breadth, (2) a slack analyzer associated with the clock cell identifier/sorter and configured to identify flops that are downstream of the cells and determine a worst setup and hold timing slack thereof and (3) a clock cell delay adjuster associated with the slack analyzer and configured to adjust delays of the cells subject to the worst setup and hold timing slack. | 10-14-2010 |
| 20100262876 | TEST CIRCUIT AND METHOD FOR TESTING OF INFANT MORTALITY RELATED DEFECTS - The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node. | 10-14-2010 |
| 20100262394 | METHOD AND AN APPARATUS FOR EVALUATING SMALL DELAY DEFECT COVERAGE OF A TEST PATTERN SET ON AN IC - A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path. | 10-14-2010 |
| 20100251012 | Data Volume Rebuilder and Methods for Arranging Data Volumes for Improved RAID Reconstruction Performance - A data volume rebuilder reduces the time required to reconstruct lost data in a RAID protected data volume operating with a failed physical disk drive. A data volume rebuilder uses the remaining functioning physical disk drives in the RAID protected data volume operating with the failed disk to regenerate the lost data and populate a virtual hot spare store allocated in a separate RAID protected data volume. The recovered data is distributed across the physical disk drives supporting the virtual hot spare store. Once the virtual hot spare store is populated, the data volume can recover from a subsequent failure of a second physical disk drive in either RAID group. After replacement of the failed physical disk drive, the data volume rebuilder moves the recovered data from the virtual hot spare store to the new physical disk drive. | 09-30-2010 |
