LSI Corporation Patent applications |
Patent application number | Title | Published |
20160142233 | DATA RATE AND PVT ADAPTATION WITH PROGRAMMABLE BIAS CONTROL IN A SERDES RECEIVER - Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through programmable bias based on sensed PVT and data rate changes. The low frequency attenuation/gain range is extended, and can be programmed to a desirable targeted range by a SerDes device RX adaptive process for a given VGA and linear equalizer (LEQ) setting at any given PVT and data rate condition. | 05-19-2016 |
20160034393 | Slice-Based Random Access Buffer for Data Interleaving - The disclosure is directed to a system and method for interleaving data utilizing a random access buffer that includes a plurality of independently accessible memory slots. The random access buffer is configured to store slices of incoming data sectors in free memory slots, where a free memory slot is identified by a status flag associated with a logical address of the free memory slot. Meanwhile, a label buffer is configured to store labels associated with the slices of the incoming data sectors in a sequence based upon an interleaving scheme. Media sectors including the interleaved data slices are read out from the memory slots of the random access buffer in order of the sequence of labels stored by the label buffer. As the media sectors are read out of the random access buffer, the corresponding memory slots are freed up for incoming slices of the next super-sector. | 02-04-2016 |
20160034186 | HOST-BASED DEVICE DRIVERS FOR ENHANCING OPERATIONS IN REDUNDANT ARRAY OF INDEPENDENT DISKS SYSTEMS - Methods and structure for host-side device drivers for Redundant Array of Independent Disks (RAID) systems. One system includes a processor and memory of a host, which implement a device driver. The device driver receives an Input/Output (I/O) request from an Operating System (OS) of the host, translates Logical Block Addresses (LBAs) from the received request into physical addresses at multiple storage devices, generates child I/O requests directed to the physical addresses based on the received request, and accesses an address lock system at a RAID controller to determine whether the physical addresses are accessible. If the physical addresses are accessible, the device driver reserves the physical addresses by updating the address lock system, and directs the child I/O requests to a hardware path at the RAID controller for handling single-strip I/O requests. If the physical addresses are not accessible, the device driver delays processing of the child I/O requests. | 02-04-2016 |
20160028419 | Systems and Methods for Rank Independent Cyclic Data Encoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding. | 01-28-2016 |
20160020158 | Systems and Methods for Self Test Circuit Security - The present inventions are related to systems and methods for circuit implementation, and more particularly to systems and methods for securing data in a circuit. | 01-21-2016 |
20150350721 | PLL Scan Method for HDTV Products - A system and method for improved channel scanning in an HDTV device queries a database with location data input by the user, receiving an ordered list of potential channels associated with the selected location. The system may scan only those potential channels on the ordered list, storing successfully decoded channels in memory. The system may further divide the ordered list into groups based on the relative signal strength of potential channels. If a potential channel of the lowest relative signal strength group cannot be successfully decoded, the system may indicate that scanning is complete. | 12-03-2015 |
20150349988 | SELECTING FLOATING TAP POSITIONS IN A FLOATING TAP EQUALIZER - In one embodiment, an apparatus has an equalizer, a tap position locator, and a tap weight updater. The equalizer has a plurality of floating taps. The tap position locator generates metrics for a set of possible tap positions of the equalizer. Each possible tap position corresponds to a different tap weight, and the metrics are generated without updating the tap weights for all of the possible tap positions in the set. Further, the tap position locator selects a subset of possible tap positions from the set based on the metrics. The tap weight updater updates a subset of the tap weights corresponding to the selected subset of possible tap positions, and applies the updated subset of tap weights to the plurality of floating taps. | 12-03-2015 |
20150349811 | SCALABLE MAPPING WITH INTEGRATED SUMMING OF SAMPLES FOR MULTIPLE STREAMS IN A RADIO INTERFACE FRAME - An apparatus includes a first circuit, a second circuit, and a third circuit. The first circuit may be configured to buffer a plurality of antenna carrier sample streams. The second circuit is coupled to the first circuit and may be configured to generate message data through pipelined processing and mapping of the antenna carrier samples. The third circuit is coupled to the second circuit and may be configured to generate a master frame in response to the processed and mapped message data. | 12-03-2015 |
20150348594 | MEMORY BANKS WITH SHARED INPUT/OUTPUT CIRCUITRY - A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks. | 12-03-2015 |
20150347310 | Storage Controller and Method for Managing Metadata in a Cache Store - A cache controller coupled to a cache store supported by a solid-state memory element uses a metadata update process that reduces write amplification caused by writing both cache data and metadata to the solid-state memory element. The cache controller partitions the solid-state memory element to include a metadata portion, a host data or cache portion and a log portion. Host write requests that include “hot” data are processed and recorded by the cache controller. The cache controller maintains first and second maps. A log thread combines multiple metadata updates in a single log entry block. Pending metadata updates are checked to determine when a commit threshold is reached. Thereafter, the pending metadata updates are written to the solid-state memory element and the maps are updated. | 12-03-2015 |
20150347289 | Forced Map Entry Flush to Prevent Return of Old Data - A data storage device flushes newly written data in response to certain events such that, when the device has acknowledged newly written data, the device cannot return old data of the referenced logical block address to the host in any case. If the data of the logical block address has been corrupted, the device returns an uncorrectable error, not old data. A “force map entry flush” flushes modified map entries to NAND when an upper page is programmed. After a power failure and restoration, a storage device is able to analysis map entries to determine whether there is some host data in the uncorrectable die, then prevent return of old data to a host. | 12-03-2015 |
20150346762 | DWELL TIMERS FOR SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE DEVICES - Methods and structure for dwell timers in Serial Attached Small Computer System Interface (SAS) devices. An exemplary system includes a SAS end device. The SAS end device includes a physical link (PHY) operable to receive an OPEN Address Frame (OAF) from a coupled SAS device. The SAS end device also includes a controller. The controller is able to determine that the end device is presently unable to service a connection, and to wait a period of time for a dwell timer to expire. The controller is also able to service the connection by sending an OPEN_ACCEPT response if the end device becomes able to service the connection before the dwell timer expires, and to send an OPEN_REJECT (RETRY) response if the end device does not become able to service the connection before the dwell timer expires. | 12-03-2015 |
20150339189 | FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value. | 11-26-2015 |
20150333745 | VOLTAGE COMPARATOR - A voltage comparator for comparing reference voltage applied to a first input node to an input voltage applied to a second input node. A first pair of transistors have output terminals coupled in series between the first input node and common node, and gate terminals connected together. A second pair of transistors, having both gate terminals of the pair connected to the gate terminals of the first pair of transistors, have output terminals coupled in series between a second input terminal, an intermediate node, and the common node. An inverter has an input coupled to the intermediate node and an output coupled to an output of the comparator. An optional feedback transistor might be used to latch the output of the comparator. Optional transistors might also be added to the first and second transistor pairs to selectively enable as the comparator and reset the latched output of the comparator. | 11-19-2015 |
20150332755 | MEMORY CELL HAVING BUILT-IN READ AND WRITE ASSIST - A memory cell having integrated read and write assist functionality includes a storage element and first and second switching circuits. The first switching circuit is configured to selectively couple a first internal storage node of the storage element with a first bit line. The second switching circuit is configured to selectively couple a second internal storage node of the storage element with a second bit line. During a read operation, at least one of the first and second switching circuits is configured to increase a switching threshold of at least one inverter in the storage element. During a write operation, at least one of the first and second switching circuits is configured such that ground bounce associated with at least one of the first and second switching circuits assists in writing a logical state of the memory cell. | 11-19-2015 |
20150331773 | SIDEBAND LOGIC FOR MONITORING PCIe HEADERS - Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal, packets. | 11-19-2015 |
20150331765 | COORDINATION TECHNIQUES FOR REDUNDANT ARRAY OF INDEPENDENT DISKS STORAGE CONTROLLERS - Methods and structure for coordinating between Redundant Array of Independent Disks (RAID) storage controllers are provided. An exemplary system includes a RAID controller. The RAID controller includes a Peripheral Component Interconnect Express (PCIe) interface, a Serial Attached Small Computer System Interface (SAS) port operable to communicate with another RAID controller, and a command unit. The command unit is able to direct the interface to contact another PCIe interface at the other controller, to acquire an identifier of the other controller stored in a PCIe Inbound Map (PIM) for the other interface, and to activate a feature for the controller that enables cooperative management of storage devices between the controller and the other controller, if the identifier of the other controller matches discovery information maintained at the controller. | 11-19-2015 |
20150331748 | METHOD TO DYNAMICALLY UPDATE LLRs IN AN SSD DRIVE AND/OR CONTROLLER - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error correction code decoding fails. The controller may be configured to generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold. The plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units. | 11-19-2015 |
20150325266 | Multi-Dimensional Optimization of Read Channel - Variations of the Nelder-Mead direct search method are employed to find read channel parameter settings in a discrete field having three or more dimensions. The three or more dimensions correspond to read channel parameters, at least some of which are highly correlated. The steps of the Nelder-Mead method are executed according to a methodology to arrive at substantially optimal parameter settings for a read channel, even where a discrete function defining parameter outcomes is noisy. In some embodiments, dimensional collapse, considered inefficient in a two-dimensional field, is allowed in order to reach an optimal solution in a greater-than-two-dimensional field. | 11-12-2015 |
20150324300 | System and Methods for Efficient I/O Processing Using Multi-Level Out-Of-Band Hinting - A storage subsystem can achieve more efficient I/O processing by enabling users to specify and pass out of band I/O hints comprising an object to be hinted, a hint type, and caching strategies associated with a hint type. A hinted object may be either a virtual device or a file. In addition to priority cache, hint types may include never-cache, sticky-cache, and volatile-cache. Hints may be passed via command-line or graphical-user interfaces. | 11-12-2015 |
20150324295 | Temporal Tracking of Cache Data - A data storage system with a cache organizes cache windows into lists based on the number of cache lines accessed during input/output operations. The lists are maintained in temporal queues with cache windows transferred from prior temporal queues to a current temporal queue. Cache windows are removed from the oldest temporal queue and least accessed cache window list whenever cached data needs to be removed for new hot data. | 11-12-2015 |
20150324136 | STORAGE SYSTEM HAVING FIFO STORAGE AND RESERVED STORAGE - An apparatus having first-in-first-out storage and reserved storage is disclosed. In one or more embodiments, the apparatus includes memory circuitry having first-in-first-out storage and reserved storage. The first-in-first-out storage and the reserved storage include an array of data elements having contiguous addresses across the first-in-first-out storage and the reserved storage. The memory circuitry includes a first-in-first-out pointer for referencing an index corresponding to a data element of the array of data elements of the first-in-first-out storage to be read and a read pointer mapped to the first-in-first-out pointer and for referencing a memory location of the data element to be read. The read pointer is mapped such that the read pointer does not reference a plurality of data elements stored in the reserved storage. | 11-12-2015 |
20150323595 | SYSTEM FOR REDUCING TEST TIME USING EMBEDDED TEST COMPRESSION CYCLE BALANCING - An apparatus for reducing test time is disclosed. The apparatus includes a processor operable to execute one or more modules to cause the processor to receive operational parameters associated with a first scan chain grouping circuitry and a second scan chain grouping circuitry of an integrated circuit design. The operational parameters include a number of initialization cycles of a first test signal selected for the first scan chain grouping circuitry, a number of initialization cycles of a second test signal selected for the second scan chain grouping circuitry, and a sum for a total number of cycles for the first test signal. The processor also determines a scan chain length for one of the first scan chain grouping circuitry or the second scan chain grouping circuitry based upon the operation parameters such that the total number of cycles of the first signal and the second signal are the same. | 11-12-2015 |
20150319018 | SLICER TRIM METHODOLOGY AND DEVICE - Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle. | 11-05-2015 |
20150318740 | ELECTROMAGNETIC ENERGY TRANSFER USING TUNABLE INDUCTORS - A receiving coil apparatus for use in an electromagnetic energy transfer system includes multiple conductive loops and a switching circuit connected with the conductive loops. The switching circuit is configured to control an electrical center of the receiving coil apparatus as a function of at least one control signal. A controller connected with the switching circuit is configured to generate the control signal for controlling an alignment of the electrical center of the receiving coil apparatus with an electromagnetic field so as to enhance an amount of energy transferred to the receiving coil apparatus from the electromagnetic field. | 11-05-2015 |
20150318030 | MULTIPLEXED SYNCHRONOUS SERIAL PORT COMMUNICATION WITH SKEW CONTROL FOR STORAGE DEVICE - A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus. | 11-05-2015 |
20150318014 | MULTIPLEXED COMMUNICATION IN A STORAGE DEVICE - A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation. | 11-05-2015 |
20150317219 | LOGICAL VOLUME MIGRATION IN SINGLE SERVER HIGH AVAILABILITY ENVIRONMENTS - Methods and structure for migrating logical volumes are provided. The system includes a Redundant Array of Independent Disks controller, which includes a Peripheral Component Interconnect Express interface, a Serial Attached Small Computer System Interface port operable to communicate with another Redundant Array of Independent Disks controller, and a command unit. The command unit is able to direct the interface to access another Peripheral Component Interconnect Express interface at the other controller, to synchronize with Disk Data Format information from a Peripheral Component Interconnect Express Inbound Map of the other interface, to detect that the other controller has failed, and to utilize the Disk Data Format information to migrate a logical volume from the other controller to the controller. | 11-05-2015 |
20150317204 | Systems and Methods for Efficient Data Refresh in a Storage Device - Systems and method relating generally to data storage processing, and more particularly to systems and methods for refreshing data in a data storage device. | 11-05-2015 |
20150317090 | System and Method of Life Management for Low Endurance SSD NAND Devices Used as Secondary Cache - A system and method for managing the life expectancy of at least one solid state drive (SSD) within a cache device of a storage subsystem includes determining a baseline rate of decline for each SSD based on its guaranteed life expectancy. At intervals, each SSD of the cache device is polled for remaining life and power-on time, and a current rate of decline (based on time since initialization) and a cumulative rate of decline (based on total lifespan of the SSD) is determined. When both the current rate of decline and the cumulative rate of decline exceed the baseline rate of decline for any SSD of the cache device, write requests to that SSD are blocked and redirected to the virtual device until either the current rate of decline or cumulative rate of decline drop below the baseline rate. | 11-05-2015 |
20150312060 | DECISION FEEDBACK EQUALIZATION SLICER WITH ENHANCED LATCH SENSITIVITY - A decision feedback equalization slicer for ultra-high-speed backplane Serializer/Deserializer (SerDes) with improved latch sensitivity. A first regeneration stage can be configured in association with a second regeneration stage to compensate for channel impairment such as inter-symbol interference due to channel loss, reflections due to impedance mismatch, and cross-talk interference from neighboring electrical channels. The first regeneration stage includes two first stage slicers corresponding to a set of speculative decision (+h | 10-29-2015 |
20150312037 | DATA SCRAMBLING INITIALIZATION - Systems and methods for improved synchronization between a transmit device and a receive device in a communication system. In one embodiment, an apparatus for transmitting bits of data over a link includes a scrambler to scramble data and circuitry configured to insert the scrambled data into frames and to transmit the frames in data blocks over the link. The apparatus also includes an initialization module configured to generate an unscrambled pseudo-random sequence. The circuitry is further configured to periodically insert the unscrambled pseudo-random sequence into a frame, to initialize the scrambler to a starting point based on the insertion of the unscrambled pseudo-random sequence into the frame, and to transmit the frame in a data block over the link. | 10-29-2015 |
20150309872 | DATA RECOVERY ONCE ECC FAILS TO CORRECT THE DATA - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page. | 10-29-2015 |
20150303943 | Systems and Methods for Puncture Based Data Protection - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for protecting portions of data sets during data processing. | 10-22-2015 |
20150303396 | METHOD AND SYSTEM FOR AN ORGANIC LIGHT EMITTING DIODE STRUCTURE - Disclosed is a system and method for a nano-pillar geometry for increased light extraction properties of an Organic Light Emitting Diode. | 10-22-2015 |
20150302918 | WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES - Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path. | 10-22-2015 |
20150302887 | Cross-Talk Measurement In Array Reader Magnetic Recording System - An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head. | 10-22-2015 |
20150302593 | Front-End Architecture for Image Processing - Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask. | 10-22-2015 |
20150301956 | DATA STORAGE SYSTEM WITH CACHING USING APPLICATION FIELD TO CARRY DATA BLOCK PROTECTION INFORMATION - In a data storage system in which a host system transfers data to a data storage controller having cache memory, the data storage controller can use a designated field of each of several cache data blocks, such as an application (APP) field, to contain protection information from fields of a host data block, such as the guard (GRD) and reference (REF) fields as well as the APP field. | 10-22-2015 |
20150301934 | FLASH-BASED DATA STORAGE WITH DUAL MAP-BASED SERIALIZATION - A RAID storage system serializes data blocks to be stored in a RAID storage array and uses a primary map table and a number of secondary map tables to relate host addresses to logical block addresses in the storage array. Secondary map tables and other metadata can be cached from the storage array. The dual or two-tier map scheme and metadata caching promote scalability. | 10-22-2015 |
20150294739 | ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING - A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells. | 10-15-2015 |
20150293808 | SOFT READ HANDLING OF READ NOISE - Aspects of the disclosure pertain to methods and systems that are configured to handle excessive read noise in soft read systems. In an implementation, a method includes determining a number of unexpected patterns of a soft read of a memory cell after a soft decoding failure. The method also includes determining whether the number of unexpected patterns is greater than a threshold number of unexpected patterns. When it is determined that the number of unexpected patterns is greater than the threshold number of unexpected patterns, the method at least one of: performing at least one more soft read of the memory cell with a larger read voltage spacing than an initial read that produced the soft decoding failure; and discarding a result of one or more soft reads of the memory cell and utilizing a remainder of results of respective other soft reads of the memory. | 10-15-2015 |
20150287478 | BAD MEMORY UNIT DETECTION IN A SOLID STATE DRIVE - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to determine which of the memory units to mark as bad based on a test of whether a unit of memory larger than a block of the memory has failed. The test is based on a threshold of the bad blocks in the unit of memory. | 10-08-2015 |
20150286604 | DEVICE ABSTRACTED ZONE MANAGEMENT OF SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE TOPOLOGIES - Systems and methods provide zone management for devices in a Serial Attached Small Computer System Interface (SAS) topology. In one embodiment, a zone management device stores a zone map that identifies an initial zone of a device in the topology. The management device detects changes in the topology, and identifies a current zone of the device subsequent to the change in the topology. The management device compares the zone map for the device to the current zone to identify a change in the zone of the device, and generates a message for an expander in the topology based on the change in the zone. The management device then transmits the message to the expander to restore the zone of the device to the initial zone. | 10-08-2015 |
20150286600 | ARBITRATION MONITORING FOR SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE SYSTEMS DURING DISCOVERY - Methods and structure for detecting that arbitration is delaying discovery. One embodiment is a Serial Attached Small Computer System Interface (SAS) expander. The SAS expander includes multiple SAS ports, a port monitor, and a controller. The port monitor is able to track physical link events during arbitration for at least one of the ports while discovery is in progress at the expander, and to detect based on the physical link events that arbitration is delaying discovery. The controller is able to prioritize discovery requests at the expander responsive to detecting that arbitration is delaying discovery. | 10-08-2015 |
20150286528 | ERROR CORRECTION CODE (ECC) SELECTION IN NAND FLASH CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES - An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined data characterizing distribution properties of each of the plurality of error correction codes. | 10-08-2015 |
20150286523 | Systems and Methods for Differential Message Scaling in a Decoding Process - Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. | 10-08-2015 |
20150286438 | System, Method and Computer-Readable Medium for Dynamically Configuring an Operational Mode in a Storage Controller - A storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. For a logical volume in RAID 0, the device driver compares the queue depth to a threshold value and configures the storage controller to process the stream of I/O commands with a first path or an alternative path based on a result of the comparison. For a logical volume in RAID 5, the device driver performs a similar comparison and uses the result to direct the storage controller to use a write back or a write through mode of operation. | 10-08-2015 |
20150286421 | READ POLICY FOR SYSTEM DATA OF SOLID STATE DRIVES - An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies. | 10-08-2015 |
20150279415 | Systems and Methods for Skew Tolerant Multi-Head Data Processing - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing skew tolerant processing of data derived from multiple read heads. | 10-01-2015 |
20150279398 | Locking a Disk-Locked Clock Using Timestamps of Successive Servo Address Marks in a Spiral Servo Track - Described embodiments provide a magnetic mass storage device with a system clock phase-locked to servo address marks on the magnetic disk. A head sequentially reads multiple adjacent servo address marks in a spiral track of servo address marks. When a servo address mark detector detects a mark, the count value of a counter driven by the system clock is sampled and held by a latch. A system clock synthesizer calculates differences in value between successively sampled count values from the latch, averages the differences in value to create an average difference value, and normalizes a difference between the average difference value and a target value to create a phase error value. The phase of the system clock is updated using the phase error value. | 10-01-2015 |
20150269990 | Memory Sense Amplifier And Column Pre-Charger - A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit. | 09-24-2015 |
20150269304 | SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE TOTAL POWER WITHIN A CIRCUIT DESIGN - A system is described that analyzes timing of a design and conditionally replaces values of a cell to lower total power within circuit paths having a positive timing margin. The system includes a computing device that includes a memory for storing modules and a processor that is operable to execute the modules. The modules cause the processor to conditionally replace a first semiconductor characteristic with a second semiconductor characteristic associated with a cell in a path of a circuit design and estimating a delay and a slack of the path based upon the first semiconductor characteristic. The modules also cause the processor to determine whether the second semiconductor characteristic causes a timing violation with respect to the path and causes conditional replacement of the second semiconductor characteristic with a third semiconductor characteristic until the timing violation is removed. | 09-24-2015 |
20150269097 | System and Method for Elastic Despreader Memory Management - The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability. | 09-24-2015 |
20150269054 | Multiple Core Execution Trace Buffer - A data processing system includes a number of processor cores each having a trace interface with an address signal carrying program addresses being executed, a processor core identification circuit connected to the trace interfaces and operable to replace a portion of some of the program addresses with a processor core identification that identifies which of the processor cores provided the program addresses, and an execution trace buffer operable to store the program addresses associated with non-sequential execution in the processor cores. At least some of the program addresses include the processor core identification along with address bits. | 09-24-2015 |
20150269025 | WRITE REDIRECTION IN REDUNDANT ARRAY OF INDEPENDENT DISKS SYSTEMS - Methods and structure for redirecting writes in Redundant Array of Independent Disks (RAID) systems are provided. One exemplary embodiment is a RAID controller that includes a memory and a control unit. The memory is able to store mapping information that correlates Logical Block Addresses of a RAID volume with physical addresses of storage devices. The control unit is able to generate a request to write volume data to at least one of the physical addresses, to determine that a storage device has failed to complete the request, to alter the mapping information by correlating Logical Block Addresses for the request with physical addresses of a spare storage device, to redirect the request to the spare storage device, and to rebuild remaining Logical Block Addresses that are correlated with the storage device that failed. | 09-24-2015 |
20150268871 | READ DISTURB HANDLING IN NAND FLASH - An apparatus having a processor and an interface to a nonvolatile memory having a plurality of blocks is disclosed. The processor is configured to (i) monitor a number of reads since a respective erase in at least one of the blocks in the nonvolatile memory, (ii) move a page from a first block to a second block in response to the number of reads exceeding a first threshold where the first block is partially programmed and (iii) move the page from the first block to the second block in response to the number of reads exceeding a second threshold where the first block is fully programmed. The first threshold is less than the second threshold. | 09-24-2015 |
20150263848 | CDR RELOCK WITH CORRECTIVE INTEGRAL REGISTER SEEDING - Described embodiments provide for, in a clock and data recovery (CDR) circuit, detection of loss of acquisition and CDR restarting with corrective integral accumulator register seeding and gearshift restarting. In described embodiments, a mechanism is employed to cause faster loss of lock condition if the CDR circuit directed on an incorrect acquisition trajectory, actual loss of CDR lock is then detected, and CDR acquisition is recovered with corrective integral accumulator seeding. | 09-17-2015 |
20150263732 | SYSTEMS AND METHODS FOR VOLTAGE LEVEL SHIFTING IN A DEVICE - Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal. | 09-17-2015 |
20150262950 | Method for Fabricating Equal Height Metal Pillars of Different Diameters - A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process. | 09-17-2015 |
20150262949 | Method for Fabricating Equal Height Metal Pillars of Different Diameters - A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow pillars are formed by electroplating metal into the second openings for a second time period during which the metal is also added to the metal layers in the first openings to form wide pillars having substantially the same height as the narrow pillars. The photoresist is then removed along with conductive layers on the device used as part of the plating process. | 09-17-2015 |
20150262710 | METHOD AND SYSTEM FOR REDUCING MEMORY TEST TIME UTILIZING A BUILT-IN SELF-TEST ARCHITECTURE - Methods and systems for reducing memory test time utilizing a serial per march element communicating architecture. A small number of slow speed signals can be configured between a BIST wrapper and a BIST controller to transfer information in accordance with a BIST sequence that includes a number of march elements. An information transfer protocol can be implemented between the BIST wrapper and the BIST controller to transfer Information with respect to each march element that includes a number of BIST operations, address sequencing information, and data pattern. A command register can be loaded utilizing the slow speed signals and slow speed clock and content of the command register can be decoded. An encoded BIST operation can then be executed once for each BIST operation per march element. The serial per march element communicating architecture reduces test time as a communication overhead and a requirement for high speed wires are eliminated. | 09-17-2015 |
20150262667 | LOW POWER HIT BITLINE DRIVER FOR CONTENT-ADDRESSABLE MEMORY - An apparatus includes a hit bitline driver circuit and an equalization control circuit. The hit bitline driver circuit may be configured to drive a pair of hit bitlines responsive to a search bit. The equalization control circuit may be configured to transfer charge from one hit bitline of the pair to the other hit bitline of the pair in response to the search bit changing state. | 09-17-2015 |
20150262598 | Systems and Methods for Head Position Estimation - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly. | 09-17-2015 |
20150262592 | Systems and Methods for Distortion Characterization - Systems, methods, devices and circuits for data amplification, and more particularly systems and methods for characterizing distortion introduced during data amplification. In some cases, an amplifier modeling circuit is discussed that receives a preamplifier status input from a preamplifier circuit; applies a vector fitting algorithm to the preamplifier status to yield a pole value; determines that the pole value is greater than unity; and replaces the pole value with an inverse of the pole value when the pole value is greater than unity. | 09-17-2015 |
20150261636 | DATA TRANSFORMATIONS TO IMPROVE ROM YIELD AND PROGRAMMING TIME - Methods and systems for generating data transformations to improve ROM yield and programming time. A bit flip register can be configured in association with the ROM and a binary string can be read into the bit flip register on reset. Subsequently, data output from the ROM can be selectively complemented utilizing a content of the bit flip register and the content of the bit flip register can be programmed into the ROM in order to reduce programming time for each ROM. A defective cell can be tolerated by selectively flipping a column with respect to the defective cell to improve yield. A built-in self-test (BIST) engine that generates addresses up to and including content of an address limiting register can be employed to limit the ROM access to a programmed part during testing in order to tolerate defects in any unused location. | 09-17-2015 |
20150256364 | GROUP DELAY BASED BACK CHANNEL POST CURSOR ADAPTATION - Described embodiments provide for de-coupling between adaptation of decision feedback equalizer (DFE) filter taps and transmitter (TX) post cursor filtering in group delay (GD)-based adaptation. Consequently, an excessive build-up of transmitter post cursor effects and its excessive equalization cancellation by the DFE may be substantially reduced or eliminated. By breaking this coupling, a transmitter does not over equalize a signal, the DFE does not attempt to “undo” the over equalization, and a variable gain amplifier (VGA) in the receiver front end data path generally does not apply gain to amplify the signal back again due to the reduced DC level. GD-based TX post cursor adaptation may reduce over equalization effect and hence save power and increase performance by not over equalizing the signal. | 09-10-2015 |
20150256363 | Integrated PAM4/NRZ N-Way Parallel Digital Unrolled Decision Feedback Equalizer (DFE) - An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold. | 09-10-2015 |
20150256196 | SOFT DECODING OF POLAR CODES - An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities. | 09-10-2015 |
20150255148 | BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES - SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state. | 09-10-2015 |
20150255113 | Online Iteration Resource Allocation for Large Sector Format Drive - Systems and methods for resource allocation for a large sector format processing may include, but are not limited to, operations for: determining non-convergence of a magnetic disc sub-sector of a first magnetic disc sector within a processing time frame allocated to the magnetic disc sub-sector; determining a convergence of a second magnetic disc sector occurring in less time than a processing time frame allocated to the second magnetic disc sector; and processing the magnetic disc sub-sector during a portion of the processing time frame allocated to the second magnetic disc sector remaining after processing of the second magnetic disc sector. | 09-10-2015 |
20150255109 | Non-Decision Directed Magnetoresistive Asymetry Estimation - Systems and methods for magnetoresistive asymmetry estimation may include, but are not limited to, operations for: receiving a magnetic read head transducer output; computing a mean value of the magnetic read head transducer output; computing a median value of the magnetic read head transducer output; and applying a correction coefficient to a magnetic read head detector input according to at least the mean value of the magnetic read head transducer output and the median value of the magnetic read head transducer output. | 09-10-2015 |
20150255101 | TRACK MISREGISTRATION SENSITIVE INITIALIZATION OF JOINT EQUALIZER - A method of mitigating an effect of track misregistration on read performance in a system comprising an array-reader includes determining an estimated off-track condition, selecting translation coefficients based on the estimated off-track condition, determining updated equalizer coefficients by applying the translation coefficients to native equalizer coefficients, and applying the updated equalizer coefficients to signals received from the array-reader to output a read signal. | 09-10-2015 |
20150249555 | SERDES PVT DETECTION AND CLOSED LOOP ADAPTATION - In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition. | 09-03-2015 |
20150243617 | Method for Flip-Chip Bonding Using Copper Pillars - A bonding pad arrangement and method of bonding a flip-chip semiconductor device to a substrate using copper pillars and solder to join die pads on the flip-chip to substrate pads on the substrate. Each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. Alternatively, the offset for each of the substrate pads is the above-determined offset scaled as a function of a distance the respective die pad is from the centroid of the device. | 08-27-2015 |
20150243534 | Copper Wire Bonding Apparatus Using A Purge Gas to Enhance Ball Bond Reliability - A bonding apparatus and method of bonding copper bond wires to bond pads on an integrated circuit devices attached to a substrate. A heater block heats the devices and substrate prior to and during wire bonding. A clamp presses the substrate down onto the heater block during wire bonding and thereby forms a region of the substrate isolated from the remainder of the substrate. A bonder head creates ball bonds as it attaches one end of the bond wires to the bond pads on the devices within the isolated region. The bonder head also attaches the other end of the bond wires to substrate pads adjacent the devices being wire bonded. To prevent corrosion of the ball bonds, a gas source floods the substrate and the attached devices that have not yet wire bonded with a purge gas while the heater block heats the substrate and the attached devices. | 08-27-2015 |
20150243363 | ADJUSTING LOG LIKELIHOOD RATIO VALUES TO COMPENSATE MISPLACEMENT OF READ VOLTAGES - An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values. | 08-27-2015 |
20150243322 | Systems and Methods for Multi-Head Servo Data Processing - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads. | 08-27-2015 |
20150243321 | Reading Data from Hard Disks Having Reduced Preambles - An exemplary hard disk (HD) track has a full overhead section followed by user sections interleaved with intervening partial overhead sections that are too short for an HD drive (HDD) to attain sufficient timing lock using only one partial overhead section, but long enough for the drive to attain sufficient timing lock using multiple partial overhead sections to read user data from the user section immediately following the partial overhead section where sufficient timing lock is attained. The drive begins, but does not finish, attaining timing lock based on the first partial overhead section, but the drive does finish attaining timing lock based on the last partial overhead section. The drive can also read user data in subsequent user sections by maintaining or re-attaining sufficient timing lock using each successive partial overhead section. Increased user data storage is achieved without significantly impacting average latency of HDD read sessions compared to conventional HD drives. | 08-27-2015 |
20150243311 | Systems and Methods for Synchronization Hand Shaking in a Storage Device - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window. | 08-27-2015 |
20150243310 | Systems and Methods for Multi-Head Separation Determination - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly. | 08-27-2015 |
20150242133 | STORAGE WORKLOAD HINTING - Methods and structure for reconfiguring storage systems are provided. One exemplary embodiment is a storage controller. The storage controller includes a memory that stores multiple profiles that are each designated for a different type of Input/Output processing workload from a host, and each include settings for managing communications with coupled storage devices. Each type of workload is characterized by a pattern of Input/Output requests from the host. The storage controller also includes a control unit able to process host Input/Output requests at the storage controller in accordance with a first profile, identify a change in type of workload from the host, and load a second profile designated for the changed type of workload in place of the first profile. The control unit is also able to process host Input/Output requests at the storage controller in accordance with the second profile. | 08-27-2015 |
20150236875 | Method and Apparatus for Pre-Cursor Intersymbol Interference Correction - A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient. | 08-20-2015 |
20150236726 | Refresh, Run, Aggregate Decoder Recovery - A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder. | 08-20-2015 |
20150235705 | SYSTEM TO CONTROL A WIDTH OF A PROGRAMMING THRESHOLD VOLTAGE DISTRIBUTION WIDTH WHEN WRITING HOT-READ DATA - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to write user data using a plurality of threshold voltages. The data considered hot-read data is written using a first voltage threshold. The data not considered hot-read data is written using a second voltage threshold. The first voltage threshold reduces an impact on endurance of the memory. | 08-20-2015 |
20150234423 | Baud Rate Phase Detector with No Error Latches - Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits. | 08-20-2015 |
20150229337 | MITIGATION OF WRITE ERRORS IN MULTI-LEVEL CELL FLASH MEMORY THROUGH ADAPTIVE ERROR CORRECTION CODE DECODING - An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process. | 08-13-2015 |
20150228304 | Systems and Methods for End of Fragment Marker Based Data Alignment - Systems and method relating generally to data processing, and more particularly to systems and methods for data synchronization and detection. | 08-13-2015 |
20150228303 | Read Channel Sampling Utilizing Two Quantization Modules for Increased Sample Bit Width - A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process. | 08-13-2015 |
20150228302 | Zero Phase Start Estimation in Readback Signals - A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation. | 08-13-2015 |
20150227418 | HOT-READ DATA AGGREGATION AND CODE SELECTION - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory. | 08-13-2015 |
20150227403 | Decoding System and Method for Electronic Non-Volatile Computer Storage Apparatus - Methods are systems for calculating log-likelihood ratios for a decoder utilized in an electronic non-volatile computer storage apparatus are disclosed. A log-likelihood ratio handler is configured to provide an input log-likelihood ratio to the decoder, wherein the input log-likelihood ratio is one of: a uniform input log-likelihood ratio for all bits calculated based on an estimated raw bit error rate for a particular data unit, or a bit-based input log-likelihood ratio for each bit calculated based on a confidence value for a cell containing said each bit. The decoder of the electronic non-volatile computer storage apparatus is configured to decode encoded data at least partially based on the input log-likelihood ratio from the log-likelihood ratio handler. | 08-13-2015 |
20150227314 | Systems and Methods for Last Written Page Handling in a Memory Device - Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. | 08-13-2015 |
20150221333 | READER SEPARATION DEPENDENT LINEAR AND TRACK DENSITY PUSH FOR ARRAY READER BASED MAGNETIC RECORDING - A method of operating a multi-reader two-dimensional magnetic recording system includes determining a position of a multi-reader head of the multi-reader two-dimensional magnetic recording system, determining an areal density push according to the position of the multi-reader head, and performing an operation to read data from or write data to a magnetic recording medium according to the areal density push. | 08-06-2015 |
20150220744 | SYSTEM FOR EXECUTION OF SECURITY RELATED FUNCTIONS - An apparatus having a first memory circuit, a plurality of arithmetic modules, and a plurality of second memory circuits. The first memory circuit may be configured to read or write data to or from a host. The plurality of arithmetic modules each may be configured to be enabled or disabled in response to control signals received from the first memory circuit. The plurality of second memory circuits may be configured to read or write data to or from the first memory circuit through a data exchange layer. The arithmetic modules provide cryptographic protection of the data. | 08-06-2015 |
20150220452 | System, Method and Computer-Readable Medium for Dynamically Mapping a Non-Volatile Memory Store - Applications that use non-volatile random access memory (NVRAM), such as those that apply file system journal writes and database log writes where write operations apply data sequentially over the NVRAM, map the available capacity of the NVRAM in a virtual address space without compromising performance. The NVRAM is segmented into regions with multiple such regions fitting within a volatile RAM element accessible to the application and the NVRAM. One or more regions are loaded in the volatile RAM and reflected in page tables that reference the regions. The page tables are managed on a host computer executing the application. One region space in the volatile RAM is unused and available for transferred information. Mechanisms are provided for dynamically transferring regions and interfacing with the host computer. As the application sequentially accesses information in the stored regions, older regions are removed and new regions loaded from NVRAM to the volatile RAM. | 08-06-2015 |
20150220388 | Systems and Methods for Hard Error Reduction in a Solid State Memory Device - Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory. | 08-06-2015 |
20150213881 | INTEGRATED READ/WRITE TRACKING IN SRAM - Systems and methods presented herein provide for integrated read/write tracking in an SRAM device. In one embodiment, an SRAM device includes a clock, a memory cell array, a column of dummy bit cells operable to mirror bit line loading of the memory cell array, and a row of dummy bit cells operable to mirror word line loading of the memory cell array. The SRAM devices also includes a read/write tracking cell operable to track read operations from the memory cell array via the dummy bit cells, to track write operations to the memory cell array via the dummy bit cells, and to reset the clock based on the tracked read operations and the tracked write operations. | 07-30-2015 |
20150208076 | MULTI-CORE ARCHITECTURE FOR LOW LATENCY VIDEO DECODER - An apparatus having first, second and third processors of a multi-core processor is disclosed. The first processor is configured to perform one or more first operations in a decoding of a plurality of macroblocks of video in a bitstream. The second processor (i) operates as a slave to the first processor and (ii) is configured to perform one or more second operations in the decoding of the macroblocks. The third processor (i) operates as a slave to the second processor and (ii) is configured to perform one or more third operations in the decoding of the macroblocks. | 07-23-2015 |
20150207648 | Modular Low Power Serializer-Deserializer - Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications. | 07-23-2015 |
20150205752 | HIGH DENSITY MAPPING FOR MULTIPLE CONVERTER SAMPLES IN MULTIPLE LANE INTERFACE - An apparatus having a plurality of buffers, a first circuit and a second circuit is disclosed. The buffers are configured to store a plurality of frames to be transmitted in a plurality of respective lanes of a communication channel. The first circuit is configured to (i) generate a plurality of first groups from a first number of a plurality of samples, at least one of the first groups contains an initial portion of a given one of the samples, and (ii) generate a first of the frames by appending the first groups. The second circuit is configured to (i) receive a final portion of the given sample from the first circuit, (ii) generate a plurality of second groups from the final portion of the given sample and a second number of the samples and (iii) generate a second of the frames by appending the second groups. | 07-23-2015 |
20150200681 | Segmented Digital-To-Analog Converter With Overlapping Segments - In one embodiment, a segmented digital-to-analog converter (DAC) has two configurations (i.e., sub-DACs) with overlapping operating ranges and a data mapper that maps the digital input signal into two different digital signals, one for each sub-DAC. The currents generated by the sub-DACs are combined and then used to generate the corresponding analog output signal. Because the sub-DACs have overlapping operating ranges, the DAC can be calibrated to account for process variations that result in the actual current ratio between the two sub-DACs being different from the ideal, designed current ratio. Calibration algorithms generate calibration constants that are applied by the data mapper when mapping the digital input signal into the two digital signals respectively applied to the two sub-DACs. In this way, high-precision DACs can be implemented without requiring expensive circuitry to handle undesirable current mismatch resulting from process variations. | 07-16-2015 |
20150199991 | Multiple Track Detection - An apparatus for reading data includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, wherein the analog inputs correspond to multiple data tracks on the magnetic storage medium, and wherein the number of analog inputs in the array of analog inputs is greater than the number of data tracks being read, at least one joint equalizer operable to filter the analog inputs to yield an equalized output for each of the data tracks being read, and at least one data detector operable to apply a detection algorithm to the equalized output from the joint equalizer to yield detected values for each of the data tracks being read. | 07-16-2015 |
20150199269 | ENHANCED SSD CACHING - An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines may be associated with meta-data indicating one or more of a dirty state and an invalid state. The controller may be connected to the memory and configured to detect an input/output (I/O) operation directed to a file system. The controller may perform a read-fill based on a hint value when there is a read miss in the cache. The hint value may be based on the application access pattern. The hint value may be passed to a caching layer with a corresponding I/O. | 07-16-2015 |
20150199244 | INTELLIGENT I/O CACHE REBUILD IN A STORAGE CONTROLLER - Systems and methods presented herein provide for redundancy in I/O caching. In one embodiment, a storage controller includes a first cache operable to receive input/output requests between a host system and a storage device, to compress data of the input/output requests, and to cache the compressed data before writing to the storage device. The storage controller also includes a second cache operable to track chunks of the compressed data in the first cache. When the first cache fails, the second cache is operable to cache the tracked chunks of the compressed data that have not been written to the storage device in a third cache while leaving chunks of data in the second cache that have been written to the storage device. | 07-16-2015 |
20150199227 | Fault Detection and Identification in a Multi-Initiator System - A storage system and method for identifying a faulty link the storage system is disclosed. The storage system includes a plurality of target devices and at least one expander configured to communicatively couple a plurality of initiators to the plurality of target devices. Each initiator of the plurality of initiators monitors occurrences of link disruptions independently, wherein upon detecting occurrences of a predetermined number of link disruptions within a predetermined time period, a reporting initiator reports a detection of a faulty link in the multi-initiator topology and requests an arbitrator to identify at least one peer initiator in the multi-initiator topology that shares at least one shared link with the reporting initiator. This reporting initiator and its peer initiators then jointly execute a common diagnostic process to identify the faulty link in the multi-initiator topology. | 07-16-2015 |
20150199149 | FRAMEWORK FOR BALANCING ROBUSTNESS AND LATENCY DURING COLLECTION OF STATISTICS FROM SOFT READS - An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block. | 07-16-2015 |
20150199140 | INTERLEAVING CODEWORDS OVER MULTIPLE FLASH PLANES - An apparatus having an interface to a plurality of memories and a circuit is disclosed. Each memory generally has a plurality of planes and is nonvolatile. The circuit is configured to (i) generate a plurality of codewords by encoding a plurality of data units, (ii) generate a plurality of slices by parsing the codewords, (iii) generate a plurality of pages by interleaving the slices and (iv) write the pages in parallel into respective ones of the planes. | 07-16-2015 |
20150199129 | System and Method for Providing Data Services in Direct Attached Storage via Multiple De-clustered RAID Pools - A system and method for providing Quality of Service (QoS)-based data services in a direct attached storage system including at least one physical drive comprises logically dividing the drive or drives into a plurality of pools implemented according to CRUSH algorithms or other declustered RAID configurations. The plurality of pools are then managed as declustered RAID virtual drives. The system and method further comprises identifying a pool with a performance characteristic and monitoring the pool to detect “hot” data within the pool, which may then be migrated to a pool with a more desirable performance characteristic. The system and method further comprises prioritizing critical operations performed on a pool based on the performance characteristic of the pool. | 07-16-2015 |
20150195357 | ENHANCING ACTIVE LINK UTILIZATION IN SERIAL ATTACHED SCSI TOPOLOGIES - Methods and systems are provided for enhanced link utilization in attached SCSI (SAS) topologies. A SAS expander may be configured to monitor link utilization within a SAS topology, and may manage connection requests received thereby based on the monitoring of link utilization. The monitoring may comprise determining availability of links for at least one node within the SAS topology with respect to other nodes in the SAS topology. This may be done based on pending connection requests, and/or responses thereto received by the SAS expander. It may also be done based on shared link utilization data. The managing may comprise determining for each received connection request when link unavailability in other nodes within the SAS topology prevents connectivity to a destination node corresponding to the connection request. When this situation occurs, the SAS expander may handle the connection request directly. | 07-09-2015 |
20150195108 | RECEIVER WITH PIPELINED TAP COEFFICIENTS AND SHIFT CONTROL - A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag. | 07-09-2015 |
20150194219 | CAPACITANCE COUPLING PARAMETER ESTIMATION IN FLASH MEMORIES - A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more parameters in response to the system of equations. The parameters include one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to the perturbed memory cell. | 07-09-2015 |
20150193564 | SYSTEM AND METHOD FOR USING CLOCK CHAIN SIGNALS OF AN ON-CHIP CLOCK CONTROLLER TO CONTROL CROSS-DOMAIN PATHS - An on-chip clock controller configured to control cross-domain paths using clock chain signals is disclosed. The on-chip clock controller includes a clock bits module configured to receive a clock chain signal and to output an enable signal based upon the clock chain signal. The on-chip clock controller also includes a clock gating module that is communicatively coupled to the clock bits module. The clock gating module is configured to receive a clock signal and to selectively output either a signal corresponding to the clock signal or a non-transitioning signal based upon the enable signal for operating a state storage module. | 07-09-2015 |
20150188576 | Systems and Methods for Efficient Targeted Symbol Flipping - Systems and method relating generally to data processing, and more particularly to systems and methods for modifying symbols in a data set prior to re-processing. | 07-02-2015 |
20150188551 | CLOCK RECOVERY USING QUANTIZED PHASE ERROR SAMPLES USING JITTER FREQUENCY-DEPENDENT QUANTIZATION THRESHOLDS AND LOOP GAINS - A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples. | 07-02-2015 |
20150187385 | Systems and Methods for Multi-Head Balancing in a Storage Device - Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. | 07-02-2015 |
20150187384 | TWO-DIMENSIONAL MAGNETIC RECORDING READER OFFSET ESTIMATION - A method for enhancing read performance in a multi-reader two-dimensional magnetic recording system comprising first and second readers includes: receiving first and second analog read signals from the first and second readers, respectively; sampling the first and second analog read signals to generate first and second sampled signals, respectively, each of the first and second sampled signals comprising an integer component, indicative of a value of a corresponding one of the first and second analog read signals, respectively, at an integer multiple of a corresponding sampling period associated therewith, and/or a fractional component, indicative of a value of the corresponding one of the first and second analog read signals, respectively, at an arbitrary point in time between integer multiples of the corresponding sampling period; and combining the integer and/or fractional components of the respective first and second sampled signals to thereby generate a reader offset estimation signal. | 07-02-2015 |
20150186317 | METHOD AND APPARATUS FOR DETECTING THE INITIATOR/TARGET ORIENTATION OF A SMART BRIDGE - Methods and systems are provided for adaptive interconnect bridging. A first interconnect type may be determined for a first bridging interface, which is configurable to support a first plurality of interconnect types; and a second interconnect type may be determined for a second bridging interface that is configurable to support a second plurality of interconnect types. The first bridging interface may then be configured based on the first interconnect type, and the second bridging interface may then be configured based on the second interconnect type. Further, the orientation of bridging may be configured based on the determined interconnect types as well as on functions of devices attached to the first bridging interface and the second bridging interface. One of the first bridging interface and the second bridging interface may be assigned a function of ‘initiator’ whereas the other one of the first bridging interface and the second bridging interface a function of ‘target’. | 07-02-2015 |
20150180512 | Systems and Methods of Converting Detector Output To Multi-Level Soft Information - A data processing system includes a binary data detector having a hard decision output, a reliability calculator operable to calculate an error pattern reliability metric for each of a number of dominant error patterns associated with the hard decision output, and a converter operable to convert the error pattern reliability metrics to multi-level soft information. | 06-25-2015 |
20150179213 | Servo Channel With Equalizer Adaptation - A servo system includes an equalizer circuit operable to filter digital servo data samples according to filter tap coefficients to yield equalized data, a detector circuit operable to apply a data detection algorithm to the equalized data to yield hard decisions, a convolution circuit operable to yield ideal digital data based on the hard decisions and on target values, a subtraction circuit operable to subtract the ideal digital data from the equalized data to yield an adaptation error signal, an error gradient calculator operable calculate an error gradient signal based at least in part on the adaptation error signal, and a tap adaptation circuit operable to calculate values of the filter tap coefficients based on the error gradient signal. | 06-25-2015 |
20150178312 | ATTRIBUTE-BASED ASSISTANCE REQUEST SYSTEM FOR SEQUENTIALLY CONTACTING NEARBY CONTACTS WITHOUT HAVING THEM DIVULGE THEIR PRESENCE OR LOCATION - An anonymous non-emergency help system matches capabilities of potential helpers to a requestor's needs. Helpers identify the type of assistance they are willing to provide and then agree to become available anonymously. The helpers are contacted sequentially for assistance based on proximity to the requestor. The nearest helper may choose to respond or decline the request. This anonymous location process occurs sequentially, awaiting a requestor-defined timeout, until one of the identified individuals agrees to fulfill the request or until there are no other proximate individuals that meet the specific request criteria. A call for help is not broadcast, but helpers are chosen based on their disclosed skills/capabilities, attributes, and their proximity to the requestor. The attributes are related to at least one of speed and trajectory relative to the requestor, time the helper is in a particular location, and altitude difference between the requestor and the helper. | 06-25-2015 |
20150178201 | SYSTEM FOR EFFICIENT CACHING OF SWAP I/O AND/OR SIMILAR I/O PATTERN(S) - An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache may comprise one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. The controller is connected to the memory and configured to (A) process normal read/write operations in a first mode and (B) process special read/write operations in a second mode by (i) tracking a write followed by read condition on each of said cache windows and (ii) discarding data on the cache-lines associated with the cache windows after completion of the write followed by a read condition on the cache-lines. | 06-25-2015 |
20150178152 | PREVENTING PROGRAMMING ERRORS FROM OCCURRING WHEN PROGRAMMING FLASH MEMORY CELLS - Mis-programming of MSB data in flash memory is prevented by using ECC decoding logic on the flash die that error corrects the LSB values prior to the LSB values being used in conjunction with the MSB values to determine the proper reference voltage ranges. Error correcting the LSB page data prior to using it in combination with the MSB page data to determine the reference voltage ranges ensures that the reference voltage ranges will be properly determined and programmed into the flash cells. | 06-25-2015 |
20150178149 | METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS - An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types. | 06-25-2015 |
20150163363 | LOW COMPLEXITY TONE/VOICE DISCRIMINATION METHOD USING A RISING EDGE OF A FREQUENCY POWER ENVELOPE - An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal. | 06-11-2015 |
20150162781 | Illumination-Based Charging System for Portable Devices - The disclosure is directed to illumination-based charging of one or more portable devices. According to an embodiment of the disclosure, an illumination-based charging pad includes a platform, a plurality of illumination sources, a plurality of photosensitive detectors, and a controller. The controller performs a scan by activating the illumination sources and detecting reflected illumination from an illuminated surface of at least one portable device disposed upon the platform. The controller determines a set of one or more illumination sources that are at least partially overlaid by the portable device based upon the detected illumination. The controller selects one or more illumination sources for charging the portable device at least partially based upon the set of one or more illumination sources determined to be overlaid by the portable device. | 06-11-2015 |
20150162057 | MULTIPLE RETRY READS IN A READ CHANNEL OF A MEMORY - An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads. | 06-11-2015 |
20150161045 | Slice Formatting and Interleaving for Interleaved Sectors - A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence. | 06-11-2015 |
20150160886 | METHOD AND SYSTEM FOR PROGRAMMABLE SEQUENCER FOR PROCESSING I/O FOR VARIOUS PCIe DISK DRIVES - Disclosed is a system and method for using a programmable sequencer to produce a required command for a particular standard, or format, being used by the PCIe disk drive. A PCIe disk drive may support a different standard, or format. A mix of any number of different standards, or formats, is permitted in the system and method. For each message, a different set of instructions can be selected for the conversion process. | 06-11-2015 |
20150160869 | Systems and Methods for Multi-Dimensional Data Processor Operational Marginalization - Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability. | 06-11-2015 |
20150154138 | WIDE PORT EMULATION AT SERIAL ATTACHED SCSI EXPANDERS - Methods and structure for emulating wide ports at an expander are provided. An exemplary system includes a Serial Attached Small Computer System Interface (SAS) expander. The expander includes a plurality of physical links, and a controller. The controller is able to identify a physical link coupled with a device, to generate a plurality of virtual physical links that are configured as a virtual wide port coupled with the device, and to present the virtual wide port at the expander in place of the physical link. | 06-04-2015 |
20150154114 | SYSTEM AND METHOD TO INTERLEAVE MEMORY - A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed. | 06-04-2015 |
20150149871 | Flash Channel With Selective Decoder Likelihood Dampening - An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding. | 05-28-2015 |
20150149856 | DECODING WITH LOG LIKELIHOOD RATIOS STORED IN A CONTROLLER - An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values. | 05-28-2015 |
20150149855 | BIT-LINE DEFECT DETECTION USING UNSATISIFIED PARITY CODE CHECKS - An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines. | 05-28-2015 |
20150149840 | Read Retry For Non-Volatile Memories - An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns. | 05-28-2015 |
20150149698 | ELIMINATING OR REDUCING PROGRAMMING ERRORS WHEN PROGRAMMING FLASH MEMORY CELLS - Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur. | 05-28-2015 |
20150149395 | INCREMENTAL UPDATES FOR ORDERED MULTI-FIELD CLASSIFICATION RULES WHEN REPRESENTED BY A TREE OF LONGEST PREFIX MATCHING TABLES - An apparatus includes a memory and a processor. The memory may be configured to store at least a portion of a multi-level tree representation of an ordered multi-field rule-based classification list. The tree representation includes at least one non-leaf level and one or more leaf levels. Each entry in the at least one non-leaf level contains a count value indicating a number of rules having a matching field. Entries in at least one of the one or more leaf levels include rule pointers arranged in priority order. The processor may be configured to incrementally insert or delete rules, while preserving ordering semantics of the tree representation. | 05-28-2015 |
20150145740 | Integrated Frequency Multiplier and Slot Antenna - A metal substrate with a slot therein forms a slot antenna, the slot having a major axis and a minor axis. A dielectric layer has a plurality of terminals disposed on or in the dielectric layer and the layer is attached on one surface of the substrate. The terminals of a non-linear device, such as a diode, are connected to corresponding terminals of the dielectric layer. The non-linear device is positioned proximate the slot and is substantially aligned with a minor axis of the slot. A transmission line feeds an RF signal to the non-linear device that in turn frequency multiplies the RF signal to an RF signal that is radiated by the slot antenna. The dielectric layer is positioned in the slot such that the radiated RF signal has a desired output power. A protective layer is applied to the other surface of the substrate to cover the slot. | 05-28-2015 |
20150143202 | Systems and Methods for Soft Decision Generation in a Solid State Memory System - Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. | 05-21-2015 |
20150143196 | Systems and Methods for FAID Follower Decoding - Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information. | 05-21-2015 |
20150143164 | I/O REQUEST MIRRORING IN A CLUSTERED STORAGE SYSTEM - Clustered storage systems and methods are presented herein. One clustered storage system includes a logical volume comprising first and second pluralities of storage devices. The first plurality of storage devices is different from the second plurality of storage devices and includes at least the same data as the second plurality of devices. The storage system also includes a first storage node operable to process first I/O requests to the first plurality of storage devices and a second storage node communicatively coupled to the first storage node and operable to process second I/O requests to the second plurality of storage devices. An I/O request of the first I/O requests initiates a redirection condition that the first storage node detects. Then, based on the redirection condition, the first storage node directs the second storage node to process data of the I/O request. | 05-21-2015 |
20150138876 | GLOBAL BITLINE WRITE ASSIST FOR SRAM ARCHITECTURES - An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment. | 05-21-2015 |
20150138864 | MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES - Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines. | 05-21-2015 |
20150138863 | INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES - An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines. | 05-21-2015 |
20150137855 | Current To Voltage Converter - An apparatus for converting current to voltage includes a pair of current inputs, a differential voltage output connected to the pair of current inputs, a current summing node connected to the pair of current inputs through a first resistor branch, a common mode feedback node connected to the pair of current inputs through a second resistor branch, an amplifier operable to generate a current control signal based at least in part on a voltage at the common mode feedback node, and a current controller operable to control a current through the current summing node based at least in part on the current control signal. | 05-21-2015 |
20150135032 | Detection/Erasure of Random Write Errors Using Converged Hard Decisions - A low-density parity-check decoder in a system with multi-level cells identifies zones of reliability where write errors or stuck cells are identifiable. The system uses assumedly successfully decoded pages associated with bits in a cell to identify candidate write errors or stuck cells and erases a corresponding log-likelihood ratio even where such log-likelihood ratio is saturated, thereby breaking a potential trapping set without post-processing. | 05-14-2015 |
20150135031 | DYNAMIC PER-DECODER CONTROL OF LOG LIKELIHOOD RATIO AND DECODING PARAMETERS - An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information. | 05-14-2015 |
20150135006 | System and Method of Write Hole Protection for a Multiple-Node Storage Cluster - The disclosure is directed to preserving data consistency in a multiple-node data storage system. According to various embodiments, a write log is maintained including log entries for data transfer requests being served by a respective node of the multiple-node data storage system. Rather than maintaining a full write journal of data and parity associated with each data transfer request, the log entries only need to identify portions of the virtual volume being updated according to the data transfer requests served by each node. When a first node fails, a second node takes over administration of a virtual volume for the failed node. Upon taking over for the first (failed) node, the second node resolves any inconsistencies between data and parity in portions of the virtual volume identified the respective log entries. Accordingly, write holes are prevented without substantially increasing memory usage or system complexity. | 05-14-2015 |
20150134855 | Decoupling Host and Device Address Maps for a Peripheral Component Interconnect Express Controller - A controller includes a virtual memory mapped to device-side Peripheral component interconnect express address space includes virtual buffers allocation for each data transfer. Each virtual buffer is associated with a scatter/gather list entry in a host memory. The controller executes direct transfers between Peripheral component interconnect express devices and host memory without introducing address mapping dependencies between the host and device domains. | 05-14-2015 |
20150134613 | Systems and Methods for Lost Synchronization Data Set Reprocessing - Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. | 05-14-2015 |
20150131373 | Incremental Programming Pulse Optimization to Reduce Write Errors - In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed using more program voltage pulses, narrower program voltage pulses or some other modification to the incremental step programming pulse to reduce the range where the intermediate least significant (lower) bit read voltage may be erroneous, thereby reducing the probability of write errors when the most significant page (upper) is programmed. | 05-14-2015 |
20150128006 | DEVICE QUALITY METRICS USING UNSATISFIED PARITY CHECKS - An apparatus having a device and a circuit is disclosed. The device is configured to convey a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword, (iii) generate a value by counting a number of unsatisfied parity checks in the syndrome and (iv) generate a quality metric of the device according to the value. | 05-07-2015 |
20150127883 | REDUCTION OR ELIMINATION OF A LATENCY PENALTY ASSOCIATED WITH ADJUSTING READ THRESHOLDS FOR NON-VOLATILE MEMORY - Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations. | 05-07-2015 |
20150121173 | Systems and Methods for Internal Disk Drive Data Compression - The present invention is related to systems and methods for data storage compression. | 04-30-2015 |
20150121088 | METHOD OF MANAGING ALIGNED AND UNALIGNED DATA BANDS IN A SELF ENCRYPTING SOLID STATE DRIVE - An apparatus includes a storage medium and a controller. The storage medium generally stores user data in logical pages. The controller may be configured to encrypt and decrypt user data during write and read operations, respectively. The user data is generally in a plurality of data bands. Each data band is encrypted and decrypted using a unique media encryption key. When a boundary between a pair of data bands is within a logical page, the controller may be configured to create two logical page instances, a first logical page instance storing data from a first data band of the pair of data bands and a second logical page instance storing data from a second data band of the pair of data bands. The first and second logical page instances are encrypted and decrypted using the unique media encryption key of the first and second data bands, respectively. | 04-30-2015 |
20150120989 | Tracking and Utilizing Second Level Map Index for Recycling of Solid State Drive Blocks - A recycling method for a solid state drive is disclosed. The method includes selecting a logical block for recycle wherein the logical block includes a plurality of pages across a plurality of flash dies. The method also includes retrieving an address map index record associated with the logical block selected for recycle. For each particular address map index stored in the address map index record, the recycling method retrieves a set of address map entries referenced by the particular address map index, determines whether any page in the logical block is referenced by the set of address map entries, and if at least one page in the logical block is referenced by the set of address map entries, the method writes the at least one page to a different logical block. The method further includes erasing the plurality of pages in the logical block. | 04-30-2015 |
20150120981 | Data Interface for Point-to-Point Communications Between Devices - A data interface is provided for point-to-point communications between two devices, such as a read channel and a disk controller in an HDD system. An interface for communications from a transmitting device to a receiving device comprises a data bus configured to communicate m bits of data and a corresponding n bit data tag, wherein a given n bit data tag identifies a data type of a corresponding m bits of data on the data bus. An acknowledge signal from the receiving device optionally indicates that data on the data bus has been received and that the data on the data bus can be changed to a new value. A valid flag optionally indicates when a new predefined m-bit data value and corresponding n-bit tag value are on the data bus. | 04-30-2015 |
20150117226 | METHOD AND SYSTEM FOR SESSION BASED DATA MONITORING FOR WIRELESS EDGE CONTENT CACHING NETWORKS - Aspects of the disclosure pertain to methods and systems that are configured to monitor data usage at a network edge. In an implementation, a method includes monitoring data usage information associated with a mobile user session between a mobile device and a plurality of edges nodes of a communication network, where the plurality of edge nodes includes at least a beginning edge node and a final edge node. The method also includes storing data usage information from the monitored data usage information, the stored data usage information including data associated with the transfer of cached data stored at the plurality of edge nodes. The method further includes forwarding the stored data access information to a central database of the communication network. | 04-30-2015 |
20150117097 | Systems and Methods for Sub-Zero Threshold Characterization in a Memory Cell - Systems and method relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. | 04-30-2015 |
20150113354 | GENERATING SOFT DECODING INFORMATION FOR FLASH MEMORY ERROR CORRECTION USING HARD DECISION PATTERNS - A flash memory controller having soft-decoding error correcting code (ECC) logic generates log likelihood ratio or similar ECC decoder soft input information from decision patterns obtained from reading data from the same portion of flash memory two or more times. Each decision pattern corresponds to a voltage region bordering one of the reference voltages. Each decision pattern represents a combination of flash memory bit value decisions for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell. Numerical values are then computed in response to combinations of the flash memory bit value decisions represented by the decision patterns. The numerical values are provided to the soft-decoding ECC logic to serve as soft input information. | 04-23-2015 |
20150113335 | SENDING FAILURE INFORMATION FROM A SOLID STATE DRIVE (SSD) TO A HOST DEVICE - A system, method, and computer program product are provided for a host device to request and obtain failure information from a solid state drive (SSD). In operation, an error is detected during an operation associated with a solid state drive. Additionally, a command to return failure information is provided to the solid state drive by a host device. Further, the failure information is sent from the solid state drive to the host device, the failure information including failure information associated with the solid state drive. | 04-23-2015 |
20150113318 | Systems and Methods for Soft Data Utilization in a Solid State Memory System - Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. | 04-23-2015 |
20150113312 | SYSTEM AND METHOD FOR DETECTING SERVER REMOVAL FROM A CLUSTER TO ENABLE FAST FAILOVER OF STORAGE - Aspects of the disclosure pertain to a system and method for detecting server removal from a cluster to enable fast failover of storage (e.g., logical volumes). A method of operation of a storage controller of a cluster is disclosed. The method includes receiving a signal. The method further includes, based upon the received signal, determining that communicative connection between a second storage controller of the cluster and the first storage controller of cluster is unable to be established. The method further includes determining whether communicative connection between the first storage controller and expanders of first and second enclosure services manager modules of the cluster is able to be established. The method further includes, when it is determined that communicative connection between the first storage controller and the expanders of the first and second enclosure services manager modules of the cluster is able to be established, performing a failover process. | 04-23-2015 |
20150113205 | Systems and Methods for Latency Based Data Recycling in a Solid State Memory System - Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. | 04-23-2015 |
20150110165 | Transmitter Training Using Receiver Equalizer Coefficients - A method of adjusting a post-cursor tap weight in a transmitter FIR filter in a high-speed digital data transmission system. A receiver, over a forward channel, receives a signal from the transmitter and equalizes the received signal using an adaptive analog equalizer coupled to the forward channel and a decision feedback equalizer (DFE) coupled to the analog equalizer. A gain coefficient used to adjust the peaking by the analog equalizer is adapted using an error signal generated by the DFE. The post-cursor tap weight of the transmitter filter is adjusted up or down based on a comparison of the gain coefficient to a set. of limits. The post-cursor tap weight is transmitted to the transmitter over a reverse channel and then equalizers in the receiver readapt. Alternatively, eye opening data and a DFE tap coefficient are used to determine whether the post-cursor tap weight is adjusted up or down. | 04-23-2015 |
20150109052 | CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS - In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode. | 04-23-2015 |
20150106675 | Systems and Methods for Multi-Algorithm Concatenation Encoding and Decoding - Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. | 04-16-2015 |
20150106666 | Speculative Bit Error Rate Calculator - An apparatus for calculating a speculative bit error rate includes a data decoder operable to iteratively decode received data to yield decoded data, and a speculative bit error calculator operable to calculate a bit error rate based on the decoded data and the received data while the data decoder is decoding the received data. The bit error rate is updated with each decoding iteration in the data decoder. | 04-16-2015 |
20150106577 | DE-INTERLEAVING ON AN AS-NEEDED BASIS - One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module. | 04-16-2015 |
20150103961 | DIGITAL FREQUENCY BAND DETECTOR FOR CLOCK AND DATA RECOVERY - A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR. | 04-16-2015 |
20150103604 | MEMORY ARRAY ARCHITECTURES HAVING MEMORY CELLS WITH SHARED WRITE ASSIST CIRCUITRY - A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configuration. The first inverter is connected between the first virtual power supply node and the second power supply node, and the second inverter is connected between the second virtual power supply node and the second power supply node. The write assist circuit selectively supplies power to the first and second virtual power supply nodes during memory access operations, and is controlled by a first control signal to switchably connect the first power supply node to and from the first and second virtual power supply nodes, and a second control signal to switchably connect the one or both of the first and second virtual power supply nodes to a virtual power supply node of an adjacent memory cell of an adjacent row in the memory array. | 04-16-2015 |
20150100810 | ADAPTIVE POWER-DOWN OF DISK DRIVES BASED ON PREDICTED IDLE TIME - Systems and methods presented herein provide a storage system that adaptively powers-down one or more disk drives based on the predicted idle time of each disk drive. One embodiment includes a storage controller that includes a processor operable to track idle durations of the disk drive. When an idle duration ends, the processor associates the idle duration with a time window that includes that idle duration. Each time window is associated with a number of previous idle durations of the disk drive. Upon detection of a current idle duration, the processor identifies a time window with the highest number of previous idle durations of the disk drive. Then, the processor determines whether a maximum time associated with the identified time window exceeds a predetermined threshold. When the maximum time exceeds the predetermined threshold, the processor powers-down the disk drive. | 04-09-2015 |
20150097611 | VOLTAGE FOLLOWER HAVING A FEED-FORWARD DEVICE - A circuit is described that includes a voltage follower device and a feed-forward device. In an implementation, the circuit includes a voltage follower device that includes an input and an output. The voltage follower device is configured to transfer a voltage signal at least substantially unchanged from the input to the output of the voltage follower device. The circuit also includes a feed-forward device that includes an input and an output. The input of the feed-forward device is connected to the input of the voltage follower device and the output of the feed-forward device is connected to the output of the voltage follower device. The feed-forward device is configured to output the voltage signal to the output of the voltage follower device. | 04-09-2015 |
20150092489 | FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POINTS OF CELL VOLTAGE DISTRIBUTIONS USING HISTOGRAMS - Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations. | 04-02-2015 |
20150092290 | Non-Binary Layered Low Density Parity Check Decoder - A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages. | 04-02-2015 |
20150091620 | REDUCING CURRENT VARIATION WHEN SWITCHING CLOCKS - An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal. | 04-02-2015 |
20150089330 | Systems and Methods for Enhanced Data Recovery in a Solid State Memory System - Systems and method relating generally to data processing, and more particularly to systems and methods for recovering data from a solid state memory. | 03-26-2015 |
20150089132 | DYNAMIC STORAGE VOLUME CONFIGURATION BASED ON INPUT/OUTPUT REQUESTS - A storage system includes a plurality hard disk drives and a plurality of solid-state drives and a storage controller operable to manage the hard disk drives and solid-state drives as a plurality of logical volumes, and categorize input/output requests to the logical volumes into types based on sizes of the input/output requests (e.g., smaller and larger). The storage controller is also operable to reconfigure the logical volumes from the hard disk drives and the solid-state drives based on the types of the input/output requests to the logical volumes. A first of the reconfigured logical volumes occupies a first portion of at least one of the solid-state drives and a first portion of at least one of the hard disk drives. The storage controller is further operable to direct the first type of the input/output requests to the first portion of the solid-state drive occupied by the first reconfigured logical volume. | 03-26-2015 |
20150089102 | SOLID STATE DRIVES THAT CACHE BOOT DATA - Methods and structure for utilizing a Solid State Drive (SSD) to enhance boot time for a computer. The computer includes an SSD that stores a boot cache for an Operating System of a computer, a Hard Disk Drive that stores the Operating System, and a processor. The processor is able to load an interrupt handler that intercepts Input/Output requests directed to the Hard Disk Drive prior to loading a kernel of the Operating System. The interrupt handler is able to determine whether each intercepted request can be serviced with data from the boot cache, and to redirect a request to the SSD instead of the Hard Disk Drive if the request can be serviced with data from the boot cache. | 03-26-2015 |
20150085957 | Method Of Calibrating a Slicer In a Receiver Or the Like - A method of calibrating data slicer-latches in a receiver to remove offset errors in the slicer-latches. A known voltage is applied to all but one of the inputs of the slicer-latch. The remaining input receives an offset cancelation voltage from a DAC is stepped upward from a minimum voltage until the slicer-latch output transitions by incrementing a codeword to the DAC and the codeword that resulted the transition is saved. Then the offset cancelation voltage is swept downward in steps from a maximum voltage until the slicer-latch output transitions and the codeword that caused the transition is averaged with the stored codeword. The average of the codewords is applied to the DAC to generate the offset cancelation voltage used during normal operation of the receiver. | 03-26-2015 |
20150085592 | Bit-Line Discharge Assistance in Memory Devices - One embodiment is an apparatus that has a memory array, a discharge device, and a discharge assistance controller. The memory array has memory cells arranged in at least one column that is coupled to a read bit line, and the discharge device is configured to provide discharge assistance to the read bit line. The discharge assistance controller is configured to modify duration of the discharge assistance in correlation with capacitance of the read bit line. | 03-26-2015 |
20150085587 | PING-PONG BUFFER USING SINGLE-PORT MEMORY - A method of controlling a ping-pong buffer includes selectively providing one of a ping gated write clock signal and a ping gated read clock signal to a single-port ping buffer, and selectively providing a pong gated write clock signal or a pong gated read clock signal to a single-port pong buffer. A controller of a ping-pong buffer includes a ping multiplexer and a pong multiplexer. The ping multiplexer selectively provides a ping gated write clock signal or a ping gated read clock signal to a single-port ping buffer. The pong multiplexer selectively provides a pong gated write clock signal or a pong gated read clock signal to a single-port pong buffer. A ping-pong buffer system includes a ping buffer, a pong buffer, a ping multiplexer, and a pong multiplexer. The ping buffer and pong buffer each include a single-port memory. | 03-26-2015 |
20150085392 | System and Method for Monitoring Preamble Signal Quality - The disclosure is directed to a system and method of determining signal quality based upon at least one of: a comparison of energy content of the signal to a threshold energy content, a comparison of energy content of the fundamental harmonic of the signal to a specified percentage of the energy content of the signal, and a comparison of a difference between phase of the signal and a target phase to a threshold phase difference. | 03-26-2015 |
20150082124 | SPATIALLY DECOUPLED REDUNDANCY SCHEMES FOR A SOLID STATE DRIVE (SSD) - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to write user data using a redundancy scheme. Information about the redundancy is (i) stored in a location separate from the data and (ii) used to recover potentially corrupted user data. | 03-19-2015 |
20150082121 | METHOD OF ERASE STATE HANDLING IN FLASH CHANNEL TRACKING - An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters. | 03-19-2015 |
20150082115 | Systems and Methods for Fragmented Data Recovery - Systems and method relating generally to data processing, and more particularly to systems and methods for fragmenting a data set and recovering the fragmented data set. | 03-19-2015 |
20150081649 | IN-LINE DEDUPLICATION FOR A NETWORK AND/OR STORAGE PLATFORM - An apparatus comprising a classification block, a pattern generator block, a hash key block and a replacement block. The classification block may be configured to (i) receive a data signal and (ii) identify a portion of the data signal that contains a duplicated data pattern. The pattern generation block may be configured to generate a common continuous pattern of data in response to the data signal. The hash key block may be configured to generate a hash key representing the duplicated data pattern. The replacement block may be configured to replace the duplicated data pattern with the hash key. | 03-19-2015 |
20150081626 | Systems and Methods for Recovered Data Stitching - Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set. | 03-19-2015 |
20150078103 | SENSING TECHNIQUE FOR SINGLE-ENDED BIT LINE MEMORY ARCHITECTURES - A sense amplifier includes a latch, first and second switching circuitry, and control circuitry. The first switching circuitry selectively couples a voltage supply node and/or a voltage return node of the latch to a voltage supply and/or a voltage return of the sense amplifier, respectively, as a function of a first control signal. The second switching circuitry couples a first sensing node in the sense amplifier with a first bit line of a first sub-bank in one of multiple memory banks in a memory device as a function of a second control signal, and couples a second sensing node with a second bit line of a second sub-bank as a function of the second control signal. The control circuitry imparts an imbalance between the first and second sensing nodes which varies as a function of a third control signal. | 03-19-2015 |
20150077277 | REDUCED POLAR CODES - A method for encoding a reduced polar code is disclosed. The method generally includes steps (A) to (C). Step (A) may generate the intermediate codeword by polar code encoding input data. Step (B) may remove one or more bits from one of (i) a first part of the intermediate codeword and (ii) a second part of the intermediate codeword. Step (C) may generate an output codeword by concatenating the first part of the intermediate codeword with the second part of the intermediate codeword after the bits are removed. | 03-19-2015 |
20150074355 | EFFICIENT CACHING OF FILE SYSTEM JOURNALS - An apparatus includes a memory and a controller. The memory may be configured to implement a cache and store meta-data. The cache generally comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines is associated with meta-data indicating one or more of a dirty state, an invalid state, and a partially dirty state. The controller is connected to the memory and may be configured to (i) detect an input/output (I/O) operation directed to a file system recovery log area, (ii) mark a corresponding I/O using a predefined hint value, and (iii) pass the corresponding I/O along with the predefined hint value to a caching layer. | 03-12-2015 |
20150074328 | DYNAMIC MAP PRE-FETCHING FOR IMPROVED SEQUENTIAL READS OF A SOLID-STATE MEDIA - Described embodiments provide a solid-state drive (SSD) including a media controller and a solid-state media. A control processor of the media controller determines a logical address, a transfer size, and map data based on the logical address and transfer size, associated with a read request received from a host device. Based on the logical address and a sequential zone defined based on one or more previous read requests, the control processor determines whether the received read request is a sequential read. A map data pre-fetch size is adjusted based on the transfer size of the received read request and whether the received read request is a sequential read. A corresponding portion of the map data is transferred from the solid-state media to a map cache coupled to the control processor, the transferred portion having a size equal to the adjusted map data pre-fetch size. | 03-12-2015 |
20150074327 | Active Recycling for Solid State Drive - A solid state drive and a method for providing active recycling for the solid state drive are disclosed. The solid state drive includes a plurality of blocks and each of the plurality of blocks includes a plurality of pages. The method steps include receiving a read request from a data requester; identifying at least one page containing data requested by the read request; determining whether the at least one page belongs to a block identified for active recycling; writing the at least one page to a different block when the at least one page belongs to the block identified for active recycling; and sending the at least one page to the data requester in response to the read request. | 03-12-2015 |
20150070796 | Array-Reader Based Magnetic Recording Systems With Mixed Synchronization - A magnetic recording system includes an array of analog inputs operable to receive an array of analog signals retrieved from a magnetic storage medium, where one of the array of analog signals corresponds with a reference channel, a timing recovery circuit operable to generate a clock signal based on the analog signal for the reference channel, a number of analog to digital converters each operable to sample one of the array of analog signals based on the clock signal to yield a number of digital channels, and a joint equalizer operable to filter the digital channels to yield an equalized output. | 03-12-2015 |
20150067685 | Systems and Methods for Multiple Sensor Noise Predictive Filtering - The present invention is related to systems and methods for branch metric calculation based on multiple data streams in a data processing circuit. | 03-05-2015 |
20150067349 | VIRTUAL BANDS CONCENTRATION FOR SELF ENCRYPTING DRIVES - An apparatus includes a storage device and a host device. The storage device may be configured to encrypt and decrypt user data during write and read operations, respectively. The host device is communicatively coupled to the storage device. The host device may be configured to execute the write and read operations by concentrating a first number of virtual bands into a second number of real bands, wherein said second number is smaller than said first number. | 03-05-2015 |
20150067253 | INPUT/OUTPUT REQUEST SHIPPING IN A STORAGE SYSTEM WITH MULTIPLE STORAGE CONTROLLERS - Systems and methods presented herein provide for input/output shipping between storage controllers in a storage system. One storage system comprises a plurality of logical volumes, a host driver operable to process input/output requests to the logical volumes, and a plurality of storage controllers coupled between the server and the logical volumes. A first of storage controllers is operable to receive an input/output request from the host driver for one of the logical volumes, and transfer a command to a second of the storage controllers to retrieve the data of the input/output request. The second storage controller processes the command from the first storage controller, and retrieves the data associated with the input/output request. | 03-05-2015 |
20150063217 | MAPPING BETWEEN VARIABLE WIDTH SAMPLES AND A FRAME - An apparatus having a plurality of first circuits, a second circuit and a plurality of processor circuits is disclosed. Each first circuit is configured to store a plurality of samples corresponding to a plurality of channels. At least two of the samples having different widths. The second circuit is configured to store a plurality of frames each sized to contain two or more of the samples. The processor circuits are configured to (i) read the samples from the first circuits respectively, (ii) generate a transmit one of the frames by writing the samples to the second circuit based on one or more access pointers and (iii) pass control of the access pointers among the processor circuits. | 03-05-2015 |
20150062738 | Systems and Methods for Variable Sector Count Spreading and De-Spreading - Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. | 03-05-2015 |