| LINK_A_MEDIA DEVICES CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20120131423 | BINARY BCH DECODERS - Binary Bose-Chaudhuri-Hocquenghem (BCH) encoded data is processed by obtaining a set of syndromes associated with the binary BCH encoded data, including a subset of odd-term syndromes and a subset of even-term syndromes. During initialization of a variant error-locator polynomial, {circumflex over (Ω)}(x), the subset of even-term syndromes, but not the subset of odd-term syndromes, are loaded into the variant error-locator polynomial, {circumflex over (Ω)} | 05-24-2012 |
| 20120127799 | WRITE-PRECOMPENSATION AND VARIABLE WRITE BACKOFF - A technique for writing data is disclosed. The technique includes estimating an amount of additional voltage on a victim cell of a solid-state storage device caused by writing to one or more other cells in the solid-state storage device, determining a modified write value for the victim cell based at least in part on a desired value for the victim cell and the estimated amount of additional voltage, and writing the modified write value to the victim cell. | 05-24-2012 |
| 20120117414 | PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS - A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop. | 05-10-2012 |
| 20120113782 | STORAGE MEDIA DEFECT DETECTION - Detecting a defect on a storage device is disclosed. Detecting includes receiving a signal read from a storage device, sampling the signal to obtain a set of signal samples, wherein the sampling starts at an arbitrary time, computing a defect value for a defect type using the set of signal samples, comparing the defect value with a threshold associated with the defect type, determining whether there is a defect of the defect type based at least in part on the comparison, and in the event that a defect is detected, outputting an indication associated with the defect. | 05-10-2012 |
| 20120105994 | INTER-TRACK INTERFERENCE CANCELATION FOR SHINGLED MAGNETIC RECORDING - Inter-track interference cancelation is disclosed, including: receiving an input sequence of samples associated with a track on magnetic storage; using a processor to generate inter-track interference (ITI) data associated with a first side track including by performing a correlation between the input sequence of samples and a sequence of data associated with the first side track. | 05-03-2012 |
| 20120099217 | SPLIT SECTOR FORMATTING OF STORAGE DISKS - A length of a separator to be skipped on the storage disk is compared with a threshold. The threshold is associated with a maximum value for which a timing loop is able to be paused without causing the timing loop to have inaccurate timing. If the length is greater than the threshold, a first split sector format is assigned to the split sector and that information is recorded. In such cases, a first portion and a second portion both include synchronization information. If the length is less than the threshold, a second split sector format is assigned to the split sector and that information is recorded. In such cases, the first portion includes synchronization information and the second portion of the split sector excludes synchronization information. | 04-26-2012 |
| 20120081971 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits. | 04-05-2012 |
| 20120076196 | DECISION DIRECTED TIMING RECOVERY USING MULTI-PHASE DETECTION - A set of one or more samples is received. Using a first signal processor associated with a first phase offset, a first decision and a first error value are generated using the set of samples. Using a second signal processor associated with a second phase offset, a second decision and a second error value are generated using the set of samples. This includes interpolating the set of samples to obtain a set of interpolated samples at the second phase offset and generating the second decision and the second error value using the set of interpolated samples at the second phase offset. A selection associated with the first decision and the second decision is made based at least in part on the first error value and the second error value. | 03-29-2012 |
| 20120019950 | PAD BIT INJECTION DURING READ OPERATION TO IMPROVE FORMAT EFFICIENCY - Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel. | 01-26-2012 |
| 20110252294 | IMPLEMENTATION OF LDPC SELECTIVE DECODING SCHEDULING - A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group. | 10-13-2011 |
| 20110239085 | ECC WITH OUT OF ORDER COMPLETION - Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder. | 09-29-2011 |
| 20110191653 | QUASI-CYCLIC LDPC ENCODING AND DECODING FOR NON-INTEGER MULTIPLES OF CIRCULANT SIZE - In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the padded data over the decision and reliability information corresponding to the padded data during message passing. Zero padding is removed from the decoded data. | 08-04-2011 |
| 20110185264 | LDPC DECODING WITH ON THE FLY ERROR RECOVERY - It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder. | 07-28-2011 |
| 20110125959 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored. | 05-26-2011 |
| 20110115659 | OFFSET COMPENSATION SCHEME USING A DAC - An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset. | 05-19-2011 |
| 20110096433 | DECOUPLING MAGNETO-RESISTIVE ASYMMETRY AND OFFSET LOOPS - Signal correction is performed by determining an offset error based at least in part on a first portion of a signal within a first amplitude range. The offset error is associated with error due to offset in the signal. An signal error, associated with error due to offset and magneto-resistive asymmetry (MRA) in the signal, is determined based at least in part on a second portion of the signal within a second amplitude range; the second amplitude range does not overlap with the first amplitude range. An MRA error is determined by removing the offset error from the signal error and the MRA error is removed from the signal. | 04-28-2011 |
| 20110080939 | BASELINE WANDER COMPENSATION FOR PERPENDICULAR RECORDING - A tail estimate signal which includes noise associated with baseline wander is generated. The tail estimate signal is generated by processing an input signal using a detector to obtain one or more decisions. Using the one or more decisions, the tail estimate signal is generated. The tail estimate signal is removed from the input signal. | 04-07-2011 |
| 20110078543 | PARALLEL INVERSIONLESS ERROR AND ERASURE PROCESSING - A complementary error evaluator polynomial is generated by obtaining a syndrome polynomial and one or more erasure locations. The syndrome polynomial and the erasure locations are associated with Reed-Solomon encoded information. A complementary error evaluator polynomial and an error locator polynomial are simultaneously generated using the syndrome polynomial and the erasure locations where the complementary error evaluator polynomial is a complement of the error evaluator polynomial. | 03-31-2011 |
| 20110075779 | PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS - A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop. | 03-31-2011 |
| 20110075569 | OBTAINING PARAMETERS FOR MINIMIZING AN ERROR EVENT PROBABILITY - A set of one or more receiver parameters is adjusted. It is determined whether to adjust the set of receiver parameters. In the event it is determined to adjust the set of receiver parameters, a new set of values is generated for the set of receiver parameters using a cost function (where the cost function does not assume a noise signal in a receive signal to have a particular statistical distribution) and the set of receiver parameters is changed to have the new set of values. | 03-31-2011 |
