KAWASAKI MICROELECTRONICS, INC. Patent applications |
Patent application number | Title | Published |
20130222067 | PHASE-LOCKED LOOP - A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal. | 08-29-2013 |
20130207711 | CALIBRATION CIRCUIT - A first constant voltage is supplied to a variable capacitance in a switched capacitor, and the variable capacitance is effectively charged to the first constant voltage in each cycle of a sampling clock. A current generated by charging the calibration resistance is averaged, and a resultant current is compared against a current generated by applying a second constant voltage to a resistance. The capacitance value of the variable capacitance is adjusted in accordance with a result of the comparison. Thus the variable capacitance is calibrated so as to have a target value. | 08-15-2013 |
20130207706 | PHASE INTERPOLATOR AND METHOD OF PHASE INTERPOLATION WITH REDUCED PHASE ERROR - An exemplary phase interpolator includes a first to a fourth differential pair. Each of the differential pairs includes a first and a second transistor and a stabilizing capacitor connected between a source coupled node and a reference voltage. The phase interpolator also includes a plurality of current sources and a group of switches to switch connections between the source coupled nodes of the differential pairs and the current sources so that (i) a first operating current is supplied to a first selected one of the first and second differential pairs and (ii) a second operating current is supplied to a second selected one of the third and fourth differential pairs. Drains of the first transistors in the differential pairs are commonly connected and drains of the second transistors in the differential pairs are commonly connected to form a first and a second output node so that a differential output signal is output. | 08-15-2013 |
20130147548 | LINEAR AMPLIFIER THAT PERFORM LEVEL SHIFT AND METHOD OF LEVEL SHIFTING - A linear amplifier that comprises a signal input terminal that receives an input signal having a first common mode voltage, a voltage amplifier having a non-inverting input terminal that receives a second common mode voltage, a first and a second input resistance connected in series from the signal input terminal to the inverting input terminal of the voltage amplifier, a feedback resistance connected between the inverting input terminal and the output terminal of the voltage amplifier, and a constant current source. The constant current source supplies a constant current to a middle node between the first and the second input resistances. The constant current generates a voltage drop, which is equal to a difference between the first and the second common mode voltages, across the first input resistance. Accordingly, the common mode voltage of the output signal is directly determined by the second common mode voltage. | 06-13-2013 |
20120317464 | RECEIVING APPARATUS AND METHOD THAT DETECT RECEPTION OF SERIAL DATA HAVING A PLURALITY OF BLOCKS - Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N12-13-2012 | |
20120262467 | IMAGE PROCESSING APPARATUS THAT ENABLES TO REDUCE MEMORY CAPACITY AND MEMORY BANDWIDTH - An image processing apparatus includes a memory control circuit that stores pixel data in a frame memory, an image processing circuit that processes the pixel data stored in the frame memory, and an output circuit that outputs processed pixel data. The memory control circuit divides the pixel data into upper bit portions and lower bit portions, and a lower bit processing circuit stores the lower bit portions in the frame memory by one of (i) dividing lower bit portion of each of the pixel data into n unit portions and storing corresponding one of n unit portions in the frame memory during each of n successive frame periods, and (ii) dividing pixels constituting each of the frames into n groups and storing the lower bit portions of the pixel data of pixels in corresponding one of n groups in the frame memory during each of n successive frame periods. | 10-18-2012 |
20120262205 | Circuit and Method for Current-Mode Output Driver With Pre-Emphasis - An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines. | 10-18-2012 |
20120249188 | DIFFERENTIAL OUTPUT BUFFER HAVING MIXING AND OUTPUT STAGES - An exemplary differential output buffer includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal to generate a mixed differential data signal. The output stage includes a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled. Gates of the transistors in the first and second output stage differential pairs are supplied with the differential data signal and the mixed differential data signal, respectively. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes to output an emphasized differential data signal. The mixing stage includes a mixing ratio setting circuit that sets the mixing ratio to one of 1:0, 1:1, and 0:1. | 10-04-2012 |
20120007755 | PARALLEL TO SERIAL CONVERSION APPARATUS AND METHOD OF CONVERTING PARALLEL DATA HAVING DIFFERENT WIDTHS - Various exemplary embodiments of this disclosure provide parallel to serial conversion apparatuses that includes a bit-swapping circuit that generates bit-swapped parallel data by swapping bits of input parallel data, and a parallel to serial conversion circuit that acquires M1 and M2 bits of the bit-swapped parallel data in a first and a second mode, respectively. The parallel to serial conversion circuit generates serial data by arranging the acquired bits of the bit-swapped parallel data in a first specified order in the first mode and in a second specified order in the second mode The bit-swapping circuit swaps the bits of the input parallel data such that the parallel to serial conversion circuit acquires 1st to M1-th and 1st to M2-th bits of the input parallel data in the first and second modes, respectively, and arranges the acquired bits of the input parallel data in the same order. | 01-12-2012 |
20110299397 | COMMUNICATION CONTROL APPARATUS AND SHAPING APPARATUS HAVING TOKEN BUCKET - Various exemplary shaping apparatuses for shaping packets stored in queues are provided. The shaping apparatus includes a token bucket that accumulates tokens with a predetermined rate. When a number of tokens accumulated in the token bucket is equal to or larger than a reference number corresponding to a maximum packet length that the queues may store, the shaping apparatus allows one of the packets stored in the queues to transmit and subtracts a number of tokens corresponding to a length of the packet allowed to be transmitted. Various exemplary communication control apparatuses that incorporate the shaping apparatuses are also provided. | 12-08-2011 |
20110255778 | IMAGE PROCESSING APPARATUS AND METHOD OF PROCESSING COLOR IMAGE DATA THAT PERFORM OVERDRIVE - Image processing apparatuses and methods of processing color image data that perform overdrive are provided. The apparatuses include a restoration block that restores R-, G-, and B-element values of respective pixels of previous one of successive frames based on Y-element values of the respective pixels of the previous one of the successive frames and the color image data of a current one of the successive frames. The apparatus further includes a correction block that compares the R-, G-, and B-element values of the respective pixels of the previous one of the successive frames that the restoration block restored and R-, G-, and B-element values of corresponding pixels of the current one of the successive frames and generates the corrected color image data. | 10-20-2011 |
20110234439 | TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERSION CIRCUIT HAVING POLYPHASE CORRECTION FILTER - Time-interleaved analog-to-digital (AD) conversion circuit, which includes first and second AD converters that generate first and second digital signal sequences by converting an analog input signal into first and second digital signals with a first frequency at first and second timings mutually different with each other is disclosed. The AD conversion circuit further includes a FIFO that receives the first and second digital signal sequences, and a correction filter including first and second portions that are supplied with a common clock signal. The correction filter generates a first corrected digital signal sequence by adding the first synchronized digital signal sequence and the second synchronized digital signal sequence passed through the first portion of the correction filter, and a second corrected digital signal sequence by passing the second synchronized digital signal sequence through the second portion of the correction filter. | 09-29-2011 |
20110231693 | NUMERICALLY CONTROLLED OSCILLATOR AND OSCILLATION METHOD FOR GENERATING FUNCTION VALUES USING RECURRENCE EQUATION - Numerically controlled oscillators and oscillation methods for generating function values in respective clock cycles by using a recurrence equation are provided. The oscillation circuit generates, in each of the clock cycles, a current one of the function values by multiplying, using a multiplier having a latency of k clock cycles, a first one of the function values generated in a first one of the clock cycles that is j cycles before a current one of the clock cycles by a coefficient and adding an output of the multiplier and at least one of the function values generated in previous ones of the clock cycles that are 1 to i−1 cycles before the current one of the clock cycles excluding the first one of the clock cycles, where 2 | 09-22-2011 |
20110018887 | APPARATUS AND METHOD FOR CONTROLLING DISPLAY DEVICES - An exemplary apparatus for controlling display devices writes pixel data in a buffer in synchronous with an input clock signal. A differential value that represents a change of timing difference between input and output sides is calculated in each of a plurality of frames, and a timing correction based on the differential value calculated during the previous frame is performed within the vertical blanking period. Thereafter, the pixel data is read and output from the buffer to the display device in synchronous with an output clock signal. | 01-27-2011 |
20110001531 | Method and apparatus for receiving burst data without using external detection signal - Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data. | 01-06-2011 |
20110001530 | METHOD AND APPARATUS FOR RECEIVING BURST DATA WITHOUT USING EXTERNAL DETECTION SIGNAL - Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data. | 01-06-2011 |
20100271739 | Semiconductor integrated circuit having protection circuit capable of protecting against ESD and EOS - A semiconductor integrated circuit has an internal circuit having an input terminal connected to a connection terminal, a protection circuit that discharges an over-voltage supplied to the connection terminal to a power line. The protection circuit includes a first discharge circuit connected to the connection terminal, a second discharge circuit connected to the connection terminal and discharges the over-voltage to the power line, and an over-voltage detect circuit that detects a discharge current flowing through the second discharge circuit and generates an over-voltage detect signal when the discharge current is detected. The first discharge circuit is disabled to discharge the over-voltage when the over-voltage detect signal is supplied. | 10-28-2010 |
20100246699 | Communication system, data transmitter, and data receiver capable of detecting incorrect receipt of data - A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N≠M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel dada stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received. | 09-30-2010 |
20090287974 | Method of generating test condition for detecting delay faults in semiconductor integrated circuit and apparatus for generating the same - Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop. | 11-19-2009 |
20090231048 | BIAS CIRCUIT TO STABILIZE OSCILLATION IN RING OSCILLATOR, OSCILLATOR, AND METHOD TO STABILIZE OSCILLATION IN RING OSCILLATOR - Bias circuits to stabilize oscillation in ring oscillators, oscillators, and methods to stabilize oscillation in ring oscillators are provided. The ring oscillator includes a plurality of differential delay cells, each including a pair of input transistors, a pair of voltage-controlled resistors, and a common current source. The bias circuit includes a replica arm that includes a replica of one of the voltage-controlled resistors, and a resistor arm that includes a fixed resistor. The bias circuit supplies bias voltages to the differential delay cells such that ratio of voltage swing to bias current of the delay cell is kept constant by referring the ratio to the fixed resistor. | 09-17-2009 |
20090184971 | Method of controlling frame memory, memory control circuit, and image processing apparatus including the memory control circuit - Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened. | 07-23-2009 |
20090160496 | Output driver circuit - In an output driver circuit, a replica circuit includes seventh and eighth transistors corresponding to first and second transistors, respectively, ninth and tenth transistors corresponding to third or fifth, and fourth or sixth transistors in a driver circuit, respectively, and a resistor corresponding to a termination resistor. A reference voltage and a voltage of a node between the ninth transistor and the resistor are input to an operational amplifier, and an output signal of the operational amplifier is input to gates of the first and seventh transistors. | 06-25-2009 |
20090109784 | Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same - An access area is set within an address space of a dynamic random access memory by arranging two or more complete columns of blocks, in which blocks of memory cells are arranged within an entirety of a specified range of row addresses, along a direction of column addresses. Each of the blocks includes memory cells positioned at a same row address and a specified number of consecutive column addresses. The total number of blocks arranged in the access area is just capable of storing the number of words of the data to be stored. The two or more complete columns of blocks are successively accessed by successively accessing the blocks arranged in each of the columns of blocks. Thereby, a refresh operation of the dynamic random access memory is made unnecessary. | 04-30-2009 |
20090103334 | Switching-type power-supply unit and a method of switching in power-supply unit - A switching-type power-supply which enables the switching with little power loss and a method of switching the switching-type power-supply are provided. The switching-type power-supply unit includes a transformer with primary, secondary, winding and control windings, a switch which switches supply of a primary current from a dotted terminal to a non-dotted terminal through the primary winding, a rectifying diode connected the secondary winding, a monitoring signal generation circuit with a diode and a resistor, the diode between GND and a dotted terminal of the control winding, the resistor between GND and a non-dotted terminal of the control winding, the monitoring signal generation circuit generating a monitoring signal at the dotted terminal of the control winding, and a control unit with a zero-point detector and a controller. The zero-point detector monitoring the monitoring signal and supplying a detection signal to the controller. The controller determining on-timing of the switch based on the detection signal supplied from the zero-point detector. | 04-23-2009 |
20090064078 | Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof - An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality of pattern layers. The dummy region includes a plurality of character dummies, which do not contribute to an operation of the semiconductor integrated circuit. The character dummies have a fixed shape and dimension, and arranged in a character pattern layer selected from the plurality of pattern layers with a fixed pitch. The dummy region further includes an identification sign formed by connecting selected ones of the character dummies chosen from the plurality of the character dummies. | 03-05-2009 |
20080315931 | Semiconductor integrated circuit having active and sleep modes and non-retention flip-flop that is initialized when switching from sleep mode to active mode - A semiconductor integrated circuit has an active mode and a sleep mode. The semiconductor integrated circuit is constructed by alternately connecting a plurality of combinational logic circuits and a plurality of flip-flops. The flip-flops include a retention flip-flop that is supplied with electric power and retains the data in the sleep mode, and a non-retention flip-flop that is not supplied with electric power during the sleep mode. The non-retention flip-flop includes an initializing circuit that initializes the non-retention flip-flop when the semiconductor integrated circuit is switched from the sleep mode to the active mode. | 12-25-2008 |
20080252657 | Color conversion circuit and method of color conversion using interpolation from conversion coefficients some of which are substituted - Exemplary embodiments of color conversion circuits and color conversion methods convert input color data into output color data. The input color data is positioned in a three-dimensional color space, which is divided into a plurality of unit cubes each having a fixed dimension. The input color data is converted by performing interpolations using conversion coefficients at vertexes of the unit cube within which the input color data is positioned. When the input color data is positioned on a gray axis of the color space, a substitution circuit substitutes some of the conversion coefficients such that the interpolation becomes a linear interpolation. As a result, it is assured that input color data positioned on the gray axis is converted to gray output color data. | 10-16-2008 |
20080246503 | Method of testing a semiconductor integrated circuit - A method of testing a semiconductor integrated circuit is disclosed. Specifically, a method of testing a semiconductor integrated circuit comprising a plurality of flip-flops is provided. The disclosed method includes connecting the plurality of flip-flops in series so that the plurality of flip-flops forms a scan-chain; inputting data to the scan-chain while supplying a clock signal to the plurality of flip-flops so that the data is set in the plurality of flip-flops; retaining the data in the plurality of flip-flops while inhibiting the clock signal for a predetermined period; restarting the clock signal to the plurality of flip-flops so that the data retained in the plurality of flip-flops is output from the scan-chain; and comparing the data output from the scan-chain and the data input to the scan-chain to test data retention of the plurality of flip-flops. | 10-09-2008 |
20080218222 | Circuit and method for current-mode output driver with pre-emphasis - An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines. | 09-11-2008 |
20080206452 | Quartz component for plasma processing apparatus and restoring method thereof - The main surface of a quartz component is divided by an offset into a first region having a larger height around an inner perimeter and a second region adjacent to the outer perimeter of the first region. Repeated restoration of a damaged component by forming a bulge on the first region and machining the bulge to make a flat surface while maintaining the offset enables long term use of the component. | 08-28-2008 |