| KABUSHI KAISHA TOSHIBA Patent applications |
| Patent application number | Title | Published |
|---|
| 20120001331 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects. | 01-05-2012 |
| 20110079723 | CONFIGURABLE COINCIDENCE PAIRING AND FILTERING SYSTEM AND METHOD FOR POSITRON EMISSION TOMOGRAPHY - A method of processing positron emission tomography (PET) information obtained from a PET detector having a plurality of detector regions, each detector region having at least one detector module and a corresponding regional collector, the method including the steps of receiving PET event information for a single PET event, the PET event information including energy information and crystal position information of the single PET event; receiving non-detector event information; generating an event list that includes (1) a PET event entry, the PET event entry including a fine time stamp, the energy information, and the crystal position information, and (2) a non-detector event entry that includes the received non-detector event information; and transmitting the generated event list to a computer for off-line processing. | 04-07-2011 |
| 20110051491 | FERROELECTRIC RANDOM ACCESS MEMORY AND MEMORY SYSTEM - Certain embodiments provide a ferroelectric random access memory comprising a first buffer, a second buffer, a third buffer, a first controlling unit, a second controlling unit, a memory cell array, a sense amplifier circuit, and a third controlling unit. The first buffer outputs a first signal changed from a first value to a second value based on notification of power-down. The second buffer stops supply of inner clock signal with the change of the first signal from the first value to the second value. The third buffer receives an address signal corresponding to data to be read or written. The first controlling unit receives a command signal. The second controlling unit generates a basic signal that has a third value when the command signal indicates a bank active command and has a fourth value when the command signal indicates a precharge command and the first signal has the second value. The sense amplifier circuit reads data via a pair of bit lines from the memory cell corresponding to the address signal. The third controlling unit controls write back to the memory cell from which the data are read so as to be performed after an elapse of a predetermined time from the time the basic signal has the third value and when the basic signal has the fourth value. | 03-03-2011 |
| 20100236619 | LIGHT TRANSMISSION TYPE SOLAR CELL AND METHOD FOR PRODUCING THE SAME - The present invention provides a light transmission type solar cell excellent in both power generation efficiency and light transparency, and also provides a method for producing that solar cell. The solar cell of the present invention comprises a photoelectric conversion layer, a light-incident side electrode layer, and a counter electrode layer. The incident side electrode layer is provided with plural openings bored through the layer, and has a thickness of 10 nm to 200 nm. Each of the openings occupies an area of 80 nm | 09-23-2010 |
| 20100186836 | COUPLER | 07-29-2010 |
| 20100109990 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a pair of substrates, a plurality of pixels arranged in a matrix and a static memory formed on the substrates. A bit signal corresponding to an image data is written and held in a static memory in the pixel. The polarity of the input bit signal is controlled. A liquid crystal voltage supplied to a liquid crystal layer arranged between the pair of substrates is generated by the bit signal. The polarity of the bit signal is controlled to alternate the liquid crystal voltage, and a transmittance of the liquid crystal layer is changed by supplying the alternated liquid crystal voltage. | 05-06-2010 |
| 20100002496 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes: an inverter pair of a cross-coupled first and second inverters; a first transfer transistor including a front gate and a back gate connected to a first node to which an output terminal of the first inverter and an input terminal of the second inverter are connected; a second transfer transistor including a front gate and a back gate connected to a second node to which an output terminal of the second inverter and an input terminal of the first inverter are connected; a driver transistor whose gate is connected to the second node; and a read transistor including a front gate, a back gate connected to the second node, and a current path whose one end is connected to one end of a current path of the driver transistor. | 01-07-2010 |
| 20090250425 | Screw-Type Cap and Safety Cap - There are provided a screw-type cap which can secure necessary fastening torque (opening torque) even in a case of a container having a plug having a foremost end portion of a small diameter and also a safety cap which cannot be opened by only rotation and therefore has a child resistance effect. A safety cap | 10-08-2009 |
| 20090208821 | BATTERY SYSTEM - In a battery system, battery modules ( | 08-20-2009 |
| 20090196537 | POUCH WITH SPOUT - A pouch with a spout includes a pouch body | 08-06-2009 |
| 20090154237 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and a second register group configured to store the adjusting data read from the adjusting data storage area. | 06-18-2009 |
| 20080287135 | COMMUNICATION SCHEME WITH ARBITRATION MECHANISM FOR CASES OF ADDRESS INITIALIZATION AND SERVER SETTING - The other communication devices are prohibited to transmit the address initialization request for a prescribed period of time since one communication device transmitted the address initialization request for an address managed by a control protocol, so that the conflict of the initialization requests for the same address will not occur and the problem of assigning the address in overlap to the communication devices will not arise. Also, the other communication devices are prohibited to transmit the address server detection request packet for a prescribed period of time since one communication device transmitted the address server detection request packet, so that the conflict on the network by a plurality of address server detection requests will not occur, and it is possible to determine the MAC address server uniquely. | 11-20-2008 |
| 20080211020 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a lateral direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer; and a sixth first-conductivity-type semiconductor layer provided on the major surface of the first first-conductivity-type semiconductor layer in a termination section outside the periodic array structure. The second first-conductivity-type semiconductor layer has an impurity concentration varying in the lateral direction and the impurity concentration is minimized at a center in the lateral direction. An impurity concentration in the sixth first-conductivity-type semiconductor layer is not higher than the impurity concentration at the center of the second first-conductivity-type semiconductor layer. | 09-04-2008 |
