| KABUSHHIKI KAISHA TOSHIBA Patent applications |
| Patent application number | Title | Published |
|---|
| 20110096324 | RETICLE DEFECT INSPECTION APPARATUS AND RETICLE DEFECT INSPECTION METHOD - A reticle defect inspection apparatus that can carry out a defect inspection with high detection sensitivity are provided. The apparatus includes an optical system of transmitted illumination for irradiating one surface of a sample with a first inspection light, an optical system of reflected illumination for irradiating another surface of the sample with a second inspection light, and a detecting optical system that can simultaneously detect a transmitted light obtained by the first inspection light being passed through the sample and a reflected light obtained by the second inspection light being reflected by the sample. And the optical system of transmitted illumination includes a focusing lens driving mechanism for correcting a focal point shift of the transmitted light resulting from thickness of the sample. | 04-28-2011 |
| 20080311486 | PHOTOMASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a reflective layer formed on a substrate and an absorber pattern is formed on the layer. A reflection correction coefficient map is generated by dividing a mask region, where the absorber pattern is formed, into a plurality of subregions, and determining a reflection correction coefficient for each subregion. The reflection correction value of each subregion is calculated based on the dimensional difference indicated in the pattern dimensional map and the reflection correction coefficient of each subregion. A reflection coefficient of each reflective layer region corresponding to each subregion is changed based on the reflection correction value. | 12-18-2008 |
| 20080309607 | LIQUID CRYSTAL DISPLAY DRIVER AND LIQUID CRYSTAL DISPLAY DEVICE - A driver includes a delay-time adjuster. A data clock is inputted to the delay-time adjuster through a data-clock signal line. While receiving input of a load signal that is a sampling signal of a second register, the delay-time adjuster adjusts a delay time of the data clock so that a phase difference between the data clock and gradation data inputted into a first register through a gradation-data signal line can be set to a predetermined value. After the completion of the input of the load signal, the delay-time adjuster holds a data clock for the adjusted delay time, and outputs the delayed data clock as a shift clock for a shift register. | 12-18-2008 |
