Japan Radio Co., Ltd. Patent applications |
Patent application number | Title | Published |
20140168002 | RADAR RECEIVER - The object of the present invention is to provide a radar receiver that can steadily and reliably detect the target in the close zone without largely complicating the construction compared to the conventional radar apparatuses. The radar receiver according to the present invention comprises a receiving unit | 06-19-2014 |
20110188626 | Damage Evaluation Apparatus, and Damage Evaluation Method - Provided is a damage evaluation apparatus capable of evaluating the damage of an asphalt mixture or the like non-destructively for a short time and in a precise manner. This apparatus turns a sample (S) and irradiates it at every predetermined angle with an X-ray so that it detects the transmitted X-ray with an X-ray detector ( | 08-04-2011 |
20100251050 | TIME-DIVISION DUPLEX TRANSMIT-RECEIVE APPARATUS - There is provided a time-division duplex transmit-receive apparatus in which the respective amplitude and phase characteristics of N sets of transmitting unit-receiving unit pair connected with N antenna elements are corrected all together and at the same time. At the time of reception, the reference signal from reference signal generator is branched into N reference signals. The branched reference signal is applied to the reception system through the transmit-receive switching switch. The reception-side error detector detects the error between the output signal of the reception-side amplitude-phase correction circuit and the reference signal to control the reception-side amplitude-phase correction circuit so that the error becomes zero. At the time of transmission, a part of transmitting signal is applied to the reception system through the antenna path. The transmission-side error detector detects the error between the output signal of the reception-side amplitude-phase correction circuit and the transmitting signal to control the transmission-side error detector so that the error becomes zero. | 09-30-2010 |
20100109782 | FET BIAS CIRCUIT - A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class. | 05-06-2010 |
20100074245 | MOBILE BODY-MOUNTED COMMUNICATION APPARATUS AND ADDRESS MANAGEMENT APPARATUS - A mobile body-mounted communication device mounted in a mobile body such as a vehicle and making difficult the long-time tracking of the moving path of the mobile body. The mobile body-mounted communication device mounted in a mobile body and used for transmitting/receiving packet information is characterized by comprising a borrowing address acquiring section for acquiring lending addresses as borrowed addresses from an address management device managing lending addresses, a borrowing time information acquiring section for acquiring information representing predetermined times during which the borrowing addresses can be used from the address management device, and a transmitting section for transmitting packet information including information on a borrowing address out of the borrowing addresses and the mobile body during the predetermined borrowing times determined for the borrowing addresses. | 03-25-2010 |
20090147441 | Closed-Type Capacitor - A closed type capacitor ( | 06-11-2009 |
20090121952 | Slot Antenna - Impedance matching is achieved in a waveguide of a slot antenna, which is provided with an input waveguide that is fed power via an aperture plane; a stairway structure is provided in the input waveguide; the structure creates a step going upward toward a surface provided with a slot; the step difference and height of the step going upward are adjusted so that the impedance at a plane above the step and the impedance at the aperture plane match. | 05-14-2009 |
20090115526 | FET BIAS CIRCUIT - A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class. | 05-07-2009 |
20090052116 | ELECTRIC DOUBLE-LAYER CAPACITOR - A plurality of capacitor cells ( | 02-26-2009 |