IPGoal Microelectronics (Sichuan) Co., Ltd. Patent applications |
Patent application number | Title | Published |
20150117590 | Shift frequency demultiplier - A shift frequency demultiplier includes: an inverter; N-2 registers; and N-4 OR gates; wherein an output terminal of the No. N-2 register is connected to an input terminal of the inverter, an output terminal of the inverter is connected to an input terminal of the No. 1 register and input terminals of the OR gates; the output terminal of the No. 1 register is connected to another input terminal of the No. 1 OR gate, the output terminal of the No. N-4 register is connected to another input terminal of the No. N-4 OR gate; an output terminal of the No. 1 OR gate is connected to the input terminal of the No. 2 register, an output terminal of the No. N-4 OR gate is connected to the input terminal of the No. N-3 register whose the output terminal is connected to an input terminal of the No. N-2 register. | 04-30-2015 |
20150082073 | Circuit and method for producing USB host working clock - A circuit for producing USB host working clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a USB host interface, and a frequency division controller. According to the frequency multiplier providing clock, the USB host interface configures with USB peripherals for responding. The frequency division controller is connected to the USB host interface and the controllable frequency divider. The USB host interface transmits a response result that the USB host interface configures with USB peripherals for responding to the frequency division controller. According to the USB host interface feeding back the response result, the frequency division controller regulates a frequency dividing ratio of the controllable frequency divider in set scope of the frequency dividing ratio. After regulating the frequency dividing ratio of the controllable frequency divider, the frequency division controller controls the controllable frequency divider that is processed with frequency division in fixed frequency dividing ratio. | 03-19-2015 |
20150030117 | Shift frequency divider circuit - A shift frequency divider circuit includes: an inverter; N−1 registers; and N−2 logic gates; wherein each reset terminal of the register is connected to a system reset signal terminal; an output terminal of the inverter is respectively connected to an input terminal of the No. 1 register and input terminals of all the logic gates; all the logic gates are respectively connected between output terminals and input terminals of the No. 1 register to the No. N−1 register, and the output terminal of the No. 1 register is connected to another input terminal of the No. 1 logic gate, an output terminal of the No. 1 logic gate is connected to the input terminal of the No. 2 register; an output terminal of the No. N−2 logic gate is connected to the input terminal of the No. N−1 register. | 01-29-2015 |
20150030114 | Frequency locking system - A frequency locking system for locking a clock frequency in a CDR circuit without crystal oscillator is provided. Reference data information is inputted into a first low-pass filter; the first low-pass filter is connected to a first swing detector; the first swing detector is connected to a non-inverting terminal of a comparator; an output terminal of the comparator is connected to a charge pump; the charge pump is connected to a first terminal of a capacitor; the capacitor is grounded. The capacitor is also connected to a voltage-controlled oscillator; the voltage-controlled oscillator is connected to a code pattern conversion generator; the code pattern conversion generator is connected to of a second low-pass filter; the second low-pass filter is connected to an input terminal of a second swing detector; an output terminal of the second swing detector is connected to an inverting terminal of the comparator. | 01-29-2015 |
20140176354 | Sampling circuit for ADC - A sampling circuit for ADC includes an external input terminal, a sampling circuit and an auxiliary circuit which are connected with the external input terminal, a clock circuit and an external output terminal which are connected with the sampling circuit, and a clock feedthrough circuit connected with the auxiliary circuit, wherein the clock feedthrough circuit is respectively connected with the clock circuit and the external output terminal. The sampling circuit for ADC of the present invention decreases the impact of clock feedthrough on signal sampling, improves linearity of sampling FET, reduces harmonic distortion of the sampling circuit and improves sampling speed thereof, and improves sampling accuracy of the sampling circuit for ADC. | 06-26-2014 |
20140176241 | High-frequency bandwidth amplifying circuit - A high-frequency bandwidth amplifier circuit comprises: a push-pull amplifier, a feedback resistor, a first active inductor, and a second active inductor. An input terminal of the push-pull amplifier is connected with an external input terminal. An output terminal of the push-pull amplifier is connected with an output port. A first end of the feedback resistor is connected with the external input terminal A second end of the feedback resistor is connected with the output port. A first end of the first active inductor is connected with an external power source. A second end of the first active inductor is connected with the output port. A first end of the second active inductor is grounded. A second end of the second active inductor is connected with the output port. | 06-26-2014 |
20140176240 | High-frequency bandwidth amplifying circuit - A high-frequency bandwidth amplifying circuit includes a forward channel and a backward channel. An input terminal of the forward channel and an external forward input terminal are connected; an output terminal of the forward channel and a forward output port are connected. An input terminal of the backward channel and an external backward input terminal are connected; an output terminal of the backward channel and a backward output port are connected. The high-frequency bandwidth amplifying circuit further includes a feedback network. The forward channel includes a first operational amplifier and a second operational amplifier. An input terminal of the first operational amplifier is connected to the external forward input terminal; an output terminal of the first operational amplifier is connected to an input terminal of the second operational amplifier; and an output terminal of the second operational amplifier is connected to the forward output port. | 06-26-2014 |
20140176204 | Phase locked loop system and working method thereof - A PLL system includes: an input end; an output end; a first PFD; a first CHP connected to the first PFD; a first LPF connected to the first CHP; a first VCO connected to the first CHP and the first LPF; a second PFD connected to the first VCO; a second CHP connected to the second PFD; a second LPF connected to the second CHP; a second VCO connected to the second CHP and the second LPF; a first DIV connected to the first PFD and the second VCO; and a second DIV connected to the second PFD and the second VCO. A working method of the PLL system is also provided, which can restrain input noise as well as phase noise of the second VOC in such a manner that noise of the PLL system is well restrained. | 06-26-2014 |
20140176113 | Circuit for outputting reference voltage - A circuit for outputting reference voltage includes: a detecting unit, a feedback unit and an output unit which are respectively connected with an external power source, wherein a plurality of field effect transistors (FETs) are provided in the detecting unit, wherein the detecting unit is for detecting foundry corners of the FETs therein, the feedback unit is for feeding back and comparing a detecting result of the detecting unit, and outputting information after feeding back and comparing, and the output unit is for outputting reference voltage corresponding to the foundry corners of the FETs to an external output terminal. The reference voltage outputted by the circuit for outputting reference voltage of the present invention is capable of varying with foundry corners of the FETs, and achieves compensating for foundry corners of the FETs. | 06-26-2014 |
20140143584 | Circuit for generating peripheral clock for USB and method therefor - A circuit for generating a peripheral clock for USB, provided on a USB major structure, comprises an internal oscillator, a receiver, a transmitter, a clock counter, and a clock processor; wherein the internal oscillator generates a clock having a settled frequency; the receiver is connected with the internal oscillator and a system unit, and receives a packet transmitted by the system unit; the transmitter is connected with the internal oscillator and the system unit, and transmits a packet of the USB major structure to the system unit; the clock counter is connected with the receiver and the internal oscillator, and counts a length of the packet received; and the clock processor is connected with the clock counter, the internal oscillator, and the transmitter, and controls and adjusts a length of the packet transmitted by the transmitter according to the length of the packet counted by the clock counter. | 05-22-2014 |
20140143583 | Circuit for generating USB peripheral clock and method therefor - A circuit for generating USB peripheral clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a receiving counter and a frequency division controller, wherein the internal oscillator generates a clock having a fixed frequency; the controllable frequency divider processes frequency division on the clock generated by the internal oscillator; the frequency multiplier processes frequency multiplication on the clock after frequency division and transmits the clock after frequency multiplication to the USB main structure; the receiving counter receives an SOF packet which is transmitted by a host according to the clock outputted by the frequency multiplier, and counts intervals of receiving the SOF packet; and the frequency division controller compares the difference between the counting result of the receiving counter and a standard interval, controls and regulates frequency division parameters of the controllable frequency divider according to a comparing result thereof. | 05-22-2014 |
20140133532 | Serial data transmission system and method - A serial data transmission system includes a sending terminal for sending data, a receiving terminal for receiving the data sent by the sending terminal, a first connecting capacitor connected between the sending terminal and the receiving terminal, and a second connected capacitor connected between the sending terminal and the receiving terminal. The sending terminal includes a sending terminal driving unit, and an amplitude detecting unit connected to the sending terminal driving unit. The sending terminal driving unit outputs a pair of differential signals according to signals of the received data. The amplitude detecting unit detects changes in amplitudes of the differential signals outputted by the sending terminal driving unit, and outputs an indicating signal for indicating whether the sending terminal is properly connected to the receiving terminal. A serial data transmission method is further provided. | 05-15-2014 |
20140126747 | Power amplifying circuit and system - A power amplifying circuit includes: a signal input terminal, a common-mode voltage input terminal, a power tube control unit, a feedback loop, a driving unit, a first switching element, a second switching element, a low-pass filter, a speaker, a source voltage terminal, and a ground terminal, wherein the power tube control unit includes: an operational amplifier, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a eighth switch, a ninth switch, a third switching element connected with the third switch and the fourth switch, a fourth switching element connected with the fifth switch and the sixth switch, and a comparator connected with the third switching element and the fourth switching element. The present invention is able to realize functions of CLASS AB amplifier and CLASS D amplifier. | 05-08-2014 |
20140126673 | Differential signal detecting device - A differential signal detecting device includes a secondary amplifier; a front-end receiver and a final amplifier which are respectively connected to the secondary amplifier; and a signal outputter which is connected to the final amplifier. The front-end receiver receives two externally inputted channels of differential signals and an externally inputted reference threshold voltage, differentiates and transduces the two channels of differential signals. The secondary amplifier receives and amplifies the signals which are outputted by the front-end receiver, and outputs the signals amplified again. The final amplifier differentiates and amplifies the signals outputted by the secondary amplifier and outputs the two channels of differentiated signals. The signal outputter receives the two channels of differentiated signals which are outputted by the final amplifier and processes the two channels of differentiated signals with a logical conjunction before outputting. | 05-08-2014 |
20140125447 | Resistance calibrating circuit - A resistance calibrating circuit includes an external power source; a reference unit, a current calibrating circuit and a voltage calibrating unit which are respectively connected to the external power source; an external reference voltage which is respectively connected to the reference unit and the voltage calibrating unit; an to-be-calibrated voltage-controlled resistor which is respectively connected to the current calibrating unit and the voltage calibrating unit, wherein the current calibrating unit is further connected to the reference unit. The resistance calibrating circuit is capable of automatically adjusting a resistance of the to-be-calibrated voltage-controlled resistor highly precisely and highly efficiently. | 05-08-2014 |
20140089372 | Divider Logic Circuit and Implement Method Therefor - A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, includes a first constant value input terminal, a first adder, a second constant value input terminal, a base number input terminal, at least one integer power device, at least one right shift register, a second adder, and a multiplier; wherein the integer power device determines a first constant value that the base number is N | 03-27-2014 |
20140086432 | POP noise suppression circuit and system - A POP noise suppression circuit includes a power source terminal, a clock signal input terminal, a charge unit, a discharge unit, a common-mode voltage judging and switching control unit, a charge and discharge capacitor, and a ground terminal. The charge unit includes a first clock generation circuit for generating a first pair of non-overlapped clock signal, and a first equivalent resistor. The discharge unit includes a second clock generation circuit for generating a second pair of non overlapped clock signals, and a second equivalent resistor. The charge unit generates a charge voltage changing slowly to the charge and discharge capacitor. The discharge unit generates a discharge voltage changing slowly to the charge and discharge capacitor. A POP noise suppression system is further provided. | 03-27-2014 |
20140028359 | Frequency multiplier circuit and system - A frequency multiplier circuit includes a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to the first signal input terminal, the second signal input terminal, the power source terminal and the ground terminal, a reference circuit which is connected to the power source terminal and the ground terminal, and a frequency synthesis circuit which is connected to the main control circuit, the reference circuit, the output terminal, the power source terminal and the ground terminal. | 01-30-2014 |
20140028353 | High speed signal detecting circuit and system - A high speed signal detecting circuit includes an input terminal, a reference terminal, an output terminal, a power source terminal, a ground terminal, a front-end receiver which is connected to the input terminal, the reference terminal and the ground terminal, a secondary amplifier which is connected to the front-end receiver and the ground terminal, a final amplifier which is connected to the secondary receiver, the output terminal, the power source terminal and the ground terminal, and a biasing circuit which is connected to the front-end receiver, the secondary amplifier, the final amplifier, the power source terminal and the ground terminal. A high speed signal detecting method is also provided to precisely detect high speed signal and change a detection threshold value of the high speed signals by changing a voltage value of the reference terminal and thus has a great flexibility. | 01-30-2014 |
20130265019 | Current source circuit with temperature compensation - A current source circuit with temperature compensation includes a power supply terminal, a reference current source unit connected to the power supply terminal, a feedback control unit connected to the power supply terminal and the reference current source unit, a current source generating unit connected to the feedback control unit and a ground terminal connected to the current source generating unit. The reference current source unit is a current source connected to the power supply terminal. The feedback control unit includes a first switching element, connected to the current source, and an inverting amplifier, connected between the current source and the first switching element. The current source generating unit includes a second switching element, connected to the first switching element, the current source and the inverting amplifier, and a first resistor, connected to the first and the second switching elements and the ground terminal. | 10-10-2013 |
20130169334 | INTERPOLATION CIRCUIT AND INTERPOLATION SYSTEM - An interpolation circuit, includes a bias generating module, a load module consisting of a current source sub-module and a load resistance sub-module, first and second clock control modules, and an output module. The first clock control module includes a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module. The bias generating module includes first, second and third FETs, and a bias current terminal. The current source sub-module includes fourth and fifth FETs. The load resistance sub-module includes first and second resistors. The first input sub-module includes sixth and seventh FETs. The first source terminal negative feedback sub-module includes a third resistor and a first capacitor. The first multiplex switch sub-module includes first and second groups of switches. The first multiplex current sink sub-module includes first and second groups of FETs. An interpolation system is further provided. | 07-04-2013 |
20130154753 | Oscillation circuit and oscillation system - An oscillation circuit includes a threshold voltage extraction module, a positive temperature coefficient voltage generation module, an addition module, a common-source amplifier module, a charge and discharge module, and a clock output terminal. The common-source amplifier module includes a first field effect transistor (FET) and a second FET. The addition module includes a first operational amplifier, a second operational amplifier, a third FET, a fourth FET, a fifth FET, a sixth FET, a first resistor, a second resistor, and a third resistor. The charge and discharge module includes a seventh FET, an eighth FET, a charge and discharge FET, a first switch, a second switch, a first comparator, a second comparator, a first nor gate and a second nor gate. An oscillation system is further provided. The oscillation circuit and the oscillation system of the present invention have simple structures and are easy to implement. | 06-20-2013 |
20130141076 | Spread Spectrum Clock Signal Detection System and Method - A spread spectrum clock signal detection system includes: a spread spectrum clock signal input terminal; a reference clock signal input terminal; a frequency difference detection module connected with the spread spectrum clock signal input terminal and the reference clock signal input terminal; a spread spectrum pulse detection module connected with the spread spectrum clock signal input terminal, the reference clock signal input terminal and the frequency difference detection module; a spread spectrum value calculating module connected with the spread spectrum pulse detection module; a spread spectrum value reference input terminal connected with the spread spectrum value calculating module; and an output module connected with the spread spectrum value calculating module, wherein the spread spectrum clock signal detection system judges whether the spread spectrum clock signal exists according to the information of the spread spectrum value with magnitude and direction. A spread spectrum clock signal detection method is also provided. | 06-06-2013 |
20130106392 | Reference current source circuit and system | 05-02-2013 |
20130099769 | Current source circuit with high order temperature compensation and current source system thereof - A current source circuit with high order temperature compensation, includes a reference voltage terminal, a first power module, a second power module, a control module, a current source output module and a bias current source module. The control module includes a first field-effect tube (FET), a second FET, and a third FET. The bias current source module includes a first bias current source and a second bias current source. The current source output module includes a fourth FET, a fifth FET, and an output terminal. The first power module includes a first comparator, a sixth FET, a first resistor and a second resistor. The second power module includes a second comparator, a seventh FET, a third resistor, and a fourth resistor. A current source system with high order temperature compensation is further provided. | 04-25-2013 |
20130077702 | Serial data transmission system and method - A serial data transmission system, includes a transmitting terminal for transmitting a data, a receiving terminal for receiving the data transmitted by the transmitting terminal, a first connecting capacitor connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit and an amplitude detection unit connected with the transmitting terminal driver unit, the transmitting terminal driver unit outputs a pair of differential signals, the amplitude detection unit detects an amplitude variation of the differential signals output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other. A serial data transmission method is further provided. | 03-28-2013 |
20130076329 | Equalization circuit and equalization system - An equalization circuit, includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit, a second regulating circuit, and a bias voltage generating circuit. The bias voltage generating circuit is connected with both the first regulating circuit and the second regulating circuit. The first regulating circuit includes a first field effect transistor (FET), a second FET, a third FET, a fourth FET, a first resistor connected with the first FET, a second resistor connected with the second FET, a third resistor connected with the third FET, a fourth resistor connected with the fourth FET, a fifth resistor connected with the third FET, a sixth resistor connected with the fourth FET, a first capacitor connected with the third FET, and a second capacitor connected with the fourth FET. An equalization system is further provided. | 03-28-2013 |
20120306555 | Duty cycle adjusting system - A duty cycle adjusting system includes a detection circuit, a first clock signal adjusting circuit connected with the detection circuit, and a second clock signal adjusting circuit connected with the detection circuit, wherein the detection circuit detects a duty cycle of a first output signal outputted by the first clock signal adjusting circuit and a duty cycle of a second output signal outputted by the second clock signal adjusting circuit, and outputs a first detection signal and a second detection signal, the first and second output signals are a pair of differential clock signals, the first and second detection signals are adapted for respectively adjusting rising edges of the pair of differential clock signals. No peripheral circuit is needed to provide the bias in the duty cycle adjusting system. The duty cycle adjusting system has the simple structure and can be independently applied to the clock path. | 12-06-2012 |