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INTRINSITY, INC.
| INTRINSITY, INC. Patent applications | ||
| Patent application number | Title | Published |
|---|---|---|
| 20110214097 | Method for Preparing Re-Architected Designs for Sequential Equivalence Checking - This disclosure describes a method illustrated in FIG. | 09-01-2011 |
| 20110214096 | Method For Piecewise Hierarchical Sequential Verification - This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled | 09-01-2011 |
| 20100045333 | GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN - This invention ( | 02-25-2010 |