Interuniversitair Microelektronica Centrum (IMEC) vzw Patent applications |
Patent application number | Title | Published |
20090301557 | METHOD FOR PRODUCING PHOTOVOLTAIC CELLS AND PHOTOVOLTAIC CELLS OBTAINED BY SUCH METHOD - A method for the production of a photovoltaic device, for instance a solar cell, is disclosed. In one aspect, the method comprises providing a substrate having a front main surface and a rear surface. The method further comprises depositing a dielectric layer on the rear surface, wherein the dielectric layer has a thickness larger than about 100 nm. The method further comprises depositing a passivation layer comprising hydrogenated SiN on top of the dielectric layer and forming back contacts through the dielectric layer and the passivation layer. In another aspect, corresponding photovoltaic devices, for instance solar cell devices, are also disclosed. | 12-10-2009 |
20090152526 | Method for manufacturing a memory element comprising a resistivity-switching NiO layer and devices obtained thereof - The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients. | 06-18-2009 |
20090141563 | Method for Operating a Non-Volatile Charge-Trapping Memory Device and Method for Determining Programming/Erase Conditions - A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state. | 06-04-2009 |
20090134469 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH DUAL FULLY SILICIDED GATE - A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method comprises providing a first metal layer over a first electrode in a first region, and at least a first work function tuning element. The method further comprises providing a second metal layer of a second metal in a second region at least over a second electrode. The method further comprises performing a first silicidation of the first electrode and a second silicidation of the second electrode simultaneously. | 05-28-2009 |
20080315125 | METHOD AND SYSTEM FOR MEASURING CONTAMINATION OF A LITHOGRAPHICAL ELEMENT - A method and system for measuring contamination of a lithographic element is disclosed. In one aspect, the method comprises providing a first lithographical element in a process chamber. The method further comprises providing a second lithographical element in the process chamber. The method further comprises covering part of the first lithographical element providing a reference region. The method further comprises providing a contaminant in the process chamber. The method further comprises redirecting an exposure beam via the test region of the first lithographical element towards the second lithographical element whereby at least one of the lithographical elements gets contaminated by the contaminant. The method further comprises measuring the level of contamination of the at least one contaminated lithographical element in the process chamber. | 12-25-2008 |
20080230856 | INTERMEDIATE PROBE STRUCTURES FOR ATOMIC FORCE MICROSCOPY - An intermediate probe structure for atomic force microscopy is disclosed. The probe structure comprises a semiconductor substrate with one or more moulds formed on a surface of one side of the substrate. The probe structure further comprises one or more probe configurations formed on the one side of the semiconductor substrate, wherein each probe configuration comprises a contact region and at least one set of a probe tip and a cantilever. The probe structure further comprises one or more holders attached to each of the contact regions, wherein the surface area of each contact region is smaller in size than the surface area of the holder which is attached to the contact region. | 09-25-2008 |
20080229273 | SYSTEMS AND METHODS FOR UV LITHOGRAPHY - A method of designing a lithographic mask for use in lithographic processing of a substrate is disclosed. The lithographic processing comprises irradiating mask features of a lithographic mask using a predetermined irradiation configuration. In one aspect, the method comprises obtaining an initial design for the lithographic mask comprising a plurality of initial design features having an initial position. The method further comprises applying at least one shift to at least one initial design feature and deriving there from an altered design so as to compensate for shadowing effects when irradiating the substrate using a lithographic mask corresponding to the altered design in the predetermined irradiation configuration. Also disclosed herein are a corresponding design, a method of setting up lithographic processing, a system for designing a lithographic mask, a lithographic mask, and a method of manufacturing it. | 09-18-2008 |
20080213689 | WATERMARK DEFECT REDUCTION BY RESIST OPTIMIZATION - A method is disclosed for lithographic processing. In one aspect, the method comprises obtaining a resist material with predetermined resist properties. The method further comprises using the resist material for providing a resist layer on the device to be lithographic processed. The method further comprises illuminating the resist layer according to a predetermined pattern to be obtained. The obtained resist material comprises a tuned photo-acid generator component and/or a tuned quencher component and/or a tuned acid mobility as to reduce watermark defects on the lithographic processed device. In another aspect, a corresponding resist material, a set of resist materials, use of such materials and a method for setting up a lithographic process are disclosed. | 09-04-2008 |