| Intersil Americas Inc. Patent applications |
| Patent application number | Title | Published |
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| 20120133037 | CLIP INTERCONNECT WITH ENCAPSULATION MATERIAL LOCKING FEATURE - A clip interconnect comprises a columnar part, a bridge part, and a locking feature. The bridge part has a plurality of sides. The columnar part and the bridge part are configured to form an angle at an interface between the columnar part and the bridge part. The locking feature is located in at least one of the plurality of sides of the bridge part. The locking feature comprises an alternating pattern of teeth and valleys. | 05-31-2012 |
| 20120126773 | SWITCHING REGULATOR WITH BALANCED CONTROL CONFIGURATION WITH FILTERING AND REFERENCING TO ELIMINATE COMPENSATION - A switching regulator and controller and an electronic device using same are disclosed in which the controller includes a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal and which balances the filtered sense signal and the error signal at a common DC level. The comparator circuit develops a pulse control signal using the error signal and the filtered sense signal, where the pulse control signal is for controlling switching of the pulse switch circuit. | 05-24-2012 |
| 20120119833 | CLASS AB OUTPUT STAGES AND AMPLIFIERS INCLUDING CLASS AB OUTPUT STAGES - A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and includes an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier. | 05-17-2012 |
| 20120112721 | SYNTHETIC RIPPLE REGULATOR WITH FREQUENCY CONTROL - A synthetic ripple regulator including frequency control based on a reference clock. The regulator includes an error network, a ripple detector, a combiner, a ripple generator, a comparator network and a phase comparator. The error network provides an error signal indicative of relative error of the output voltage. The ripple detector provides a ramp control signal based on the input and output voltages and a pulse control signal. The combiner adjusts the ramp control signal based on a frequency compensation signal to provide an adjusted ramp control signal. The ripple generator develops a ripple control signal based on the adjusted ramp control signal. The comparator network develops the pulse control signal to control switching based on the error signal and the ripple control signal. The phase comparator compares the pulse control signal with the reference clock and provides the frequency compensation signal. | 05-10-2012 |
| 20120105038 | CLOCK PHASE SHIFTER FOR USE WITH BUCK-BOOST CONVERTER - A buck boost converter generates a regulated output voltage responsive to an input voltage and switching control signals. Switching control circuitry generates the switching control signals responsive to the regulated output voltage, a maximum duty cycle signal and a mode signal. Mode control circuitry generates the maximum duty cycle signal and the mode signal responsive to a buck PWM signal and a boost PWM signal, a first clock signal and a second clock signal phase shifted from the first clock signal by a fixed, programmable amount. A phase shifter generates the first clock signal and the second clock signal responsive to a reference voltage and a synchronization signal. | 05-03-2012 |
| 20120098090 | HIGH-EFFICIENCY POWER CONVERTERS WITH INTEGRATED CAPACITORS - A power converter device comprises a substrate, a power die mounted on the substrate, and a capacitor die mounted over the power die in a stacked configuration. The capacitor die is electrically coupled to the power die. A packaging material encapsulates the power die and the capacitor die. An integrated circuit die can also be mounted to the substrate and electrically coupled to the power die to receive power signals from the power die, with the packaging material also encapsulating the integrated circuit die. | 04-26-2012 |
| 20120092899 | DYNAMIC CONVERTER TOPOLOGY - Methods and apparatus of dynamic topology power converters are provided. One method includes monitoring at least one variable of the power converter and based on the at least one monitored variable, using a converter topology selected between at least a full-bridge converter topology and a half-bridge converter topology to achieve an efficient operation at a then current operational load. | 04-19-2012 |
| 20120091320 | CONFIGURABLE PHOTO DETECTOR CIRCUIT - A configurable photo detector circuit comprises a photo detector array including a plurality of photo detectors coupled to a plurality of amplifiers. A method for programming a detection pattern of the configurable photo detector circuit comprises selecting a first detection pattern for the photo detector array, generating first signals to create the first selected detection pattern, and applying the first generated signals to the photo detector circuit to implement the first selected detection pattern. | 04-19-2012 |
| 20120086401 | CELL BALANCING CIRCUIT FOR USE IN A MULTI-CELL BATTERY SYSTEM - An apparatus for balancing a multi-cell battery pack has a plurality of switchable loads. Each of the plurality of switchable loads are associated with one of a plurality of cells of a multi-cell battery. The plurality of switchable loads discharge an associated cell in a first mode and diverts part of a charging current away from the associated cell in a second mode responsive to a drive signal. A plurality of current mode driver circuits applies the drive signal to each of the plurality of switched loads. | 04-12-2012 |
| 20120081936 | SYSTEM AND METHOD FOR CONVERTING AN AC INPUT VOLTAGE TO A REGULATED DC OUTPUT VOLTAGE USING A Z-TYPE CONVERTER WITH RECTIFIED SWITCHES - An AC to DC converter for converting an AC input voltage to a regulated DC output voltage using a Z-type converter and rectified switches. The Z-type converter includes first and second inductors, a capacitor, two rectified switches and a load device coupled in a cross-coupled configuration. The Z-type converter may be configured according to a Z-source or a quasi-Z-source rectifier network. The AC input voltage is applied to an input and the DC output voltage is developed across the load device. Each rectified switch may be configured as a series-coupled diode and electronic switch or as a dual gate GaN device with a shorted gate. A control network monitors the DC output voltage and develops a control signal for controlling the first and second rectified switches to regulate the DC output voltage. The control network may control the rectified switches based on duty cycle control or current mode control. | 04-05-2012 |
| 20120081128 | SYSTEM AND METHOD FOR DETECTION OF OPEN CONNECTIONS BETWEEN AN INTEGRATED CIRCUIT AND A MULTI-CELL BATTERY PACK - An apparatus comprises an integrated circuit and an open connection detection circuit within the integrated circuit. The integrated circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack. The open connection detection circuit within the integrated circuit detects an open connection on at least one of the plurality of inputs from the multi-cell battery and generates a fault condition responsive thereto. | 04-05-2012 |
| 20120081081 | SYSTEM AND METHOD FOR CONVERTING AN AC INPUT VOLTAGE TO A REGULATED OUTPUT CURRENT - A converter according to one embodiment converts an AC voltage to a regulated output current provided to a DC load of a Z-type configuration. A filter capacitor is provided to average current flowing through the load. The converter includes a rectifier network for rectifying the AC voltage and for providing a rectified voltage, and a smoothing capacitor for smoothing the rectified voltage. The converter includes a hysteretic current mode controller which controls a switching transistor based on sensed voltage and sensed current provided through an inductor coupled in series with the load. The transistor is turned on when current reaches a low valley level and is turned off when the current reaches a peak level. Operation toggles in this manner while a sensed voltage is above a predetermined level. A valley fill network may be provided to keep sensed voltage from falling below the predetermined minimum level. | 04-05-2012 |
| 20120081016 | LED DRIVER WITH ADAPTIVE DYNAMIC HEADROOM VOLTAGE CONTROL - A multi-channel LED driver includes a plurality of linear current regulators, each connected to a bottom of a string of series connected LEDs of a multi-channel LED that controls a bias current and the string of series connected LEDs responsive to an LED bias reference voltage. A dynamic headroom regulation voltage control circuit monitors the headroom regulation voltage at the bottom of each string of the series connected LEDs in the multi-channel LED and generates a reference voltage controlling each of the headroom regulation voltages responsive to the LED bias reference voltage. | 04-05-2012 |
| 20120075006 | ZERO PIN SERIAL INTERFACE - A method for controlling performance of an integrated circuit using a zero-pin serial interface is provided. The method comprises identifying a desired performance characteristic of the circuit, and transmitting a first change mode signal to the circuit on a first pin to cause the circuit to enter an instruction reception mode, with the first pin performing differently during a normal operation mode. The method also comprises transmitting a performance adjusting instruction to the circuit on a second pin when the circuit is in the instruction reception mode, with the second pin performing differently during the normal operation mode, and transmitting a second change mode signal to the circuit on the first pin to cause the circuit to enter the normal operation mode. An output performance of the circuit is compared to the desired performance characteristic, with the output performance being the performance of the circuit during the normal operation mode. The circuit is set to permanently provide the output performance when the output performance is within a desired tolerance of the desired performance characteristic. | 03-29-2012 |
| 20120074924 | SYSTEM AND METHOD FOR OPEN LOOP MODULATION TO DETECT NARROW PWM PULSE - An open loop modulation network for a voltage regulator including a latch network, an output sense network, a timing network, and pulse control logic. The latch network latches assertion of a pulse control signal and provides a corresponding latched control pulse indication. The output sense network detects initiation of an output pulse and provides a corresponding output pulse indication. The timing network initiates a delay period in response to the output pulse indication and resets the latched control pulse indication after expiration of the delay period. The pulse control logic terminates the output pulse after the latched control pulse indication is reset and the pulse control signal is negated, whichever occurs last. Very narrow input pulses are detected and either a minimum output pulse is generated or the output pulse is based on the pulse control signal. | 03-29-2012 |
| 20120063045 | DETECTING AND SELECTIVELY IGNORING POWER SUPPLY TRANSIENTS - Systems and methods for discriminating a negative-going load fault from a positive-going input voltage (VIN) surge are disclosed. The system includes a circuit that senses the VIN voltage to generate a disable signal, if the positive-going VIN surge is identified. Specifically, the circuit can include a high pass filter to facilitate identification of the positive-going VIN surge. Moreover, the disable signal is employed to control an overcurrent comparator that provides an overcurrent shut-off. Typically, when the positive-going VIN surge is identified, the disable signal is generated, which masks the overcurrent response, such that, normal operation can be continued without erroneously shutting-off the load. | 03-15-2012 |
| 20120063038 | POWER-SUPPLY MODULE WITH ELECTROMAGNETIC-INTERFERENCE (EMI) SHIELDING, COOLING, OR BOTH SHIELDING AND COOLING, ALONG TWO OR MORE SIDES - An embodiment of a power-supply module includes a package having sides, a first power-supply component disposed in the package, and an electromagnetic-interference (EMI) shield disposed adjacent to two sides of the package. For example, such a module may include component-mounting platforms (e.g., a lead frame or printed circuit board) on the top and bottom sides of the module, and these platforms may provide a level of EMI shielding specified for a particular application. Consequently, such a module may provide better EMI shielding than modules with shielding along only one side (e.g., the bottom) of the module. Moreover, if the module components are mounted to, or otherwise thermally coupled to, the shielding platforms, then the module may provide multi-side cooling of the components. | 03-15-2012 |
| 20120044732 | ISOLATED EPITAXIAL MODULATION DEVICE - An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage. | 02-23-2012 |
| 20120044018 | SYSTEMS AND METHODS FOR IMPROVED OVER-CURRENT CLIPPING - Systems and methods for implementing over-current protection include reducing a clip level while an over-current condition is being detected. Once the over-current condition is no longer detected, the clip level is maintained for a specified period before allowing the clip level to be increased. In an embodiment, the specified period, for which the clip level is maintained before the clip level is allowed to be increased, starts when the over-current condition is no longer detected, and ends when each of N immediately preceding sample(s) of the audio signal are not clipped to the clip level, where N is an integer ≧1. After an over-current condition is no longer detected, and after the clip level has been maintained for the specified period, the clip level can be increased if an over-current condition is not detected for a sample and the clip level is below a specified maximum clip level. | 02-23-2012 |
| 20120033466 | PARTIAL POWER MICRO-CONVERTER ARCHITECTURE - A system and method for reducing the amount of power processed in a power converter during power generation is provided. In one aspect, the system includes a partial power converter connected between a set of power sources and a load. The partial power converter includes a primary power converter coupled to a first power source and a set of auxiliary power converters coupled to the remaining power sources. Moreover, the secondary power converters only process current that is necessary to achieve a maximum power point (MPP) for each power source. In one example, the secondary power converters are smaller in size and/or power rating, as compared to the primary power converter, and thus reduce the size and cost of the system. Additionally, the secondary power converters operate on an “as-needed” basis rather than in “always-on” fashion, and thus are more reliable and efficient. | 02-09-2012 |
| 20120032657 | REDUCING SHOOT-THROUGH IN A SWITCHING VOLTAGE REGULATOR - Methods, apparatuses, and devices for a voltage regulator are provided. In certain examples, a method for preventing shoot-through in a voltage regulator includes determining whether an output stage for a voltage regulator is operating in a continuous-conduction mode (CCM) or a discontinuous conduction mode (DCM); and setting the voltage regulator in one of adaptive dead time mode and programmable dead time mode based on whether the output stage is operating in CCM or DCM. | 02-09-2012 |
| 20120013313 | MULTIPHASE DC-DC CONVERTER USING ZERO VOLTAGE SWITCHING - A multiphase DC-DC converter including at least one conversion path, multiple switch capacitance networks, and a multiphase switch controller. Each conversion path includes first and second intermediate nodes. Each switch capacitance network includes a capacitance coupled in parallel with an electronic switch and is coupled to one of the intermediate nodes. The switch controller controls the switch capacitance networks using zero voltage switching. Multiple phases may be implemented as multiple conversion paths each having first and second intermediate nodes coupled to first and second switch capacitance networks, respectively. A single conversion path may be provided with multiple switch capacitance networks coupled to each intermediate node for multiple phases. Alternatively, a common front end with a first intermediate node is coupled to one or more switch capacitance networks followed by multiple back-end networks coupled in parallel for multiple phases. A regulator may be provided to regulate an output voltage. | 01-19-2012 |
| 20120008359 | ASYMMETRIC ZERO-VOLTAGE SWITCHING FULL-BRIDGE POWER CONVERTERS - Disclosed are full-bridge power converters providing DC output power at increased conversion efficiencies, and methods of operating full-bridge power converters providing DC output power at increased conversion efficiencies. In disclosed embodiments, the switches of the full-bridge are operated to reduce conduction losses and to provide for zero-voltage switching. | 01-12-2012 |
| 20120007199 | PROTECTING BOND PAD FOR SUBSEQUENT PROCESSING - A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad. | 01-12-2012 |
| 20120007097 | SCHOTTKY DIODE WITH COMBINED FIELD PLATE AND GUARD RING - A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate. | 01-12-2012 |
| 20110304393 | CLASS AB OUTPUT STAGES AND AMPLIFIERS INCLUDING CLASS AB OUTPUT STAGES - A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and include an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier. | 12-15-2011 |
| 20110302344 | I2C ADDRESS TRANSLATION - Embodiments of the present invention relate to systems, devices and methods for translating I2C addresses. In accordance with an embodiment, a method for translating an I2C address includes receiving an original I2C address from a first I2C compatible device via an I2C-bus to which the first I2C compatible device is connected. The method also includes translating the original I2C address to a translated I2C address, and outputting the translated I2C address to a second I2C compatible device via a secondary side of the I2C-bus to which the slave device is connected. The original I2C address can be translated to the translated I2C address by subtracting an offset value from (or adding an offset value to) the original I2C address to produce the translated I2C address. Such an offset value can be specified using pin strapping, or by storing the offset value in a register or non-volatile memory that is programmable via the-I2C bus. Alternatively, a look-up-table, that is programmable via the I2C-bus, can be used to perform the I2C address translation. | 12-08-2011 |
| 20110299577 | DIFFERENTIAL DRIVER WITH COMMON MODE VOLTAGE TRACKING AND METHOD - In a transceiver, a transmitter circuit is provided substantially the same common-mode voltage regardless of whether the transceiver is in a transmitting or receiving mode. In one embodiment, the transmitter circuit includes a driver circuit which, in the transmission mode of the transceiver, drives an output differential signal, and which, in the receiving mode of the transceiver, provides a termination circuit for an input differential signal. A variable resistor is provided to connect between a supply voltage and the driver circuit, the resistance of the variable resistor is selected such that the common-mode voltage of the output differential signal of the transmission mode substantially equals the common-mode voltage in the input differential signal of the receiving mode. | 12-08-2011 |
| 20110298483 | TESTER HAVING DEVICE UNDER TEST POWER SUPPLY - A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The | 12-08-2011 |
| 20110286245 | DC/DC POWER CONVERTER HAVING ACTIVE SELF DRIVING SYNCHRONOUS RECTIFICATION - A DC/DC voltage converter includes a transformer having a primary side and a secondary side. Primary side circuitry is connected to the primary side and includes a first pair of switching transistors controlled responsive to first control signals from the primary side of the transformer and receiving an input voltage. Secondary side circuitry is connected to the secondary side and includes a second pair of switching transistors controlled responsive to second control signals from the secondary side of the transformer and providing an output voltage. Driver circuitry generates the second control signals responsive to drain and source voltages at each of the second pair of switching transistors and a first and second PWM control signals. Signal shaping circuitry provides the first and second PWM control signals responsive to a drain voltage of each of the second pair of switching transistors. | 11-24-2011 |
| 20110284922 | DEVICES WITH ADJUSTABLE DUAL-POLARITY TRIGGER-AND HOLDING-VOTAGE/CURRENT FOR HIGH LEVEL OF ELECTROSTATIC DISCHARGE PROTECTION IN SUB-MICRON MIXED SIGNAL CMOS/BICMOS INTEGRATED - Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P | 11-24-2011 |
| 20110273430 | VOLTAGE LEVEL SHIFTING WITH REDUCED POWER CONSUMPTION - In an embodiment, a voltage level shifter circuit includes a first terminal configured to be connected to a high voltage supply rail (Vs+), a second terminal configured to be connected to a low voltage supply rail (Vs−), and an output voltage (V | 11-10-2011 |
| 20110272756 | METHOD OF FORMING AN INSULATOR LAYER IN A SEMICONDUCTOR STRUCTURE AND STRUCTURES RESULTING THEREFROM - An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer. | 11-10-2011 |
| 20110260703 | SYSTEM AND METHOD FOR DETECTION AND COMPENSATION OF AGGRESSIVE OUTPUT FILTERS FOR SWITCHED MODE POWER SUPPLIES - A controller for a switched mode power supply converting an input voltage to a regulated output voltage according to one embodiment includes a control network and a detection network. The control network develops a pulse width control signal for regulating a level of the output voltage. The detection network detects a phase lag of the output voltage and adjusts operation of the control network based on the phase lag. The phase lag may be determined from any parameter incorporating phase shift, such as the output voltage or the compensation voltage. Various alternative schemes are disclosed for adjusting the control loop, including, but not limited to, adding slope compensation, adjusting window resistance or window current, adding adjustment current to adjust ripple voltage, adjusting ripple transconductance, and adjusting ripple capacitance. Digital and analog compensation adjustment schemes are disclosed. | 10-27-2011 |
| 20110256857 | Systems and Methods for Improving Antenna Isolation Using Signal Cancellation - Interference compensation circuits can isolate a victim antenna from an aggressor antenna, which causes the antennas to appear as being spaced further apart. The interference compensation circuit can obtain samples of signals generated by a transmitter for transmission by the aggressor antenna and process the samples to generate an interference compensation signal. The generated interference compensation signal can be applied to a signal path between the victim antenna and a receiver to suppress, cancel, or otherwise compensate for interference imposed on the victim antenna by the signals transmitted from the aggressor antenna. The interference compensation signal is generated by adjusting at least one of amplitude, phase, and delay of the samples to emulate the interference imposed on the victim antenna. | 10-20-2011 |
| 20110249134 | SEMICONDUCTOR DEVICE WITH CONDUCTIVE TRENCHES TO CONTROL ELECTRIC FIELD - An imaging system, semiconductor device, and method of manufacture of a photo-detector device are disclosed. For example, an imaging system is disclosed, which includes a photo-detector unit including a plurality of conductive trenches formed within the photo-detector unit, and a plurality of electrical contacts, each electrical contact connected to a respective conductive trench. The imaging system further includes a light data processor unit coupled to an output of the photo-detector unit to convert an analog signal received from the photo-detector unit to a digital signal, a processing unit coupled to an output of the light data processor unit to generate a control signal in response to the digital signal, and a display unit coupled to an output of the processing unit to vary the intensity of an image displayed in response to the control signal. | 10-13-2011 |
| 20110241734 | COUPLING TOLERANT PRECISION CURRENT REFERENCE WITH HIGH PSRR - Embodiments of the present invention are related to circuits and methods for generating a reference current (Idc). In an embodiment, a voltage-to-current converter circuit is used to generate the reference current (Idc) in dependence on a reference voltage (Vref) and a precision resistor (R | 10-06-2011 |
| 20110241640 | SYSTEM AND METHOD OF INTERMITTENT DIODE BRAKING FOR MULTIPLE PHASE VOLTAGE REGULATOR - A method of operating a regulator controller IC for performing intermittent diode braking for controlling a multiple phase voltage regulator. The method includes receiving at least one signal for detecting repetitive load transients, determining a rate of the repetitive load transients, generating diode braking control signals, each for applying diode braking to a corresponding one of multiple phases for at least one load transient when the repetitive load transients are below a first rate, and controlling the diode braking control signals to drop application of diode braking of at least one phase for at least one load transient when the repetitive load transients are at least the first rate. The method may include rotating the application of diode braking among the phases during successive applications of diode braking. The method may include dropping an increased number of phases for diode braking as the rate of repetitive load transients is increased. | 10-06-2011 |
| 20110241636 | MULTI-PHASE NON-INVERTING BUCK BOOST VOLTAGE CONVERTER - A multi-phase non-inverting buck boost voltage converter has a plurality of buck boost voltage regulators. Each regulator is associated with a separate phase for generating a regulated output voltage responsive to an input voltage. A plurality of current sensors are each associated with one of the plurality of buck boost voltage regulators for monitoring an input current to the associated buck boost voltage regulator and generating a current sense signal for the associated phase. A plurality of buck boost mode control circuitries are each associated with one of the buck boost regulator for controlling an associated buck boost voltage regulator using peak current mode control in a buck mode of operation and valley current mode control in boost mode of operation responsive to a common error voltage and the associated current sense signal. The plurality of buck boost mode control circuitries provides current balancing between the phases. A voltage error circuit generates the error voltage responsive to the regulated output voltage | 10-06-2011 |
| 20110234315 | Power Amplifier Linearization Using Cancellation-Based Feed Forward Methods and Systems - Linearizers can improve the linearity of power amplifiers by canceling or reducing amplitude of non-linearity components, (e.g., IM | 09-29-2011 |
| 20110234193 | MULTIPLE PHASE SWITCHING REGULATOR WITH PHASE CURRENT SHARING - A phase current sharing network for a current mode multiphase switching regulator. The multiphase switching regulator includes switching networks for developing phase currents of switching phase networks controlled by pulse control signals for converting an input voltage to an output voltage. The regulator develops the pulse control signals based on current control values and at least one trigger value. The phase current sharing network includes conversion networks and a phase current combining network. Each conversion network provides a phase current value based on a corresponding phase current, such as by directly or indirectly measuring real current or by synthetically developing the phase current value. The phase current combining network develops an average phase current value based on the phase current values, and subtracts the average phase current value from each phase current value to provide the current control values used to control the switching networks. | 09-29-2011 |
| 20110228661 | HYBRID LASER DIODE DRIVERS - A hybrid LDD includes a read channel to selectively output a read current, a plurality of write channels, each to selectively output a different write current, and an oscillator channel to selectively output an oscillator current. Additionally, the hybrid LDD includes programmable LDD controller that receives the plurality of enable signals from the external controller, and based on the enable signals, controls timing of the currents output by at least the write channels. The programmable LDD controller can also control timing of the currents output by the read and oscillator channels, based on the enable signals. Further and alternative embodiments are also provided. | 09-22-2011 |
| 20110228507 | MOLDED POWER-SUPPLY MODULE WITH BRIDGE INDUCTOR OVER OTHER COMPONENTS - An embodiment of a power-supply module includes a molded package, power-supply components disposed within the package, and an inductor disposed within the package and over the power-supply components. For example, for a given output-power rating, such a power-supply module may be smaller, more efficient, and more reliable than, and may run cooler than, a power-supply module having the inductor mounted outside of the package or side-by-side with other components. And for a given size, such a module may have a higher output-power rating than a module having the inductor mounted outside of the package or side-by-side with other components. | 09-22-2011 |
| 20110227550 | MODULATION SCHEME USING A SINGLE COMPARATOR FOR CONSTANT FREQUENCY BUCK BOOST CONVERTER - A buck boost converter generates an output voltage responsive to an input voltage and at least one switching control signal in a buck mode of operation, a boost mode of operation and a buck-boost mode of operation. Control logic generates the at least one switching control signal responsive to the output voltage, a reference voltage, and a sensed voltage associated with an inductor current of the buck boost converter. The sensed voltage associated with the inductor current enables the control logic to generate the at least one switching control signal in a selected one of the buck mode of operation, the boost mode of operation and the buck-boost mode of operation. | 09-22-2011 |
| 20110227549 | DC/DC CONVERTER INCLUDING ULTRASONIC FEATURE FOR USE WITH LOW QUIESCENT CURRENTS - A buck voltage converter comprises an upper switching transistor connected between an input voltage node and a phase node. The upper switching transistor turns on and off responsive to a first drive signal. A lower switching transistor is connected between the phase node and ground. The lower switching transistor turns on and off responsive to a second drive signal. An inductor is connected the phase node and an output voltage node. Control circuitry generates the first drive signal and the second drive signal responsive to a feedback voltage monitored at the output voltage node and a phase at the phase node. In a pulse frequency mode voltage of operation the control circuitry turns off the upper switching transistor and turns on the lower switching transistor responsive to a determination that a predetermined period of time has occurred since a detection of a phase switch at the phase node and turns off both the upper switching transistors and the lower switching after the lower switching transistor has been turned on for a second predetermined period of time. | 09-22-2011 |
| 20110221478 | CIRCUIT FOR MULTIPLEXING DIGITAL AND ANALOG INFORMATION VIA SINGLE PIN OF DRIVER FOR SWITCHED MOSFETS OF DC-DC CONVERTER - Multiple characteristics of a DC-DC converter, such as its mode of operation (e.g., either forced continuous conduction mode, or discontinuous conduction mode), and an operational parameter (such as the dead-time between switching times of the output switching devices (upper and lower MOSFETs) of the converter, whose associated driver integrated circuit has a pin usage that leaves only a single pin available for auxiliary purposes, are programmed by a single pin-based digital and analog information extracting circuit that couples both digital information and analog information within the same control signal to the driver IC by way of only the one available pin. | 09-15-2011 |
| 20110212696 | System and Method for Reducing In-Band Interference for a Shared Antenna - An interference compensation circuit for suppressing in-band or nearby out-of-band interference in a shared antenna communication system. The communication system can include a first communication device having a transmitter for transmitting signals within a first frequency band and a second communication device having a receiver for receiving electromagnetic signals within a second frequency band. The second frequency band can be adjacent or overlapping the first frequency band. The communication system also can include an interference compensation circuit that receives samples of the signals transmitted by the transmitter and generate an interference compensation signal in response to adjusting amplitude, phase, and/or delay of the samples. The interference compensation signal can suppress interference imposed on the receiver by the signals transmitted by the transmitter when applied to a signal receive path of the receiver. | 09-01-2011 |
| 20110212692 | Cascaded Filter Based Noise and Interference Canceller - Signals propagating from an aggressor communication channel can cause detrimental interference in a victim communication channel. A high input power cascaded filter canceller (“HIPCF”) can obtain a sample of the signal that imposes interference and process the sampled signal to generate an interference compensation signal that, when applied to the victim communication channel, cancels or suppresses the detrimental interference. The HIPCF canceller can include two or more cascaded filters, such as band-pass filters, that block or reduce amplitude of a signal outside the communication frequency band of a victim receiver. The HIPCF canceller also includes an I/Q modulator that receives the filtered signal and generates the interference compensation signal by adjusting or updating one or more aspects of the filtered signal, such as a gain, phase, or delay, based upon feedback from the victim receiver or a power detector and algorithms executed by the controller. | 09-01-2011 |
| 20110211649 | Methods and Systems for Noise and Interference Cancellation - Signals propagating from an aggressor communication channel can cause detrimental interference in a victim communication channel. One or more noise cancellers can generate an interference compensation signal to suppress or cancel the interference based on one or more settings. A controller can execute algorithms to find preferred settings for the noise canceller(s). The controller can use a feedback signal (e.g., receive signal quality indicator) received from a victim receiver during the execution of the algorithm(s) to find the preferred settings. One exemplary algorithm includes sequentially evaluating the feedback resulting from a predetermined list of settings. Another algorithm includes determining whether to move from one setting to the next based on the feedback values for both settings. Yet another algorithm includes evaluating a number of sample settings to determine which of the sample settings result in a better feedback value and searching around that sample setting for a preferred setting. | 09-01-2011 |
| 20110205096 | SYSTEMS INCLUDING A PROGRAMMABLE SEGMENTED DAC AND METHODS FOR USE THEREWITH - A segmented digital-to-analog converter (DAC) includes a plurality of sub-DACs, each of which is adapted to receive a separate reference current that specifies a transfer function of the sub-DAC. A magnitude of the reference current provided to each sub-DAC is separately programmable to thereby separately control a gain of each sub-DAC. The output of the DAC can be used to drive a load having a load transfer function that differs from a desired transfer function. In an embodiment, the separate reference currents provided the sub-DACs of the DAC are programmed to implement a DAC transfer function that causes the DAC and the load (driven by the output of the DAC) to collectively have an effective transfer function that is substantially similar to the desired transfer function. | 08-25-2011 |
| 20110205095 | DATA LOOK AHEAD TO REDUCE POWER CONSUMPTION - Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Additionally, or alternatively, while the portions of the digital signal are being buffered, there can be a determination, based on the buffered portions of the digital signal, of when one or more system related parameters can be adjusted to temporarily reduce power dissipation. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa. Eventually, the portions of the digital signal are provided to the sub-system so that the sub-system can respond to the portions of the digital signal. | 08-25-2011 |
| 20110204947 | METHOD AND APPARATUS FOR ADAPTIVELY MODIFYING A PULSE WIDTH OF A PULSE WIDTH MODULATED OUTPUT - Systems, methods, and apparatus for improving steady state operation of a pulse width modulator during transient and soft start events are described herein. An apparatus can include a phase component configured to adaptively modify a pulse width of a first pulse width modulated (PWM) output signal based on a pulse width of a PWM input signal. Further, the apparatus can include a power stage component configured to source at least one of a voltage or a current to a load based on the first PWM output signal. In one example, the phase component can be configured to linearly extend the pulse width of the first PWM output signal based on the pulse width of the PWM input signal. In another example, the phase component can be configured to adaptively modify the pulse width of the first PWM output signal based on a predetermined maximum pulse width. | 08-25-2011 |
| 20110204237 | LIGHT SENSORS WITH INFRARED SUPPRESSION - Embodiments of the present invention are directed to light sensors that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors. | 08-25-2011 |
| 20110198485 | DYNAMICALLY CONFIGURABLE PHOTODETECTOR ARRAYS - In accordance with an embodiment, a circuit includes a photodetector (PD) array including a plurality of electrically isolated PD sections. Additionally, the circuit includes a switching matrix that includes a plurality of inputs and a plurality of outputs, and that can be selectively configured in a plurality of different switch configurations. Each of the electrically isolated PD sections is adapted to detect light (if any) and provide an electrical output signal, indicative of the light detected by the PD section (if any), to a different one of the inputs of the switching matrix. The switching matrix is adapted to combine the electrical output signals provided by the electrically isolated PD sections in a plurality of different manners, in dependence on which of the plurality of different switch configurations is selected. | 08-18-2011 |
| 20110194595 | METHODS AND SYSTEMS FOR TRANSMITTING SIGNALS DIFFERENTIALY AND SINGLE-ENDEDLY ACROSS A PAIR OF WIRES - Provided herein are systems and methods for transmitting signals across a pair of wires. In accordance with specific embodiments, a differential signal is transmitted across the pair of wires during one period of time, and two single-ended signals are transmitted across the same pair of wires during another period of time. Low voltage differential signaling (LVDS) can be used to transmit the differential signal across the pair of wires. In contrast, non-differential signaling can be used to transfer the two singled-ended signals across the same pair of wires. | 08-11-2011 |
| 20110190028 | Power Amplifier Linearization Feedback Methods and Systems - Linearizers can improve the linearity of power amplifiers by canceling or reducing amplitude of non-linearity components, (e.g., IM | 08-04-2011 |
| 20110187570 | SIGMA DELTA CONVERTER SYSTEM AND METHOD - A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer. | 08-04-2011 |
| 20110187336 | NON-INVERTING BUCK BOOST VOLTAGE CONVERTER - A non-inverting buck boost voltage converter includes a buck boost voltage regulation circuitry for generating a regulated output voltage responsive to an input voltage. A current sensor monitors an input current to the buck boost voltage regulation circuitry. Buck boost mode control circuitry controls the buck boost voltage regulation circuitry using peak current mode control in a buck mode of operation and valley current mode control in boost mode of operation responsive to the monitored input current. | 08-04-2011 |
| 20110187189 | SYSTEM AND METHOD FOR CONTROLLING SINGLE INDUCTOR DUAL OUTPUT DC/DC CONVERTERS - A DC to DC converter comprises voltage regulation circuitry for generating at least two output voltages responsive to an input voltage. The voltage regulation circuitry further includes a plurality of main switches connected to receive the input voltage. A plurality of auxiliary switches is connected to provide the at least two output voltages. A single inductor is connected between the plurality of main switches and the plurality of auxiliary switches. A dual-output PWM controller provides a first PWM control signal for controlling the operation of the plurality of main switches responsive to a first feedback voltage from a first output voltage using a first control loop and provides a second PWM control signal for controlling the operation of the plurality of auxiliary switches responsive to a second feedback voltage from a second output voltage using a second control loop. Current mode control can be used for each control loop to reduce the cross regulation problem. | 08-04-2011 |
| 20110182519 | GESTURE RECOGNITION WITH PRINCIPAL COMPONENT ANAYSIS - A system and method for identifying a position of a moving object, utilizing sensors arranged in any arbitrary configuration, is provided. A pre-processing method is applied to permit implementation on a low power computing device, such as a microcontroller. The preprocessing creates a set of training data corresponding to different gestures, based on different positions of moving objects. Accordingly, utilizing the training data, different types of gestures can be classified by comparing a sensed signal to the set of training gestures. | 07-28-2011 |
| 20110182126 | FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells. | 07-28-2011 |
| 20110181892 | AUTOMATIC CALIBRATION TECHNIQUE FOR TIME OF FLIGHT (TOF) TRANSCEIVERS - A system and method for automatically calibrating a Time-of-Flight (TOF) transceiver system for proximity/motion detection, is provided. Moreover, the system comprises a component that senses a signal (e.g., current or voltage) at an light emitting diode (LED), an attenuator, a signal injector at a sensor and a switching circuit that toggles between a normal mode (e.g., when signal from the sensor is input to the sensor front end) and a calibration mode (e.g., when signal from the attenuator is input to the sensor front end). During the calibration mode, the sensor front end identifies the phase delay error within the signal path, including board and/or package parasitic, and accounts for the phase delay error during proximity/motion detection in the normal mode. | 07-28-2011 |
| 20110181861 | DISTANCE SENSING BY IQ DOMAIN DIFFERENTIATION OF TIME OF FLIGHT (TOF) MEASUREMENTS - A system and method for identifying a position of a moving object, regardless of static objects present in the optical field of an active infrared (IR) proximity detector, is provided. Moreover, a modulated light emitting diode (LED) signal is captured and processed through I/Q demodulation. Specifically, the reflections received at an IR sensor are demodulated to generate in-phase (I) and quadrature phase (Q) signals and the derivative of I/Q signals is obtained to isolate motion. For example, an I/Q domain differentiator or a high pass filter is employed to calculate the derivative, which actively remove the effects of all forms of static interference. Further, the phase of the derivative I/Q signals is determined and is utilized to reconstruct the distance at which the motion occurred. | 07-28-2011 |
| 20110181254 | DIRECT CURRENT (DC) CORRECTION CIRCUIT FOR A TIME OF FLIGHT (TOF) PHOTODIODE FRONT END - A system and method that compensates for the effects of ambient light in a time of flight (TOF) sensor front end is provided. Moreover, a direct current (DC) correction loop is utilized at the front end, which removes a DC component from a current generated by the TOF sensor and accordingly prevents saturating the front end. The DC correction loop attenuates the DC component without adding significant thermal noise at a modulation frequency and provides a corrected signal to the front end circuitry. The corrected signal is processed and utilized to detect a position of an object within the optical field of the sensor. | 07-28-2011 |
| 20110181253 | SYSTEM AND METHOD FOR HIGH PRECISION CURRENT SENSING - An apparatus for sensing an input current through an inductor includes an RC circuit connected in parallel with the inductor across first and second input pins of an integrated circuit. A voltage monitoring circuit monitors a first voltage at the first input pin of the integrated circuit and monitors a second voltage at the second input pin of the integrated circuit. An op-amp compares the first voltage with the second voltage and generates a control output responsive to the comparison. A current sink circuit responsive to the indication controls the first voltage to substantially equal the second voltage. | 07-28-2011 |
| 20110180709 | SERIAL-CHAINING PROXIMITY SENSORS FOR GESTURE RECOGNITION - A system and method for identifying a position of a moving object, utilizing a serial chain of sensors is provided. The serial chain reduces the power needed for the motion detection system, allowing implementation of the motion detection system on a low-power computing device, such as a microcontroller. The serial chain can provide automatic address assignment without dedicated pins. The serial chain can also provide automatic sequencing of access to a shared LED. The serial chain can also provide automatic time correlation of data from multiple sensors in the motion detection system. | 07-28-2011 |
| 20110180693 | PHOTODIODE FRONT END WITH IMPROVED POWER SUPPLY REJECTION RATIO (PSRR) - An area effective system and method for improving power supply rejection ratio (PSRR) in an optical sensor front end, is provided. Moreover, low pass filter (LPF) that enables the reference voltage in the front end of the optical sensor, to be referred to the same substrate as that employed by the sensor. In one example, the LPF includes a capacitor, implemented using a Deep-N-Well (DNW) depletion capacitor, which is utilized to connect the reference voltage to the same substrate. Additionally, the DNW allows an area efficient realization of the LPF. The system and method disclosed herein improves the PSRR by a factor of around 40 dB for 5 MHz modulation. | 07-28-2011 |
| 20110177684 | METHOD OF MANUFACTURING A JUNCTION BARRIER SCHOTTKY DIODE WITH DUAL SILICIDES - An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well. | 07-21-2011 |
| 20110176368 | MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE - A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state. | 07-21-2011 |
| 20110176069 | SYSTEMS AND METHODS FOR PROJECTOR LIGHT BEAM ALIGNMENT - Embodiments of the present invention generally relate to circuits, systems and methods that can be used to detect light beam misalignment, so that compensation for such misalignment can be performed. In accordance with an embodiment, a circuit includes a photo-detector (PD) having a plurality of electrically isolated PD segments. Additionally, the circuit has circuitry, including switches, configured to control how currents indicative of light detected by the plurality of electrically isolated PD segments are arithmetically combined. When the switches are in a first configuration, a signal produced by the circuitry is indicative of vertical light beam alignment. When the switches are in a second configuration, the signal produced by the circuitry is indicative of horizontal light beam alignment. The signals indicative of vertical light beam alignment and horizontal light beam alignment can be used detect light beam misalignment, so that compensation for such misalignment can be performed. | 07-21-2011 |
| 20110175669 | ANALOG SWITCH WITH INTERNAL DEVICE BODY CONTROL - A body control apparatus for an analog switch for minimizing leakage current and keeping PN junctions reverse-biased. The analog switch has first and second switch device clusters coupled between input and output nodes and controlled by a control input, each having a corresponding body junction. The body control apparatus includes body control devices each controlled by one of the input and output nodes for coupling a body junction to the opposite one of the input and output nodes. Each switch device cluster may include a main switch and body devices which keep the body junction of the main switch at a voltage level between the input and output nodes when the analog switch is on. When the analog switch is off, the body control apparatus activates when voltage across the input and output nodes rises to keep the body junctions at desired voltage levels. | 07-21-2011 |
| 20110170709 | SYSTEMS AND METHODS TO REDUCE IDLE CHANNEL CURRENT AND NOISE FLOOR IN A PWM AMPLIFIER - Systems and methods provided herein decrease an idle channel noise floor and reduce power during an idle channel input for low power audio devices that include a digital pulse width modulation (PWM) amplifier having a noise shaper. An audio data signal is monitored for an idle channel condition. The noise shaper performs quantization of the audio data signal and uses noise shaper filter coefficients to shape noise resulting from the quantization. Predetermined values for the noise shaper filter coefficients are used to shape the noise resulting from quantization while the idle channel condition is not being detected. The values of the noise shaper filter coefficients are reduced so that the values move toward zeros, and the reduced values of the noise shaper filter coefficients are used to attenuate noise resulting from quantization, while the idle channel condition is being detected. The noise shaper filter coefficients are returned to the predetermined values when the idle channel condition is no longer detected. Alternative embodiments are also provided. | 07-14-2011 |
| 20110169472 | DC-DC CONVERTERS HAVING IMPROVED CURRENT SENSING AND RELATED METHODS - A DC-DC converter includes a chip including an error amplifier and a pulse width modulator (PWM) having an input connected to an output of the error amplifier, and an inductor driven by said PWM in series with an output node (V | 07-14-2011 |
| 20110163731 | THRESHOLD VOLTAGE MONITORING AND CONTROL IN SYNCHRONOUS POWER CONVERTERS - A method of providing threshold voltage monitoring and control in synchronous power converters is provided. The method includes establishing a threshold voltage level for at least one of a gate drive voltage for an upper and a lower power switch in a synchronous power converter, each threshold voltage level controlling a switching delay time for one of the upper and lower power switches. The method further includes detecting body diode conduction levels for at least one of the upper and lower power switches and adjusting the threshold voltage level for at least one of the upper and lower power switches, based on the detected body diode conduction levels, to fine-tune a body diode conduction time around an equilibrium for the at least one of the upper and lower power switches. | 07-07-2011 |
| 20110163434 | STACKED POWER CONVERTER STRUCTURE AND METHOD - A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad. | 07-07-2011 |
| 20110157485 | SYSTEMS AND METHODS FOR PARTITIONED COLOR, DOUBLE RATE VIDEO TRANSFER - Systems, methods and devices provide for fast and power efficient transfer of three color data words (e.g., a M-bit red color word, a M bit green color word and a M-bit blue color word) per pixel from a controller to a laser diode driver (LDD). First and second transfer words are produced based on the three color data words. The first transfer word is transferred from the controller to the LDD and stored at LDD in response to a low-to-high portion of a cycle of a data transfer clock, and the second transfer word is transferred and stored in response to a high-to-low portion of a cycle of the data transfer clock. The first, second and third color data words are reproduced by the LDD in dependence on the first and second received transfer words. First, second and third DACs of the LDD are driven with the first color data word, the second color data word, and the third color data word. Three light sources (e.g., red, green and blue laser diodes or LEDs) are driven with output currents of the DACs. | 06-30-2011 |
| 20110156787 | ENABLE PIN USING PROGRAMMABLE HYSTERESIS IMPROVEMENT - An apparatus for providing programmable hysteresis control using an enable pin of a device is disclosed. An enable pin is configured to receive an input signal to enable and disable an associated device responsive to the input signal. A current sink is attached to the enable pin and is responsive to circuitry that disables the current sink responsive to application of the input signal at a first voltage level and enables the current sink responsive to application of the input signal at a second voltage level. | 06-30-2011 |
| 20110149611 | BIDIRECTIONAL SIGNAL CONVERSION - An embodiment includes coupling a first intermediate node between a first inductor and a first winding of a transformer to a reference node during a first portion of a first switching cycle, uncoupling the first intermediate node from the reference node and coupling the first intermediate node to a signal-storage element during a second portion of the first switching cycle, coupling a second winding of the transformer between the reference node and a second converter node during the second portion of the first switching cycle, and regulating a signal at the second converter node by controlling a duration of one of the first and second portions of the first switching cycle. For example, in an embodiment, bidirectional signal converter may perform the above steps to handle power transfer between two loads. Such a voltage converter may have improved conversion efficiency and a smaller size and lower component count as compared to a conventional bidirectional voltage converter. Furthermore, such a voltage converter may be operable with a common switching scheme regardless of the direction of power transfer, and without the need for an indicator of the instantaneous direction of power flow. | 06-23-2011 |
| 20110149610 | BIDIRECTIONAL SIGNAL CONVERSION - An embodiment of a multidirectional signal converter includes first and second converter nodes, a transformer, and first and second stages. The transformer includes first and second windings, and the first stage is coupled between the first converter node and the first winding of the transformer. The second stage includes a first node coupled to the second converter node, a second node coupled to a node of the second winding of the transformer, and a filter node, is operable as a boost converter while current is flowing out from the second converter node, and is operable as a buck converter while current is flowing out from the first converter node. For example, in an embodiment, such a multidirectional signal converter may be a bidirectional voltage converter that handles power transfer between two loads. Such a voltage converter may have improved conversion efficiency and a smaller size and lower component count as compared to a conventional multidirectional voltage converter. Furthermore, such a voltage converter may be operable with a common switching scheme regardless of the direction of power transfer, and without the need for an indicator of the instantaneous direction of power flow. | 06-23-2011 |
| 20110149609 | BIDIRECTIONAL SIGNAL CONVERSION - An embodiment of a controller for a multidirectional signal converter is operable to cause the converter to regulate a first signal at a first converter node, and to have a switch timing that is independent of a direction of power transfer between the first converter node and a second converter node. For example, in an embodiment, such a controller may be part of a bidirectional voltage converter that handles power transfer between two loads. Such a voltage converter may have improved conversion efficiency and a smaller size and lower component count as compared to a conventional multidirectional voltage converter. Furthermore, such a voltage converter may be operable with a common switching scheme regardless of the direction of power transfer, and without the need for an indicator of the instantaneous direction of power flow. | 06-23-2011 |
| 20110141696 | THERMAL MATCHING IN SEMICONDUCTOR DEVICES USING HEAT DISTRIBUTION STRUCTURES - Embodiments described herein provide a chip, comprising a first device on a substrate and a second device on the substrate. The chip further comprises a heat distribution structure in thermal proximity to the first device and the second device, wherein the heat distribution structure is thermally isolated and reduces a thermal gradient between the first device and the second device. | 06-16-2011 |
| 20110140232 | METHODS OF FORMING A THERMAL CONDUCTION REGION IN A SEMICONDUCTOR STRUCTURE AND STRUCTURES RESULTING THEREFROM - An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a semiconductor layer over a thermal conduction layer, forming an isolation region over the thermal conduction layer, and forming a thermal conduction region in the isolation region. | 06-16-2011 |
| 20110134613 | STACKED INDUCTOR-ELECTRONIC PACKAGE ASSEMBLY AND TECHNIQUE FOR MANUFACTURING SAME - An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor. | 06-09-2011 |
| 20110133717 | CONTROLLER AND DRIVER COMMUNICATION FOR SWITCHING REGULATORS - Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode. | 06-09-2011 |
| 20110133716 | CONTROLLER AND DRIVER COMMUNICATION FOR SWITCHING REGULATORS - Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode. | 06-09-2011 |
| 20110133553 | SYSTEM AND METHOD FOR DELAYING PHASE SHIFT WITHIN A DC/DC CONVERTER - A multi-output DC/DC voltage regulator has a master regulator for providing a first output voltage pulse responsive to an input voltage. The master regulator generates a synchronization signal that ramps from a first level up to a second level and discharges back to the first level responsive to the first output voltage pulse. At least one slave regulator provides a second output voltage pulse responsive the input voltage and a delay signal. The at least one slave regulator includes comparison logic for comparing the synchronization signal with a reference value and generates the delay signal to initiate the second output voltage pulse when the synchronization signal substantially equals the reference value. The first output voltage pulse is delayed from the second output voltage pulse by a selected amount. | 06-09-2011 |
| 20110127988 | ROTATING GAIN RESISTORS TO PRODUCE A BANDGAP VOLTAGE WITH LOW-DRIFT - In accordance with an embodiment of the present invention, a bandgap voltage reference circuit includes a plurality of circuit branches, a plurality of resistors and a plurality of switches. The plurality of switches are used to selectively change over time which of the resistors are connected to be within a first one of the circuit branches and which of the resistors are connected to be within a second one of the circuit branches, to thereby reduce the effects that long term drift of the resistors have on a bandgap voltage output (VGO) of the bandgap voltage reference circuit. | 06-02-2011 |
| 20110127987 | CIRCUITS AND METHODS TO PRODUCE A BANDGAP VOLTAGE WITH LOW-DRIFT - In accordance with an embodiment of the present invention, a bandgap voltage reference circuit includes a group of X current sources, a plurality of circuit branches, and a plurality of switches. Each of the X current sources (where X≧3) produces a corresponding current that is substantially equal to the currents produced by the other current sources within the group. The plurality of circuit branches of the bandgap voltage reference circuit are collectively used to produce a bandgap voltage output (VGO). Each of the plurality of circuit branches receives at least one of the currents not received by the other circuit branches. The plurality of switches (e.g., controlled by a controller) selectively change over time which of the currents produced by the current sources are received by which of the plurality of circuit branches of the bandgap voltage reference circuit. | 06-02-2011 |
| 20110122056 | REFERENCE VOLTAGE GENERATORS FOR USE IN DISPLAY APPLICATIONS - A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver. | 05-26-2011 |
| 20110121795 | PROGRAMMABLE POWER SUPPLY CONTROLLER AND METHODOLOGY FOR AUTOMATIC PHASE ADJUSTMENT OF A PWM OUTPUT SIGNAL - A controller and methodology for a power supply are disclosed. The controller includes output channels for providing a pulse width modulation (PWM) voltage signal for driving a load, for example, a microprocessor. Each channel provides a portion of the PWM signal. The controller receives user input information and uses that information to automatically determine window sizes. A window size defines the maximum output current level for a given window. The controller uses feedback signals to determine the current being drawn by the load, and selects the number of windows and channels that are needed to adequately provide that current. The controller selectively activates and deactivates the output channels accordingly. In response a change in the user input information the controller automatically adjusts the window sizes. | 05-26-2011 |
| 20110116324 | MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells. | 05-19-2011 |
| 20110116319 | MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells. | 05-19-2011 |
| 20110116318 | MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells. | 05-19-2011 |
| 20110115450 | SYSTEM AND METHOD FOR CONTROLLING START UP OF A VOLTAGE REGULATOR SYSTEM WITH INDEPENDENT VOLTAGE REGULATION - A multichannel voltage regulator includes a plurality of voltage regulator modules for generating a regulated output voltage responsive to an input voltage and a feedback voltage. Synchronization circuitry controls a release of PWM signals during soft start within each of the plurality of voltage regulator modules. The PWM signals release are synchronized to occur substantially at a same point in time. | 05-19-2011 |
| 20110109487 | INTEGRATED NON-LINEARITY (INL) AND DIFFERENTIAL NON-LINEARITY (DNL) CORRECTION TECHNIQUES FOR DIGITAL-TO-ANALOG CONVERTERS (DACS) - INL values are determined for a plurality of sub-segments of a DAC that is adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to thereby improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the plurality of sub-segments for which INL values were determined, and a second set of correction codes that can be used to ensure that all values of DNL >−1 (to thereby ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2̂N possible digital input codes (that can be accepted by the DAC) to more than 2̂N possible digital output codes, to ensure that all values of DNL >−1. Such stored first and second sets are thereafter used when performing digital to analog conversions. | 05-12-2011 |
| 20110109346 | APPARATUS AND METHODOLOGY FOR MAXIMUM POWER POINT TRACKING FOR A SOLAR PANEL - Circuitry and methodology for tracking the maximum power point (MPP) of a solar panel is disclosed. The voltage and current generated by the solar panel are monitored and used to generate a pulse signal for charging a capacitor. The changes in the voltage and current generated by the solar panel are also monitored, and that information is used to generate a pulse signal for discharging the capacitor. The charging and the discharging pulse signals are used to charge and discharge the capacitor. A reference signal indicative of the charge level of the capacitor is generated. As the current and voltage generated by the solar panel approach the maximum power point (MPP), the frequency of the discharging pulse signal becomes progressively higher, so that the capacitor charging occurs in progressively smaller increments. When the MPP is reached, the reference signal level becomes steady because the charge level of the capacitor becomes steady. | 05-12-2011 |
| 20110109284 | SYSTEM AND METHOD FOR EQUALIZING THE SMALL SIGNAL RESPONSE OF VARIABLE PHASE VOLTAGE REGULATORS - A control circuit for a variable phase voltage regulator comprises an error amplifier to generate a difference signal based on a difference between a reference voltage and a signal representative of a voltage at an output node of the variable phase voltage regulator. The control circuit also comprises a variable phase compensator to amplify the difference signal to produce a modified difference signal to compensate for effects of varying the number of active phases in the variable phase voltage regulator, wherein the amplification is proportional to a ratio of total number of phases in the variable phase voltage regulator to number of active phases in the variable phase voltage regulator. | 05-12-2011 |
| 20110103104 | BIAS AND DISCHARGE SYSTEM FOR LOW POWER LOSS START UP AND INPUT CAPACITANCE DISCHARGE - A power supply including an AC input, a filter, a full wave rectifier, a converter, a second rectifier, and a bias system. The filter includes at least one differential capacitor coupled to the AC input. The full wave rectifier develops a DC bus voltage on a DC bus node. The converter includes a controller and operates to convert the DC bus voltage to a regulated output voltage. The second rectifier is coupled to the AC input for developing a DC bias voltage on a DC bias node. The bias system is coupled between the DC bias node and a reference node and provides at least one start-up voltage to the controller, such as a supply voltage or a sense voltage or the like. The bias circuit includes at least one current discharge path for discharging each differential capacitor within a predetermined time period when AC line voltage is removed. | 05-05-2011 |
| 20110103103 | POWER SUPPLY WITH LOW POWER CONSUMPTION HICCUP STANDBY OPERATION - A power supply including a converter, a capacitance, and a hiccup control module. The converter converts an input voltage to both an output voltage and a preliminary standby voltage when in its active state. The capacitance stores the preliminary standby voltage which is charged to an upper voltage level when the converter is in its active state and which is discharged to a lower voltage level when the converter is in its inactive state. During the standby mode, the hiccup control module operates the converter in hiccup mode by toggling between placing the converter into its inactive state when the preliminary standby voltage is charged to the upper voltage level and placing the converter into its active state when the preliminary standby voltage is discharged to the lower voltage level. The hiccup mode of the power supply eliminates a need for a separate standby converter. | 05-05-2011 |
| 20110102228 | BACKGROUND CALIBRATION OF OFFSETS IN INTERLEAVED ANALOG TO DIGITAL CONVERTERS - A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance. | 05-05-2011 |
| 20110102227 | FINE RESISTANCE ADJUSTMENT FOR POLYSILICON - A resistor string digital to analog converter formed of polysilicon resistor segments to each of which is applied an electric field. The approach improves the overall accuracy. | 05-05-2011 |
| 20110101877 | LED DRIVER WITH OPEN LOOP DIMMING CONTROL - An LED driver with open loop dimming including a full wave rectifier circuit, a DC/DC converter, and an oscillator circuit. The rectifier is configured to receive an input voltage in the form of an AC conductive angle modulated voltage and to provide a rectified voltage. The DC/DC converter converts the rectified voltage to an output voltage and an output current, where the output current has a magnitude which varies proportionately with a square of a quadratic mean of the input voltage. The oscillator circuit controls switching of the DC/DC converter with constant frequency and constant duty cycle. The DC/DC converter may be a flyback converter and may include a transformer operated in DCM. The driver may include output voltage and/or output current limit. The output current may be limited when the input voltage is within normal operating range of an AC line voltage from which the input voltage is derived. | 05-05-2011 |
| 20110096446 | ELECTROSTATIC DISCHARGE CLAMP WITH CONTROLLED HYSTERESIS INCLUDING SELECTABLE TURN ON AND TURN OFF THRESHOLD VOLTAGES - A electrostatic discharge (ESD) clamp for coupling between first and second nodes for providing ESD protection including a clamp circuit and first and second voltage threshold circuits. The clamp circuit limits operating voltage between the first and second nodes to a maximum level when activated. The first and second voltage threshold circuits each have a selectable threshold voltage, such as by coupling one or more voltage threshold devices in series. The first voltage threshold circuit triggers to turn on the clamp circuit when the operating voltage increases above a first voltage threshold. The second voltage threshold circuit triggers when the clamp circuit is turned on and is turned off to turn off the clamp circuit when the operating voltage decreases to the second threshold voltage. The second threshold voltage may be selected at any level above the nominal operating voltage to prevent the clamp from latching. | 04-28-2011 |
| 20110095818 | METHOD AND APPARATUS FOR ACCURATELY MEASURING CURRENTS USING ON CHIP SENSE RESISTORS - Systems and methods for managing process and temperature variations for on-chip sense resistors are disclosed. The system includes a circuit that can leverage a linear gm circuit in order to provide linear gains (positive gains and/or negative gains). The linearity of the circuit enables compensation for temperature and process variations across an entire range of current (positive to negative). A control signal is generated by using a linear gm amplifier and a replica resistor, which is substantially similar to the on chip resistor. The control signal is used to control the gain of a disparate linear gm amplifier within a compensation circuit, which provides an offset voltage to compensate for the variation in resistance of the on chip resistor. | 04-28-2011 |
| 20110089915 | HYSTERETIC CONTROLLED BUCK-BOOST CONVERTER - An apparatus includes a buck boost converter for generating a regulated output voltage responsive to an input voltage. The buck boost converter includes an inductor, a first pair of switching transistors responsive to a first PWM signal and a second pair of switching transistors responsive to a second PWM signal. An error amplifier generates an error voltage responsive to the regulated output voltage and a reference voltage. A control circuit generates the first PWM signal and the second PWM signal responsive to the error voltage and a sensed current voltage responsive to a sensed current through the inductor. The control circuit controls switching of the first pair of switching transistors and the second pair of switching transistors using the first PWM signal and the second PWM signal responsive to the sensed current through the inductor and a plurality of offset error voltages based on the error voltage. | 04-21-2011 |
| 20110085617 | SYSTEM AND METHOD FOR PROVIDING A FULL FAIL-SAFE CAPABILITY IN SIGNAL TRANSMISSION NETWORKS - Systems and methods for providing a full fail-safe capability in signal transmission networks are disclosed. For example, a system for providing a full fail-safe capability in signal transmission networks includes at least a first electronic circuit to transmit and receive signals or data, at least one driver unit coupled to the at least a first electronic circuit, and at least one receiver unit coupled to the at least a first electronic circuit and the at least one driver unit. The at least one receiver unit includes at least one offset signal generating unit, a signal comparing unit, and a switching unit to couple an offset signal from the at least one offset signal generating unit to an input of the signal comparing unit. | 04-14-2011 |
| 20110084681 | CIRCUITS AND METHODS TO PRODUCE A VPTAT AND/OR A BANDGAP VOLTAGE WITH LOW-GLITCH PRECONDITIONING - Provided herein are circuits and methods to generate a voltage proportional to absolute temperature (VPTAT) and/or a bandgap voltage output (VGO) with low 1/f noise. A first base-emitter voltage branch is used to produce a first base-emitter voltage (VBE | 04-14-2011 |
| 20110084620 | ADAPTIVE PWM CONTROLLER FOR MULTI-PHASE LED DRIVER - A multi channel LED driver comprises a plurality of LED strings. Each of the plurality of LED strings are associated with a separate channel. A voltage regulator generates an output voltage to the plurality of LED strings responsive to an input voltage and a PWM control signal. First control logic generates the PWM control signal responsive to a voltage at a bottom of each of the plurality of LED strings. A plurality of dimming circuitries, each connected to one of the bottoms of the plurality of LED strings, control a light intensity in each of the plurality of LED strings responsive to dimming control signals. Second control logic generates the dimming control signals responsive to forward currents monitored through each of the plurality of LED strings and dimming data. | 04-14-2011 |
| 20110080206 | SYSTEM AND METHOD FOR NEGATIVE VOLTAGE PROTECTION - An electronic system is disclosed, which includes a connector unit to communicate data with a host system, an electronic circuit to store the data, and a switch to convey the data to and from the electronic circuit via the connector unit. The switch includes a negative voltage protection unit coupled to the connector unit, and a transistor switch coupled to the negative voltage protection unit, the connector unit, and the electronic circuit. The negative voltage protection unit forces the transistor switch off if a negative voltage is detected. | 04-07-2011 |
| 20110068767 | SUB-VOLT BANDGAP VOLTAGE REFERENCE WITH BUFFERED CTAT BIAS - Circuits, methods, and apparatus that provide voltage references having a temperature independent output voltage that is less then the bandgap of silicon. The temperature coefficient and absolute voltage can be independently adjusted. One example generates two voltages, the first of which is proportional-to-absolute temperature and the second of which is complementary-to-absolute temperature. These voltages are placed across a first resistor. The first resistor is further connected to a second resistor to form a resistor divider. The resistor divider provides a reduced voltage that is below that bandgap of silicon. The temperature coefficient of the reference voltage provided by the resistor divider can be set by adjusting the first resistor. The absolute voltage provided can be set by adjusting the second resistor. | 03-24-2011 |
| 20110068426 | PHOTODIODES AND METHODS FOR FABRICATING PHOTODIODES - A photodiode includes an opening over an active photodiode region so that a top passivation layer and interlayer dielectric layers (ILDs) do not affect the spectral response of the photodiode. A dielectric reflective optical coating filter, which includes a plurality of dielectric layers, fills at least a portion of the opening and thereby covers the active photodiode region, to shape a spectral response of the photodiode. Alternatively, the dielectric reflective optical coating filter is formed prior to the opening, and the opening is formed by removing a top passivation coating and ILDs to expose the dielectric reflective optical coating filter. | 03-24-2011 |
| 20110068255 | PHOTODETECTORS USEFUL AS AMBIENT LIGHT SENSORS - A photodetector includes one or more first photodiode regions that are covered by an optical filter configured to reject infrared (IR) light and that produce a first current (I | 03-24-2011 |
| 20110063878 | POWER-SUPPLY CONTROLLER - An embodiment of a controller for a power supply includes circuitry that is operable to allow the power supply to operate as follows. During a first portion of a supply period, a first current flows through a first winding of the power supply, through a second winding of the power supply, and to an output node of the power supply. And during a second portion of the supply period, a second current flows through the first winding, through a third winding of the power supply, and to the output node. Each of the first, second, and third windings may be non-electrically isolated from one or more of the other windings during one or more portions of the supply period. Furthermore, the first, second, and third windings may be magnetically coupled to one another. For example, in an embodiment, such a controller may be part of a DC-DC converter that may be more efficient, and that may have reduced interdependence between output-signal ripple and transient response, than a conventional buck converter. | 03-17-2011 |
| 20110063149 | CALIBRATION OF OFFSET, GAIN AND PHASE ERRORS IN M-CHANNEL TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over N | 03-17-2011 |
| 20110062930 | VARYING OPERATION OF A VOLTAGE REGULATOR, AND COMPONENTS THEREOF, BASED UPON LOAD CONDITIONS - A method for operating a voltage regulator controller, for use in a voltage regulator including coupled inductors, is provided as follows. A first signal is generated for driving a first switch of the voltage regulator. A second signal is generated driving a first switch of the voltage regulator. The voltage regulator determines whether a light-load condition exists. Upon determining the existence of a light-load condition, adjusting the phase difference between said first and second signals so that the first and second signals are approximately in-phase. | 03-17-2011 |
| 20110062926 | SYSTEM AND METHOD FOR CONTROLLING A VOLTAGE SUPPLY - A system, voltage supply circuit, control unit for a voltage supply circuit, and method of controlling a voltage supply circuit are disclosed. For example, a system is disclosed that comprises at least one electronic circuit and a voltage supply unit coupled to an input of the at least one electronic circuit. The voltage supply unit includes a power unit to supply a voltage to the at least one electronic circuit and a control unit to control an operating mode of the power unit, an output of the control unit coupled to an input of the power unit. The control unit includes a mode selector to select the operating mode of the power unit, coupled to at least a first output of the power unit, an amplifier coupled to the at least a first output of the power unit, a compensation circuit, and a first switching unit coupled to the mode selector and the compensation circuit, to couple the compensation circuit to the amplifier if a selected operating mode of the power unit is a first mode. | 03-17-2011 |
| 20110043392 | SAMPLER LINEARITY BY SIMULTANEOUS DERIVATIVE SAMPLING - A circuit for improved sampler linearity, in an analog to digital converter, by taking simultaneous analog samples of an input signal V(t) and its derivative, dV/dt. The correction can be implemented as a memoryless non-linear model in the analog, digital, or mixed signal domains. Delay elements placed in the clock signal path or main input signal path can provide more precise control over the correction. | 02-24-2011 |
| 20110043281 | DYNAMICALLY ADJUSTABLE LOW NOISE, LOW POWER INSTRUMENTATION AMPLIFIER - A circuit in accordance with an embodiment of the present invention includes an instrumentation amplifier, a dynamically adjustable low pass filter, at least one monitor and a controller. The instrumentation amplifier includes a pair of buffered operational amplifiers that accept a pair of input signals, and a differential operational amplifier that outputs an output signal indicative of a difference between the pair of input signals. The dynamically adjustable low pass filter is configured to provide band limiting of the output signal at frequencies greater than a cutoff frequency. The monitor, or monitors, is/are configured to monitor a signal upstream of the instrumentation amplifier and/or a signal downstream of the instrumentation amplifier and output a monitor signal. The controller is configured to receive the monitor signal, or signals, and to dynamically adjust output voltage noise at frequencies greater than the crossover frequency of the multipath amplifiers and/or the cutoff frequency of the low pass filter based on the monitor signal, or signals. | 02-24-2011 |
| 20110043280 | LOW NOISE, LOW POWER INSTRUMENTATION AMPLIFIER - An instrumentation amplifier includes a pair of buffered operational amplifiers that accept a pair of input signals, and a differential operational amplifier that outputs an output signal indicative of a difference between the input signals. A low pass filter provides passive band limiting of the output signal. Each operational amplifier is implemented as a multi-path amplifier that includes a low frequency path and a high frequency path between an input and an output of the operational amplifier. Further, each multi-path amplifier includes a differential input transconductance stage within the low frequency path and a differential input transconductance stage within the high frequency path. Within each multi-path amplifier, the differential input transconductance stage of the high frequency path is noisier than, but consumes less power than, the differential input transconductance stage of the low frequency path. Each multi-path amplifier provides noise shaping that results in an increase in noise above a crossover frequency of the multi-path amplifier. | 02-24-2011 |
| 20110038286 | USING FREQUENCY DIVISIONAL MULTIPLEXING FOR A HIGH SPEED SERIALIZER/DESERIALIZER WITH BACK CHANNEL COMMUNICATION - A system comprising a first serializer/deserializer coupled to a first electronic device and a second serializer/deserializer couple to a second electronic device is provided. The first serializer/deserializer comprises a forward channel driver and the second serializer/deserializer comprises a reverse channel driver. A communication medium is coupled between the first and second serializer/deserializers, and the first and second serializer/deserializers are AC coupled to the communication medium to provide a high frequency forward channel and are DC coupled to the communication medium to provide a low frequency reverse channel. | 02-17-2011 |
| 20110038242 | HYBRID LASER DIODE DRIVERS THAT INCLUDE A STATE MACHINE - Provided herein are hybrid laser diode drivers (LDDs) that drive a laser diode in response to receiving enable signals from a controller. In accordance with specific embodiments, a hybrid LDD includes a read channel to selectively output a read current, one or more write channel each to selectively output a write current, and an oscillator channel to selectively output an oscillator current. Additionally, in specific embodiments the hybrid LDD includes a state machine that receives the enable signals from the controller, and based on the enable signals, controls timing of the currents output by the read, write and oscillator channels. | 02-17-2011 |
| 20110025540 | DATA LOOK AHEAD TO REDUCE POWER CONSUMPTION - Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Additionally, or alternatively, while the portions of the digital signal are being buffered, there can be a determination, based on the buffered portions of the digital signal, of when one or more system related parameters can be adjusted to temporarily reduce power dissipation. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa. Eventually, the portions of the digital signal are provided to the sub-system so that the sub-system can respond to the portions of the digital signal. | 02-03-2011 |
| 20110025217 | INRUSH CURRENT LIMITER FOR AN LED DRIVER - An inrush current limiter for use with an LED driver including a current limiting device, a bypass switch device, and a switch drive. The current limiting device is placed in the input current path of the LED driver to limit input current to a predetermined maximum level in response to an AC conductive angle modulated voltage. The bypass switch device is coupled in parallel with the current limit device. The switch drive turns on the bypass switch device to at least partially bypass the current limiting device as a voltage level of an input of a switching converter rises. The input current remains sufficiently high without exceeding the maximum level. The switch drive is implemented with a delay network driven either by a separate transformer winding or by a snubber network. The delay network may have a delay based on the delay caused by the current limiting device. | 02-03-2011 |
| 20110019522 | HYBRID LASER DIODE DRIVERS THAT INCLUDE A DECODER - Provided herein are hybrid laser diode drivers (LDDs) that drive a laser diode in response to receiving enable signals from a controller. In accordance with specific embodiments, a hybrid LDD includes a read channel to selectively output a read current, one or more write channel each to selectively output a write current, and an oscillator channel to selectively output an oscillator current. Additionally, in specific embodiments the hybrid LDD includes a decoder that receives the enable signals from the controller, and based on the enable signals, controls timing of the currents output by the read, write and oscillator channels. | 01-27-2011 |
| 20110019317 | TUNABLE VOLTAGE ISOLATION GROUND TO GROUND ESD CLAMP - A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached. | 01-27-2011 |
| 20110019316 | INRUSH CURRENT CONTROL - An inrush current control circuit selectively short-circuit bypasses an inrush current limiting resistor (R | 01-27-2011 |
| 20110018613 | SYSTEM AND METHOD FOR PRE-CHARGING A BOOT CAPACITOR IN A SWITCHING REGULATOR WITH HIGH PRE-BIAS VOLTAGE - An apparatus comprises a voltage regulator including an high side switching transistor and a low side switching transistor. An high side drive controls operation of the high side switching transistor. A low side driver controls operation of the low side switching transistor. A bootstrap capacitor provides an operating voltage to the high side switching driver. The bootstrap capacitor is charged to a predetermined level responsive to a supply voltage. A low side driver drives the low side switching transistor according to a process that charges the bootstrap capacitor to the predetermined level. The process turns on the low side switching transistor for a first predetermined number of cycles and turns off the low side switching transistor for a second predetermined number of cycles. The process is repeated for a predetermined number of times during startup of the voltage regulator when a prebias load is applied to the voltage regulator. | 01-27-2011 |
| 20110006934 | PROGRAMMABLE SEGMENTED DIGITAL-TO-ANALOG CONVERTER (DAC) - Provided herein are segmented digital to analog converters (DACs), methods for use therewith, and systems that include one or more such DACs. According to an embodiment, a DAC includes a plurality of sub-DACs, a DAC input adapted to receive a multi-bit digital input and a DAC output adapted to output an analog output current in response to and indicative of the digital input. Each sub-DAC is adapted to receive a separate reference current that specifies a transfer function of the sub-DAC. A magnitude of the reference current provided to each sub-DAC is separately programmable to thereby separately control a gain of each sub-DAC. | 01-13-2011 |
| 20110006188 | PROXIMITY SENSORS WITH IMPROVED AMBIENT LIGHT REJECTION - In accordance with an embodiment, a proximity sensor includes a driver, a photodiode (PD), an analog-to-digital converter (ADC) with analog-to-digital-to-analog (ADA) feedback, and a controller. The driver is adapted to selectively drive a light source. The photodiode (PD) is adapted to produce a photodiode current signal (Idiode) indicative of an intensity of light detected by the PD, where the light detected by the PD can include ambient light and/or light transmitted by the light source that was reflected off an object proximate the PD. The controller is adapted to control the driver and the ADC with ADA feedback. A digital output of the ADC with ADA feedback is indicative of a proximity of an object to the PD with at least a majority of the ambient light detected by the PD rejected. | 01-13-2011 |
| 20110001645 | RANDOMIZATION OF SAMPLE WINDOW IN CALIBRATION OF TIME-INTERLEAVED ANALOG TO DIGITAL CONVERTER - A technique that randomizes a sample window over which one or more interleave mismatch corrections are made to a time interleaved analog to digital converter (TIADC). | 01-06-2011 |
| 20110001644 | METER AND FREEZE OF CALIBRATION OF TIME-INTERLEAVED ANALOG TO DIGITAL CONVERTER - A technique for improving the operation of a Time Interleaved Analog to Digital Converter (TIADC) by suppressing updates and/or correction to updates of an interleave mismatch errors estimator when one or more predetermined conditions | 01-06-2011 |
| 20100327835 | INTEGRATOR FOR PROVIDING OVERSHOOT PROTECTION AND LIGHT SWITCHING MODE DURING NON-ZERO LOAD CONDITION FOR AN LED DRIVER CIRCUITRY - A voltage regulator system comprises circuitry for generating a regulated output voltage responsive to an input voltage and switching control signals. A voltage divider is connected to an output node of the circuitry to provide a way to monitor the output voltage. A voltage regulator controller generates the switching control signals responsive to the monitored output voltage and a reference voltage. A compensation network is associated with the voltage regulator controller. The voltage regulator controller further controls the circuitry for regulating an output current pulse for the regulated output voltage responsive to an indication that the monitored output voltage is below a reference voltage in the no-load condition without interaction with the loop compensation network. The voltage regulator controller further selectively associates the compensation network with the voltage regulator controller responsive to a load condition and selectively disconnects the compensation network from the voltage regulator controller responsive to a no-load condition. | 12-30-2010 |
| 20100327825 | SWITCHING REGULATOR CIRCUIT, SYSTEM, AND METHOD FOR PROVIDING INPUT CURRENT MEASUREMENT WITHOUT A DEDICATED INPUT CURRENT SENSE ELEMENT - A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current. | 12-30-2010 |
| 20100323487 | RADIATION HARDENED DEVICE - A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance. | 12-23-2010 |
| 20100321221 | SIGMA DELTA CONVERTER SYSTEM AND METHOD - A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer. | 12-23-2010 |
| 20100320983 | SYSTEM AND METHOD FOR PFM/PWM MODE TRANSITION WITHIN A MULTI-PHASE BUCK CONVERTER - A multi-phase voltage regulator comprises a plurality of DC/DC voltage regulators. Each of the DC/DC voltage regulators is associated with a particular phase of the multi-phase regulator. Each of the regulators comprises a first switching transistor connected between an input voltage node and a phase node responsive to switching control signals. A second switching transistor is connected between the phase node and a ground node and is responsive to the switching control signals. An inductor is connected between the phase node and an output voltage node. Control logic generates the switching control signals responsive to a pulse control signal. PFM/PWM transition logic generates the pulse control signal. The pulse control signal transitions between a PWM signal and a PFM signal responsive to an error voltage, a feedback voltage from the output voltage node and an inductor current through the inductor. An error amplifier generates the error voltage responsive to the feedback voltage and a reference voltage. The output of each error amplifier in each of the plurality of phases are connected to each other. A capacitor is connected between the output voltage node and a ground node. | 12-23-2010 |
| 20100320977 | PULSE ADDING SCHEME FOR SMOOTH PHASE DROPPING AT LIGHT LOAD CONDITIONS FOR MULTIPHASE VOLTAGE REGULATORS - A pulse control system for a multiphase regulator including an error amplifier, a multiphase generator, and an adaptive controller. The error amplifier provides an error signal indicative of output voltage error. The multiphase generator develops modulation pulses for phases based on the error signal. The adaptive controller is responsive to a load indication signal and redirects at least one modulation pulse from a first of phase to a second phase. The load indication signal may be received from a microprocessor indicating a low power mode. The adaptive controller provides a smooth and efficient transition to low load conditions by dropping operation of one or more phases and redirecting modulation pulses to the remaining one or more phases, and reduced phases improve power efficiency for the low load conditions. | 12-23-2010 |
| 20100320976 | DC-DC CONVERTERS HAVING IMPROVED CURRENT SENSING AND RELATED METHODS - A DC-DC converter includes a chip including an error amplifier and a pulse width modulator (PWM) having an input connected to an output of the error amplifier, and an inductor driven by said PWM in series with an output node (V | 12-23-2010 |
| 20100315847 | COMPONENT FAULT DETECTION FOR USE WITH A MULTI-PHASE DC-DC CONVERTER - Provided herein are circuits, systems and methods that monitor for a fault within a multi-phase DC-DC converter. This can include monitoring the channels of the DC-DC converter for way out of balance (WOB) conditions, and monitoring for a component fault in dependence on detected WOB conditions. A fault can be detected if, during a predetermined period of time, one of the WOB conditions occurs at least a specified amount of times more than another one of the WOB conditions. The DC-DC converter and/or another circuit can be shut-down in response to a fault being detected. Additionally, or alternatively, a component fault detection signal can be output in response to a fault being detected. | 12-16-2010 |
| 20100315059 | SYSTEM AND METHOD FOR CONTROLLING SYNCHRONOUS SWITCH FOR A SYNCHRONOUS CONVERTER - An apparatus comprises a synchronous converter for providing a regulated output voltage responsive to an input voltage, a control PWM signal to a control switch of the synchronous converter and a synchronous PWM signal to a synchronous switch of the synchronous converter. A first circuit generates the control PWM signal and the synchronous PWM signal responsive to a PWM control signal. The first circuit limits a maximum duty cycle of the synchronous PWM signal to a predetermined level. | 12-16-2010 |
| 20100315051 | WAY OUT OF BALANCE (WOB) CURRENT CORRECTION FOR USE WITH A MULTI-PHASE DC-DC CONVERTER - Provided herein are circuits, systems and methods that monitor for way out of balance (WOB) conditions within a multi-phase DC-DC converter, and adjust a balance between currents through channels of the DC-DC converter, in dependence on detected WOB conditions. | 12-16-2010 |
| 20100314708 | JUNCTION BARRIER SCHOTTKY DIODE - A junction barrier Schottky diode has an N-type well having a surface and a first peak impurity concentration; a P-type anode region in the surface of the well, and having a second peak impurity concentration; an N-type cathode contact region in the surface of the well and laterally spaced from a first wall of the anode region, and having a third peak impurity concentration; and a first N-type region in the surface of the well and laterally spaced from a second wall of the anode region, and having a fourth impurity concentration. The center of the spaced region between the first N-type region and the second wall of the anode region has a fifth peak impurity concentration. An ohmic contact is made to the anode region and cathode contact region, and a Schottky contact is made to the first N-type region. The first and fifth peak impurity concentrations are less than the fourth peak impurity concentration, and the fourth peak impurity concentration is less that the second and third peak impurity concentrations. | 12-16-2010 |
| 20100301940 | NEGATIVE CAPACITANCE SYNTHESIS FOR USE WITH DIFFERENTIAL CIRCUITS - Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit. | 12-02-2010 |
| 20100301826 | SYSTEM AND METHOD FOR ORING PHASES TO OVERCOME DUTY CYCLE LIMITATIONS IN A MULTI-PHASE BOOST CONVERTER - A multiphase boost converter includes a multiphase PWM controller for generating a plurality of PWM signals. A plurality of boost converters are each associated with a separate phase connected between an input voltage node and an output voltage node and generating an output voltage responsive to an input voltage and the plurality of PWM signals. Phase nodes of each of the plurality of boost converters are ORed to each other. | 12-02-2010 |
| 20100295510 | SYSTEM AND METHOD FOR CELL BALANCING AND CHARGING - An apparatus for charging a plurality of series connected battery cells includes first and second input terminals for providing a charging voltage to the plurality of series connected battery cells. A transformer includes a primary side associated with the charging voltage and a secondary side including a plurality of portions. Each of the plurality of portions connected across at least two of the plurality of series connected battery cells. A first switch in series between each of the plurality of portions of the secondary side and a first battery cell of the at least two of the plurality of series connected battery cells provides a charging current to the first battery cell during a first portion of a cycle of a current in the primary side of the transformer. A second switch in series between each of the plurality of portions of the secondary side and a second battery cell of the at least two of the plurality of series connected battery cells provides a charging current to the to the second battery cell during a second portion of the cycle of the current in the primary side of the transformer. | 11-25-2010 |
| 20100295509 | SYSTEM AND METHOD FOR CELL BALANCING AND CHARGING - An apparatus for charging a plurality of series connected battery cells, includes a first and second input terminals for providing a charging voltage to the plurality of series connected battery cell. A transformer includes a primary side associated with the charging voltage and a secondary side includes a plurality of portions. Each of the plurality of portions is connected across at least one of the plurality of series connected battery cell. A switch in series between each of the plurality of portions of the secondary side and the at least one of the plurality of series connected battery cells increases an impedance between the portion of the secondary side and the associated one of the plurality of series connected battery cells in a first state and decreases the impedance between the portion of the secondary side and the associated one of the plurality of series connected battery cells in a second state. | 11-25-2010 |
| 20100284452 | CAPACITIVE DIVIDER TRANSMISSION SCHEME FOR IMPROVED COMMUNICATIONS ISOLATION - A communication system comprising a first and second transceiver is provided. The first transceiver has a first and second port coupled to a communication medium, wherein a first differential capacitor couples the first and second ports together. The second transceiver has a third and fourth port each AC coupled to the communication medium, wherein a second differential capacitor couples the third and fourth ports together. | 11-11-2010 |
| 20100284203 | CONTROL MODE FOR ZVS CONVERTER AT RESONANT OPERATING FREQUENCIES - A zero volt switching voltage converter comprises a switching network including a plurality of switches for generating control signals responsive to an input voltage source and switching control signals. Circuitry generates a regulated output voltage responsive to the control current. Control circuitry generates the switching control signals wherein the switching control signals operate the plurality of switches at a resonant frequency of the zero volt switching voltage converter. | 11-11-2010 |
| 20100283523 | CONTROLLER AND DRIVER COMMUNICATION FOR SWITCHING REGULATORS - Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three ( | 11-11-2010 |
| 20100281320 | METHOD FOR ACCURACY IMPROVEMENT ALLOWING CHIP-BY-CHIP MEASUREMENT CORRECTION - A method for allowing measurement corrections on a chip-by-chip basis. Error correction values are generated responsive to the input value to a circuit of the calibrated integrated circuit chip and to a measured value from the circuit of the calibrated integrated circuit chip. The error correction values are stored within an error correction table within a nonvolatile memory of the integrated circuit chip. | 11-04-2010 |
| 20100277075 | LONG RANGE PROXIMITY AND/OR MOTION DETECTOR WITH AMBIENT LIGHT DETECTION CAPABILITIES - Provided herein are optical sensor systems that can be used for ambient light detection, proximity detection and motion detection, as well as to larger systems that include such an optical sensor system, and to related methods. In an embodiment, the optical sensor system includes a front end, an ambient light channel, a proximity channel and a motion channel. In an embodiment, offset and gain of the proximity channel is adjusted based on motion detected by the motion channel. | 11-04-2010 |
| 20100270995 | SYSTEM AND METHOD FOR DETERMINING OUTPUT VOLTAGE LEVEL INFORMATION FROM PHASE VOLTAGE FOR SWITCHED MODE REGULATOR CONTROLLERS - A controller integrated circuit for a switched mode regulator which converts an input voltage to an output voltage. The controller includes a phase pin, a modulation circuit and a filter. The modulation circuit is configured to regulate the output voltage using the input voltage and output voltage level information. The filter has an input coupled to the phase pin and an output providing the output voltage level information which approximates the output voltage based on phase pin voltage. Various filters are contemplated, including passive and active low pass filters and the like. A regulator using such a controller is disclosed. A method of determining a voltage level of an output voltage includes receiving a phase voltage from a phase pin coupled to the phase node, and filtering the phase voltage to provide an output sense voltage having a voltage level approximating the voltage level of the output voltage. | 10-28-2010 |
| 20100264895 | POWER-SUPPLY CONTROLLER - An embodiment of a power-supply controller includes a signal combiner and a control circuit. The signal combiner is operable to generate a combined feedback signal from sense and output feedback signals that are respectively derived from a sense signal and a regulated output signal, and the signal combiner is operable to receive the sense signal from a sense circuit that is operable to generate the sense signal while a current is flowing through an inductor and while a switch that is disposed between the inductor and an input voltage has a first state. The sense signal generated by the sense circuit is related to the current, and the switch and the inductor are operable to generate the regulated output signal. The control circuit is coupled to the signal combiner and is operable to cause the switch to have a second state for a predetermined time in response to the combined feedback signal having a predetermined relationship to a reference signal. | 10-21-2010 |
| 20100261344 | ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES - A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad. | 10-14-2010 |
| 20100259766 | OPTICAL SENSORS AND METHODS FOR PROVIDING OPTICAL SENSORS - Provided herein are optical sensor devices, methods for making the same, and systems including the same. An optical sensor device, according to an embodiment, includes a light detector die and a light source die attached to the same or different die attachment substrates so that there is a space between the light source die and the light detector die. A light transmissive material covers the light detector die, the light source die and at least a portion of the space between the light detector die and the light source die. A groove is formed (e.g., saw, blade or laser cut, or cast) in the light transmissive material between the light detector die and the light source die, and an opaque material is put within the groove to provide a light barrier between the light detector die and the light source die. | 10-14-2010 |
| 20100259279 | SYSTEM AND METHOD FOR USING AN INTEGRATED CIRCUIT PIN AS BOTH A CURRENT LIMITING INPUT AND AN OPEN-DRAIN OUTPUT - An integrated circuit comprises at least one pin and has at least one resistor connected between a reference voltage and the at least one pin. Current measurement circuitry applies a voltage across the at least one resistor and measures a current at the at least one pin responsive to the applied voltage in a first mode of operation. The measured current enables determination of a current limit set point for the integrated circuit. In a second mode of operation, the at least one resistor comprises a pull up resistor and the at least one pin that is connected to the at least one resistor comprises an open-drain output. | 10-14-2010 |
| 20100258712 | OPTICAL SENSORS THAT REDUCE SPECTRAL REFLECTIONS - An optical sensor device comprises a light source, a light detector, and an opaque light barrier including a first portion to block light from being transmitted directly from the source to the detector. A second portion of the light barrier extends from the first portion in a direction towards the light source, such that a portion of the second portion covers at least a portion of light emitting element(s) of the source, to reduce an amount of specular reflections, if a light transmissive cover plate were placed over the sensor. Additionally, a third portion of the barrier can extend from the first portion, in a direction towards to the detector, such that a portion of the third portion covers at least a portion of light detecting element(s) of the detector, to reduce an amount of specular reflections that would be detected by the detecting element(s) of the detector, if a light transmissive cover plate were placed over the sensor. Additionally, an off-centered lens can cover a portion of the light source. | 10-14-2010 |
| 20100258710 | OPTICAL SENSORS THAT REDUCE SPECTRAL REFLECTIONS - An optical sensor device, according to an embodiment of the present invention, includes a light source and a light detector. The light source includes one or more light emitting elements, and the light detector includes one or more light detecting elements. A first opaque light barrier portion, between the light source and the light detector, is configured to block light from being transmitted directly from the light source to the light detector. A second opaque light barrier portion, extending from the first opaque light barrier portion in a direction towards the light source, is configured to reduce an amount of specular reflections that would occur if a light transmissive cover plate were placed over the optical sensor device. A third opaque light barrier portion, extending from the first light barrier portion in a direction towards to the light detector, is configured to reduce an amount of specular reflections that would be detected by the light detector, if a light transmissive cover plate were placed over the optical sensor device. | 10-14-2010 |
| 20100252871 | LIGHT SENSORS WITH INFRARED SUPPRESSION - Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors. | 10-07-2010 |
| 20100245145 | UN-BUFFERED SEGMENTED R-DAC WITH SWITCH CURRENT REDUCTION - An resistor string digital-to-analog converter (DAC) that includes elements to compensate for resistor ladder loading, and/or to provide compensation for loading such as via switch current cancellation. The approach reduces output voltage sensitivity to switch resistances while also reducing INL and DNL errors. Additional resistor loops are optionally disposed at the top and bottom of one or more further segments to provide N | 09-30-2010 |
| 20100244799 | SYSTEM AND METHOD FOR PHASE DROPPING AND ADDING - A multi-phase voltage regulator comprisies a plurality of current supplying stages, each current supplying stage configured to supply a local output current equaling at least a portion of a load current output from the multi-phase voltage regulator; and a plurality of control circuits, each control circuit coupled to a respective one of the plurality of current supplying stages, wherein each control circuit calculates a control signal based, at least in part, on a sampled current representative of the respective local output current and a sampled current representative of a master output current. The control signal from each control circuit causes the respective current supplying stage to be disabled gradually over a first time interval if the sum of the local output current and the master output current is detected as being below a respective first predetermined level. | 09-30-2010 |
| 20100207661 | BI-DIRECTIONAL BUFFER FOR OPEN-DRAIN OR OPEN-COLLECTOR BUS - Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node. | 08-19-2010 |
| 20100201405 | DYNAMIC PHASE TIMING CONTROL FOR MULTIPLE REGULATORS OR PHASES - A drive control circuit generates switching drive signals for a single phase of a multiphase voltage regulator. A driver circuitry generates the switching drive signals for the voltage regulator responsive to a clock signal. A clock circuitry generates the clock signal responsive to a monitored external clock signal. A phase number detector determines a number of active phases in the multiphase voltage regulator in real time responsive to an indicator on a phase number input monitored by the phase detector. | 08-12-2010 |
| 20100191383 | CONNECTION SYSTEMS AND METHODS FOR SOLAR CELLS - Exemplary embodiments provide an array of solar power generation devices, and method for forming the array. Each solar power generation device can be defined as a cell, a group of cells, a panel subarray, a panel from an array of panels, etc. The solar power generation device can include a controller which can address and control each solar power generation device individually. A test method and fixture is also described, which can be used to program the controller such that incorrect assembly of the array during manufacture is overcome. | 07-29-2010 |
| 20100177625 | DYNAMICALLY CONFIGURABLE MULTIPLE WAVELENGTH PHOTODETECTOR ARRAY FOR OPTICAL STORAGE APPLICATIONS - A photodetector integrated circuit (PDIC) capable of being used with at least two different types of optical discs includes a photodetector (PD) array and a switch matrix. The PD array includes a center channel PD and a side channel PD electrically isolated from the center channel PD. The switch matrix, which includes a plurality of inputs and a plurality of outputs, can be selectively configured in a plurality of different switch configurations. The side channel PD includes a plurality of electrically isolated PD sections. Each electrically isolated PD section of the side channel PD is adapted to detect light and provide an electrical output signal, indicative of the light detected by the PD section, to a different one of the inputs of the switch matrix. The switch matrix is adapted to combine the electrical output signals provided by the electrically isolated PD sections of the side channel PD in a plurality of different manners, in dependence on which of the plurality of different switch configurations is selected. | 07-15-2010 |
| 20100171645 | N-BIT ADC READER - An integrated circuit including a single input pin for determining a value associated with a resistor divider. The circuit includes first circuitry for determining a resistor ratio of the resistor divider through the single input pin. A first register stores a first group of bits representing the resistor ratio. The first group of bits comprises the least significant bits of the value. Second circuitry determines an equivalent resistance of the resistor divider through the single input pin. A second register stores a second group of bits representing the equivalent resistance. The second group of bits comprises the most significant bits of the value associated with the resistor divider. | 07-08-2010 |
| 20100149879 | FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells. | 06-17-2010 |
| 20100141225 | ACTIVE PULSE POSITIONING MODULATOR - An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals. | 06-10-2010 |
| 20100129975 | BASE FOR A NPN BIPOLAR TRANSISTOR - An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance. | 05-27-2010 |
| 20100127684 | CURRENT SENSE CASCODE AMPLIFIER - A current sense amplifier sensing current through a main switch of a converter. The amplifier includes first and second switch devices, an amplifier control circuit, a bias circuit, a current generator circuit, and a sense circuit. The main switch is coupled to an input, phase and control nodes. The first and second switch devices are smaller matching versions of the main switch and are both coupled to the main switch and form first and second nodes. The bias circuit is coupled between second and fourth nodes and the amplifier control circuit is coupled between first and third nodes. The current generator develops a first current through the amplifier control circuit and a second current through the bias circuit. The sense circuit has a current path coupled to the first node and is controlled by the third node to develop a sense voltage indicative of current through the main switch. | 05-27-2010 |
| 20100127680 | PWM VOLTAGE CONVERTER WITH TRANSIENT AND PERMANENT FAULT IMMUNITY THROUGH REDUNDANCY AND FEEDBACK ADJUSTMENT - A pulse-width modulated (PWM) DC-DC converter has a multitude of redundant channels supplying PWM signals to a voter whose output voltage controls the regulated DC output voltage. To ensure that single transient events, single permanent faults, or mismatches in the electrical characteristics of the various components disposed in the redundant channels do not adversely affect the regulated DC output voltage, transitions of the PWM signal in each channel are compared to the corresponding transitions of the voter's output signal. If a PWM signal transition of a redundant channel is detected as occurring relatively earlier/later than the corresponding transition of the voter's output signal, the width of the PWM signal is increased/decreased. If a PWM signal transition of a redundant channel is detected as occurring within a predefined window of the corresponding transition of the voter's output signal, the width of the PWM signal is not changed. | 05-27-2010 |
| 20100127679 | FAULT TOLERANT REDUNDANT CLOCK CIRCUIT - A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives. | 05-27-2010 |
| 20100117883 | Cable Gateway Using A Charge-Domain Pipeline Analog to Digital Converter - A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages. | 05-13-2010 |
| 20100117198 | INTEGRATED PROCESS FOR THIN FILM RESISTORS WITH SILICIDES - The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed. | 05-13-2010 |
| 20100110299 | SYSTEMS AND METHODS FOR CABLE EQUALIZATION - Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels. | 05-06-2010 |
| 20100110288 | CABLE EQUALIZATION LOCKING - Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels. The compensating is selectively locked and reset in response to specific conditions being detected, e.g., a locking condition and a reset condition. | 05-06-2010 |
| 20100109631 | TUNABLE VOLTAGE ISOLATION GROUND TO GROUND ESD CLAMP - A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached. | 05-06-2010 |
| 20100102791 | AUXILIARY TURN-ON MECHANISMS FOR REDUCING CONDUCTION LOSS IN BODY-DIODE OF LOW SIDE MOSFET OF COUPLED-INDUCTOR DC-DC CONVERTER - An embodiment of a power-supply controller includes first and second circuits. The first circuit is operable to cause a first current to flow through a first phase of a power supply. And the second circuit is operable to cause the second phase of the power supply to operate in a reduced-power-dissipation mode for at least a portion of a time period during which a second current magnetically induced by the first current flows through the second phase. | 04-29-2010 |
| 20100085029 | ADVANCED SLOPE INJECTION FOR INPUT CURRENT LIMITING OF SWITCH-MODE DC/DC CONVERTER - A DC/DC converter comprising voltage conversion circuitry for generating a regulated output voltage responsive to an input current and at least one switching control signal. A current control loop generates the at least one switching control signal to limit an input current responsive to the input current, a reference voltage and a slope signal injected with the reference voltage. | 04-08-2010 |
| 20100085028 | SYSTEM AND METHOD FOR PROVIDING LINEAR BUCK BOOST TRANSITIONS WITHIN A BUCK BOOST CONVERTER - A voltage regulator, comprises first circuitry for generating an output voltage responsive to an input voltage and a plurality of switching control signal. Switching control circuitry generates the switching control signals responsive to the output voltage and at least one of a buck ramp signal and a boost ramp signal. Voltage ramp generation circuitry generates each of the buck ramp signal and the boost ramp signal. The boost ramp signal comprises the buck ramp signal offset by the peak value of the buck ramp signal. | 04-08-2010 |
| 20100085027 | SYSTEM AND METHOD FOR PROVIDING LINEAR BUCK BOOST TRANSITIONS WITHIN A BUCK BOOST CONVERTER - A voltage regulator, comprising first circuitry for generating an output voltage responsive to an input voltage and a plurality of switching control signal. Switching control circuitry generates the switching control signals responsive to the output voltage and at least one of a buck ramp signal and a boost ramp signal. Voltage ramp generation circuitry generates each of the buck ramp signal and the boost ramp signal. The boost ramp signal comprises the buck ramp signal offset by the peak value of the buck ramp signal. | 04-08-2010 |
| 20100085024 | POWER SUPPLY CONTROLLER WITH DIFFERENT STEADY STATE AND TRANSIENT RESPONSE CHARACTERISTICS - An embodiment of a power-supply controller includes a control circuit and a detection circuit. The control circuit has a signal characteristic, and is operable in response to a regulated output signal and a reference signal to cause at least one power-supply phase to generate the regulated output signal. The detection circuit is operable to detect a change in the regulated output signal, and to alter the signal characteristic of the control circuit in response to the detected change. | 04-08-2010 |
| 20100079175 | PHASE DOUBLER - A phase doubler driver circuit includes a first input for receiving a input PWM drive signal. First control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to the input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal. Second control logic adds an offset to a falling edge of the first output PWM drive signal responsive to a difference between a first current associated with the first phase current and an average current and for adding the offset to a falling edge of the second output PWM signal responsive to a difference between a second current associated with the second phase current and the average current, wherein the average current comprises the average of the first current and the second current. Drive circuitry generates drive signals responsive to each of the first output PWM drive signal and the second output PWM drive signal. | 04-01-2010 |
| 20100074070 | CONFIGURABLE PHOTO DETECTOR CIRCUIT - A configurable photo detector circuit comprises a photo detector array including a plurality of photo detectors coupled to a plurality of amplifiers. A method for programming a detection pattern of the configurable photo detector circuit comprises selecting a first detection pattern for the photo detector array, generating first signals to create the first selected detection pattern, and applying the first generated signals to the photo detector circuit to implement the first selected detection pattern. | 03-25-2010 |
| 20100073037 | OUTPUT IMPEDANCE CONTROL CIRCUIT - An external resistive element is used to provide a substantially constant output impedance for multiple drivers disposed on an IC. The drivers may operate at different supply voltages. Accordingly, the parameters which depend on the driver output impedance, such as rise/fall time, propagation delay, and the like are made substantially constant and independent of the semiconductor process variations, operating supply voltages, and the temperature. The substantially constant output impedance maintains the stability of the crossing point of a true and its complementary clock signal in high-speed applications, such as in the drivers used in charge-coupled devices. A number of feedback loops are used together with the external resistive element to achieve the substantially constant output impedance. The feedback loops compensate for the ageing effects, temperature gradients and changes in the operating conditions of the IC. | 03-25-2010 |
| 20100072964 | VOLTAGE REGULATOR INCLUDING CONSTANT LOOP GAIN CONTROL - A voltage regulation circuit includes a power stage for generating a regulated output voltage responsive to an input voltage and at least one PWM signal. A voltage divider circuit is connected to the output of the power stage and generates a feedback voltage. First circuitry generates the at least one PWM signal responsive to a voltage error signal, a filtered output voltage signal and a ramp voltage signal. The filtered output voltage is used for substantially removing loop gain change caused by the voltage divider circuit. A voltage compensation circuit generates the voltage error signal responsive to a feedback voltage and a reference voltage. | 03-25-2010 |
| 20100066448 | DEVICE UNDER TEST POWER SUPPLY - A power supply with and input and output includes an amplifier configured to set an output voltage of the power supply output equal to a fixed input voltage for the power supply. The power supply has a first output stage coupled to the amplifier and configured to source and sink current at the output of the power supply between a first voltage rail and a third voltage rail. The power supply has a second output stage coupled to the amplifier and configured to source and sink current to the output of the power supply between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages. | 03-18-2010 |
| 20100066338 | VOLTAGE REGULATOR INCLUDING QUASI TRANSITION DIODE EMULATION MODE OF OPERATION - A voltage regulator includes an upper switching transistor connected between an input voltage node and a phase node. A lower switching transistor is connected between the phase node and ground. An output filter is connected between the phase node and an output voltage node. A PWM control circuit generates an PWM control signal responsive to a feedback voltage. An upper gate control circuit controls operation of the upper switching transistor responsive to the PWM control signal. A lower gate control circuit controls operation of the lower switching transistor responsive to the PWM control signal and a ramp voltage signal. The lower gate control circuit linearly increases a lower gate control signal from 0 to (1-D), where D=the duty cycle, to transition the voltage regulator for diode emulation mode of operation to synchronous mode of operation responsive to a first pulse in the PWM control signal. | 03-18-2010 |
| 20100066323 | SYSTEM AND METHOD FOR PROVIDING PULSE FREQUENCY MODULATION MODE - A voltage regulator comprises switching circuitry for generating a phase voltage at a phase node responsive to an input voltage and switching control signals. An inductor is connected to the phase node and an output voltage node. A capacitor is connected between the output voltage node and ground. An error amplifier generates an error voltage responsive to an output voltage from the output voltage node and a reference voltage. Switching control circuitry generates switching control signals to the switching circuitry responsive to the error voltage, a ramp voltage and an established voltage level. The switching control circuitry operates the voltage regulator in a pulse frequency modulation mode of operation after sampling the error voltage and setting the established voltage level and exits the pulse frequency modulation mode of operation when the error voltage falls below the established voltage level. | 03-18-2010 |
| 20100066319 | ADVANCED PHASE NUMBER CONTROL FOR MULTIPHASE CONVERTERS - A control circuit for generating a control signal to add phases to a multiphase voltage regulator. The control circuit includes an input for receiving an error correction voltage from an error amplifier of the multiphase voltage regulator and at least one output for providing a PWM control signal. Control circuitry generates at least one PWM control signal to add a phase to the multiphase voltage regulator responsive to a determination that the error correction voltage has exceeded a threshold level. | 03-18-2010 |
| 20100052620 | BATTERY CHARGER IC INCLUDING BUILT-IN USB DETECTION - A charging circuit included on a single integrated circuit including first circuitry for generating a charging current responsive to an input voltage source. The input voltage source may comprise a USB voltage source or a non-USB voltage source. A USB detection circuit determines whether the input voltage source comprises the USB voltage source or the non-USB voltage source. | 03-04-2010 |
| 20100052611 | SWITCHING REGULATOR INPUT CURRENT SENSING CIRCUIT, SYSTEM, AND METHOD - A Buck switching regulator includes first Buck switching regulator circuitry is operable to generate a first output voltage from an input voltage and operable to generate a first sensed voltage having a value that is proportional to an output current being provided by the first Buck switching regulator circuitry. The first Buck switching regulator circuitry receives an input current and operates at a first duty cycle determined by a duty cycle signal. Input current sensing circuitry includes second Buck switching regulator circuitry coupled to the first Buck regulator switching circuitry to receive the duty cycle signal and to receive the first sensed voltage as an input voltage to the second Buck switching regulator circuitry. The second Buck switching regulator circuitry is operable responsive to the duty cycle signal to generate a second output voltage from the first sensed voltage. The second output voltage has a value that is proportional to the input current being supplied to the first Buck switching regulator circuitry. Such a Buck switching regulator can be utilized in a variety of different types of electronic systems, such as laptop computer systems, and can also be used in charging systems in laptop computer and other types of electronic systems. | 03-04-2010 |
| 20100048156 | NOISE CANCELLATION FOR ANTENNA MODULE - An antenna module with a detector and an associated canceller is disclosed. The detector may also detect interference and spurs. In one embodiment, an antenna module can include: an antenna configured to receive an electromagnetic signal in a signal path; an amplifier configured to amplify the received electromagnetic signal, and to provide the amplified signal at a first node; a filter configured to receive the amplified signal from the first node, and to provide a filtered signal output therefrom; and a noise canceller and a detector integrated in the signal path at the first node. | 02-25-2010 |
| 20100039085 | BUCK BOOST FUNCTION BASED ON A CAPACITOR BOOTSTRAP INPUT BUCK CONVERTER - A buck boost voltage converter circuit, comprises a capacitor pump circuit for boosting an input voltage in a first mode of operation when an input voltage is below a desired voltage level. A buck converter circuit provides the output voltage responsive to the boosted input voltage from the capacitor pump circuit in the first mode of operation and provides the output voltage responsive to the input voltage in a second mode of operation when the input voltage is above the desired voltage level. | 02-18-2010 |
| 20100038726 | RADIATION HARDENED DEVICE - A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance. | 02-18-2010 |
| 20100033153 | PWM CLOCK GENERATION SYSTEM AND METHOD TO IMPROVE TRANSIENT RESPONSE OF A VOLTAGE REGULATOR - A pulse control clock generator for a voltage regulator including a comparator, a window circuit, a filter circuit, a ramp circuit, and a current circuit. The comparator compares a ramp voltage with a compensation voltage and provides a corresponding pulse control signal. The compensation voltage is indicative of output voltage error. The window circuit adds a window voltage to the compensation voltage to provide a hysteretic voltage. The filter circuit filters the hysteretic voltage to provide a filtered hysteretic voltage, such that a difference between the compensation voltage and the filtered hysteretic voltage is reduced in response to a load increase. The ramp circuit provides a repetitive ramp voltage which ramps between the filtered hysteretic voltage and the compensation voltage based on the pulse control signal. The current circuit increases a slope of the ramp voltage in response to the load increase. | 02-11-2010 |
| 20100026263 | BUCK CONTROLLER HAVING INTEGRATED BOOST CONTROL AND DRIVER - An integrated circuit controller for controlling the operation of a voltage converter which includes a first comparator for comparing a voltage associated with an input of a boost converter with a threshold voltage and generating a control signal in response thereto. A second comparator compares a second voltage associated with an output of the boost converter with the threshold voltage and generates a second control signal in response thereto. Driver circuitry generates a first switching transistor drive signal and a second switching transistor drive signal. The first switching transistor drive signal is used for driving an upper gate switching transistor of a buck converter. The second switching transistor drive signal may be configured in a first mode of operation to drive a lower gate switching transistor of the buck converter and may be configured in a second mode of operation to drive a switching transistor of the boost converter. Control logic enables/disables at least a portion of the driver circuitry responsive to the control signal and the second control signal. | 02-04-2010 |
| 20100019748 | SYSTEM AND METHOD FOR REDUCING VOLTAGE OVERSHOOT DURING LOAD RELEASE WITHIN A BUCK REGULATOR - A buck regulator comprises an upper switching transistor connected between a voltage input node and a phase node. A lower switching transistor is connected between the phase node and a ground node. An inductor is connected between the phase node and an output voltage node. Circuitry generates control signals to the upper switching transistor and the lower switching transistor responsive to the output voltage and a reference voltage. The control signals to the lower switching transistor selectively turn off the lower switching transistor responsive to a current direction through the lower switching transistor and an indication of whether a voltage error signal has been clamped at a selected level. | 01-28-2010 |
| 20100013412 | TRANSIENT SUPPRESSION FOR BOOST REGULATOR - A circuit for generating an output voltage to a top node of a plurality of LED strings. The circuit includes an inductor having a load current flowing therethrough and a switching transistor responsive to a switching control signal. An integrator generates a compensation voltage responsive to a voltage at a bottom node of the LED string and a reference voltage. Circuitry for combining an offset with the compensation voltage is responsive to the compensation voltage and the load current through the inductor. The offset is generated only during a step load change of the load current and substantially reduces voltage transients from the compensation voltage and the output voltage. A summation circuit sums the compensation voltage including the offset with at least the voltage at the bottom node of the LED string to generate a first control signal. A latch generates the switching control signal responsive to the first control signal and a leading edge blanking signal. | 01-21-2010 |
| 20100013395 | DYNAMIC HEADROOM CONTROL FOR LCD DRIVER - An LED driver controller comprises a voltage regulator for controlling an output voltage to a top of a plurality of LED strings responsive to at least a reference voltage. A plurality of first circuitries each associated with a node at a bottom of each of the plurality of LED strings compares a voltage at the bottom of each of the plurality of LED strings with a high reference voltage and a low reference voltage. Control logic generates a first control signal when the voltage at the bottom of each node of the plurality of LED strings exceeds the high reference voltage and generates a second control signal when the voltage at least one of node of the plurality of LED strings falls below the low reference voltage. Second circuitry responsive to the first control signal and the second control signal generates the reference voltage. The reference voltage is controlled to cause the voltage at the bottom of the lowest voltage node of the plurality of LED strings to remain between the high reference voltage and the low reference voltage. | 01-21-2010 |
