INTERNATIONAL RECTIFIER CORPORATION Patent applications |
Patent application number | Title | Published |
20160105984 | Power Unit with Conductive Slats - In one implementation, a power unit for plugging into a mother board includes a power module situated on a substrate. The substrate is situated on conductive slats, each having an extended end away from the power module. Each of the conductive slats provides a mounting contact of the power unit. Each mounting contact is electrically coupled to the power module by electrical routing in the substrate. The mounting contacts are configured to provide electrical connection between the power module and the mother board. | 04-14-2016 |
20160105983 | Insertable Power Unit with Mounting Contacts for Plugging into a Mother Board - In one implementation, an insertable power unit for plugging into a mother board includes a power module situated on a substrate, and a mounting contact on an extended side of the substrate away from the power module. The mounting contact is electrically coupled to the power module by electrical routing in the substrate. The mounting contact is configured to provide electrical connection between the power module and the mother board. | 04-14-2016 |
20160104697 | Compact High-Voltage Semiconductor Package - There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package. | 04-14-2016 |
20160087422 | Fault and Short-Circuit Protected Output Driver - A driver and protection circuit for driving a power switch is disclosed. The driver and protection circuit includes a fault detection block configured to detect a discrepancy between a reference drive signal and a measured voltage at a gate of the power switch. The driver and protection circuit also includes a short circuit detection block configured to detect a gate-to-source short circuit or a gate-to-drain short circuit of the power switch. The driver and protection circuit further includes a latch coupled to the fault detection block and the short circuit detection block to selectively turn off an output driver coupled to the gate of the power switch when a fault or a short circuit is detected, and wherein the latch is configured to send a diagnostic signal when the fault or the short circuit is detected. | 03-24-2016 |
20160005845 | Group III-V Transistor Utilizing a Substrate Having a Dielectrically-Filled Region - There are disclosed herein various implementations of a group III-V transistor utilizing a substrate having a dielectrically-filled region. A semiconductor structure providing such a group III-V transistor includes a group IV substrate having the dielectrically-filled region, and a group III-V body situated over a top surface of the group IV substrate. The group III-V body includes a group III-V transistor having a top drain electrode, a top gate electrode, and a top source electrode. The group III-V transistor is situated substantially over the dielectrically-filled region of the substrate so as to increase a breakdown voltage of the group III-V transistor, and to also reduce an R | 01-07-2016 |
20160005821 | Group III-V Lateral Transistor with Backside Contact - There are disclosed herein various implementations of a group III-V transistor with a voltage controlled substrate. A semiconductor structure providing such a group III-V transistor includes a group IV substrate having a dielectrically-filled region, and a group III-V body situated over a top surface of the group IV substrate. The group III-V body includes a group III-V transistor having a top drain electrode, a top gate electrode, and a top source electrode. The semiconductor structure also includes a source-side via extending through the group III-V body to couple the top source electrode to a source-side region of the group IV substrate. The source-side region of the group IV substrate is further coupled to a bottom source contact situated under a bottom surface of the group IV substrate. | 01-07-2016 |
20160005816 | Group III-V Transistor with Voltage Controlled Substrate - There are disclosed herein various implementations of a group III-V transistor with a voltage controlled substrate. A semiconductor structure providing such a group III-V transistor includes a group IV substrate having a dielectrically-filled region, and a group III-V body situated over a top surface of the group IV substrate. The group III-V body includes a group III-V transistor having a top drain electrode, a top gate electrode, and a top source electrode. The semiconductor structure also includes a source-side via extending through the group III-V body to couple the top source electrode to a source-side region of the group IV substrate so as to reduce an R | 01-07-2016 |
20150371986 | Group III-V HEMT Having a Selectably Floating Substrate - There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a selectably floating substrate. Such a group III-V HEMT is situated over a substrate, and includes a transistor configured to selectably couple the substrate to ground and to selectably decouple the substrate from ground. The transistor is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state. | 12-24-2015 |
20150371982 | Composite Group III-V and Group IV Transistor Having a Switched Substrate - There are disclosed herein various implementations of a group III-V composite transistor having a switched substrate. Such a group III-V composite transistor includes a composite field-effect transistor (FET) including a depletion mode group III-V high electron mobility transistor (HEMT) situated over a substrate. The depletion mode group III-V HEMT is cascoded with an enhancement mode group IV FET to produce the composite FET. The group III-V composite transistor also includes a transistor configured to selectably couple the substrate of the depletion mode group III-V HEMT to ground and to selectably decouple the substrate from ground. That transistor is configured to ground the substrate when the depletion mode group III-V HEMT is in an off-state and to cause the substrate to float when the depletion mode group III-V HEMT is in an on-state. | 12-24-2015 |
20150348884 | Power Semiconductor Package with Multi-Section Conductive Carrier - In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed. The power semiconductor package according to the present disclosure results in effective thermal protection, current carrying capability, and a relatively small size. | 12-03-2015 |
20150340483 | Group III-V Device Including a Shield Plate - There are disclosed herein various implementations of a group III-V device including a shield plate. Such a group III-V device includes a substrate, a transition body situated over the substrate, a device channel layer situated over the transition body, and a device barrier layer situated over the device channel layer and producing a device two-dimensional electron gas (2-DEG). The group III-V device also includes a drain electrode coupled to the device barrier layer, and a shield plate, which may be coupled to the drain electrode or may be a floating shield plate. The shield plate is configured to substantially shield the device 2-DEG from charge centers situated over the device barrier layer. | 11-26-2015 |
20150311145 | Semiconductor Package with Switch Node Integrated Heat Spreader - In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier. | 10-29-2015 |
20150270249 | Semiconductor Package with Via-Coupled Power Transistors - In one implementation, a semiconductor package includes a carrier including first and second conductive segments, and first and second transistors attached respectively to the first and second conductive segments. The semiconductor package also includes a dielectric material formed in exposed portions of the first and second conductive segments, a first via extending through the dielectric material to the first conductive segment, and a second via extending through the dielectric material to the second conductive segment. A solder material fills each of the vias, the solder material protruding beyond the dielectric material and configured to electrically, thermally, and mechanically connect the carrier to a mounting surface for the semiconductor package. | 09-24-2015 |
20150228610 | Semiconductor Package Including a Power Stage and Integrated Output Inductor - In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage stacked over the integrated output inductor, the power stage including a pulse-width modulation (PWM) control and driver coupled to a control transistor and a sync transistor. | 08-13-2015 |
20150207495 | Power Converter with Split Voltage Supply - A power converter driver that is supplied with two different voltages. | 07-23-2015 |
20150194369 | Semiconductor Package with Conductive Clips - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadfirame and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-09-2015 |
20150162832 | Group III-V Voltage Converter with Monolithically Integrated Level Shifter, High Side Driver, and High Side Power Switch - There are disclosed herein various implementations of a monolithically integrated high side block. Such a monolithically integrated high side block includes a level shifter, a high side driver coupled to the level shifter, and a high side power switch coupled to the high side driver. The high side power switch is monolithically integrated with the high side driver and the level shifter on a common die. Each of the level shifter, the high side driver, and the high side power switch includes at least one group III-V device. | 06-11-2015 |
20150162321 | Composite Power Device with ESD Protection Clamp - There are disclosed herein various implementations of a normally off (enhancement mode) composite power device with an ESD protection clamp. Such a normally off composite power device includes a normally on (depletion mode) power transistor providing a composite drain of the normally off composite power device, and a normally off low voltage (LV) transistor cascoded with the normally on power transistor. The normally off LV transistor provides a composite source and a composite gate of the normally off composite power device. The normally off composite power device also includes the ESD protection clamp coupled between the composite source and the composite gate. The ESD protection clamp is configured to provide electrostatic discharge (ESD) protection for the normally off composite power device. | 06-11-2015 |
20150162303 | Array Based Fabrication of Power Semiconductor Package with Integrated Heat Spreader - In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module. | 06-11-2015 |
20150162297 | Power Converter Package with an Integrated Output Inductor - In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage stacked over the integrated output inductor. | 06-11-2015 |
20150155358 | Group III-V Transistor with Semiconductor Field Plate - There are disclosed herein various implementations of a group III-V transistor with a semiconductor field plate. Such a group III-V transistor includes a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG). In addition, the group III-V transistor includes a source electrode, a drain electrode, and a gate situated over the group heterostructure. The group III-V transistor also includes an insulator layer over the group III-V heterostructure and situated between the gate and the drain electrode, and a semiconductor field plate situated between the gate and the drain electrode, over the insulator layer. | 06-04-2015 |
20150137141 | Gallium Nitride Devices - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 05-21-2015 |
20150130036 | Semiconductor Package with Low Profile Switch Node Integrated Heat Spreader - In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier. | 05-14-2015 |
20150123630 | Voltage Converter with VCC-Less RDSon Current Sensing Circuit - In one implementation, a voltage converter includes a driver providing a gate drive for a power switch and a sense circuit coupled across the power switch. The gate drive provides power to the sense circuit, and the sense circuit provides a sense output to the driver corresponding to a current through the power switch. In one implementation, the sense circuit includes a high voltage (HV) sense transistor coupled between a first sense input and a sense output, a delay circuit configured to be coupled to the gate drive to provide power to the HV sense transistor when the gate drive is high, and a pull-down transistor configured to couple the sense output to a second sense input when the gate drive is low. | 05-07-2015 |
20150115911 | Adaptive Off Time Control Scheme for Semi-Resonant and Hybrid Converters - In one implementation, a voltage converter includes a high side power switch, and first and second low side power switches. The voltage converter also includes a driver stage for driving the high side power switch and the first and second low side power switches, and an adaptive OFF-time control circuit coupled to the driver stage. The adaptive OFF-time control circuit is configured to sense a current through one of the first and second low side switches, and to determine an adaptive off time for the high side power switch based on the sensed current. | 04-30-2015 |
20150115327 | Group III-V Device Including a Buffer Termination Body - There are disclosed herein various implementations of a III-Nitride device and method for its fabrication. The III-Nitride device includes a III-Nitride buffer layer situated over a substrate, the III-Nitride buffer layer having a first bandgap. In addition, the device includes a III-Nitride heterostructure situated over the III-Nitride buffer layer and configured to produce a two-dimensional electron gas (2DEG); the III-Nitride heterostructure including a channel layer having a second bandgap smaller than the first bandgap. The III-Nitride device also includes a buffer termination body situated between the III-Nitride buffer layer and the channel layer, the buffer termination body including a III-Nitride material having a third bandgap smaller than the first bandgap and larger the second bandgap. | 04-30-2015 |
20150077074 | Circuit and Method for Producing an Average Output Inductor Current Indicator - In one implementation, a circuit for producing an average output inductor current indicator in a voltage converter is configured to start a counter when a high side power switch turns on, to sense a sample current through an output inductor of the voltage converter after the high side power switch turns off and when a low side power switch is on, and to register a first count of the counter when the low side power switch turns off. The circuit is further configured to register a second count of the counter when the high side power switch subsequently turns on, and to produce the average output inductor current indicator based on the sample current and the first and second counts of the counter. | 03-19-2015 |
20150054564 | Level Shifter Utilizing a Capacitive Isolation Barrier - According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal. | 02-26-2015 |
20150014740 | Monolithic Composite III-Nitride Transistor with High Voltage Group IV Enable Switch - There are disclosed herein various implementations of a monolithically integrated component. In one exemplary implementation, such a monolithically integrated component includes an enhancement mode group IV transistor and two or more depletion mode III-Nitride transistors. The enhancement mode group IV transistor may be implemented as a group IV insulated gate bipolar transistor (group IV IGBT). One or more of the III-Nitride transistor(s) may be situated over a body layer of the group IV IGBT, or the III-Nitride transistor(s) may be situated over a collector layer of the IGBT. | 01-15-2015 |
20150014701 | III-Nitride Semiconductor Device with Reduced Electric Field - A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N | 01-15-2015 |
20140353723 | High Voltage Durability III-Nitride Device - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT. | 12-04-2014 |
20140353680 | Gallium Nitride Semiconductor Structures With Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 12-04-2014 |
20140339686 | Group III-V Device with a Selectively Modified Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 11-20-2014 |
20140339670 | Semiconductor Device with a Thick Bottom Field Plate Trench Having a Single Dielectric and Angled Sidewalls - Disclosed is a power device, such as a power MOSFET device and a method for fabricating same. The device includes a field plate trench. The field plate trench has a predetermined width and a predetermined sidewall angle. The device further includes a single trench dielectric on sidewalls of the field plate trench and at a bottom of the field plate trench. The single trench dielectric has a bottom thickness that is greater than a sidewall thickness. The device also includes a field plate situated within the single trench dielectric. | 11-20-2014 |
20140339669 | Semiconductor Device with a Field Plate Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as a power MOSFET, and methods for fabricating same. The device includes a field plate trench. The device further includes first and second trench dielectrics inside the field plate trench. The device also includes a field plate situated over the first trench dielectric and within the second trench dielectric. A combined thickness of the first and second trench dielectrics at a bottom of the field plate trench is greater than a sidewall thickness of the second trench dielectric. | 11-20-2014 |
20140339651 | Semiconductor Device with a Field Plate Double Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness. | 11-20-2014 |
20140332879 | Power Semiconductor Device with Reduced On-Resistance and Increased Breakdown Voltage - In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or both of an increased breakdown voltage and a reduced on-resistance in the power semiconductor device. | 11-13-2014 |
20140319665 | Power Semiconductor Package - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 10-30-2014 |
20140264373 | III-Nitride Heterojunction Device - A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions. | 09-18-2014 |
20140253217 | RF Switch Gate Control - In one implementation, a switching circuit includes a pass switch including group III-V, for example III-Nitride, transistors coupled between an input of the switching circuit and an output of the switching circuit. The switching circuit further includes a shunt switch configured to ground the input of the switching circuit while the pass switch is disabled. The switching circuit also includes a gate control transistor configured to reduce resistance between a control terminal of the pass switch and/or the shunt switch and gate of the group III-V transistor of the pass switch and/or the shunt switch so as to enable and disable the pass switch and/or shunt switch. The gate control transistor can be coupled across a gate resistor of the pass switch and/or the shunt switch. The gate control transistor can reduce the resistance in order to lower the OFF state impedance of the pass switch and/or the shunt switch. | 09-11-2014 |
20140252375 | Delamination and Crack Prevention in III-Nitride Wafers - In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches. | 09-11-2014 |
20140239349 | Drain Pad Having a Reduced Termination Electric Field - In an exemplary implementation, a semiconductor device includes a drain pad on a semiconductor substrate, the drain pad being coupled to a plurality of drain fingers. The semiconductor device further includes a source pad on the semiconductor substrate, the source pad being coupled to a plurality of source fingers. The plurality of source fingers is interdigitated with the plurality of drain fingers. Furthermore, an outer corner of the drain pad has a gradual transition between adjoining sides of the drain pad. The gradual transition between the adjoining sides of the drain pad reduces a termination electric field at the outer corner of the drain pad. Furthermore, the gradual transition between the adjoining sides of the drain pad increases the breakdown voltage of the semiconductor device. | 08-28-2014 |
20140213046 | Fabrication of III-Nitride Layers - A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method. | 07-31-2014 |
20140210768 | Single Layer Touch Sensor - According to an exemplary implementation, a touch sensor includes a plurality of traces situated between first and second columns of transmitter pads on a substrate. Each trace in the plurality of traces is routed from one extremity of the substrate and ends at a corresponding transmitter pad thereby creating an available area between the first and second columns of transmitter pads for one or more remaining traces of the plurality of traces. In some implementations, for at least one trace in the plurality of traces, each of the one or more remaining traces have an expanded width in the available area. Furthermore, at least one dummy pad can be situated in the available area for at least one trace in the plurality of traces. | 07-31-2014 |
20140210519 | Combined Sense Signal Generation and Detection - In an exemplary implementation, a detection circuit for regulating a power converter is configured to receive a combined sense signal comprising a first sense signal from the power converter superimposed with a second sense signal from the power converter. The detection circuit is further configured to generate a first detect signal from the combined sense signal and generate a second detect signal from the combined sense signal. The first detect signal can correspond to the first sense signal and the second detect signal can correspond to the second sense signal. The detection circuit can generate a filtered signal corresponding to the first sense signal from the combined sense signal to generate the first detect signal from the combined sense signal. Also, the detection circuit can generate an offset signal based on the combined sense signal to generate the second detect signal from the combined sense signal. | 07-31-2014 |
20140210092 | Refractory Metal Nitride Capped Contact - According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device. | 07-31-2014 |
20140203419 | Half-Bridge Package with a Conductive Clip - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe. | 07-24-2014 |
20140203295 | INTEGRATED POWER DEVICE WITH III-NITRIDE HALF BRIDGES - A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die. | 07-24-2014 |
20140203294 | Gallium Nitride Devices - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 07-24-2014 |
20140197462 | III-Nitride Transistor with High Resistivity Substrate - There are disclosed herein various implementations of semiconductor structures including high resistivity substrates. In one exemplary implementation, such a semiconductor structure includes a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm), and a III-N high electron mobility transistor (HEMT) having a drain, a source, and a gate, fabricated over the substrate. The III-N HEMT is configured to produce a two-dimensional electron gas (2 DEG). The resistivity of the substrate reduces the capacitive coupling of the 2 DEG to the substrate. In one implementations, a spatially confined dielectric region is formed in the substrate, under at least one of the drain and the source. | 07-17-2014 |
20140197461 | Semiconductor Structure Including A Spatially Confined Dielectric Region - There are disclosed herein various implementations of semiconductor structures including one or more spatially confined dielectric regions. In one exemplary implementation, such a semiconductor structure includes a III-Nitride field-effect transistor (FET) having a drain, a source, and a gate, fabricated over a substrate. A spatially confined dielectric region is formed under the drain in the substrate, the spatially confined dielectric region reducing a capacitive coupling of the drain to the substrate. In another exemplary implementation, a spatially confined dielectric region is formed under each of the source and the drain of the FET, in the substrate, the spatially confined dielectric regions reducing a capacitive coupling of the source and the drain to the substrate. | 07-17-2014 |
20140192441 | DC/DC Converter with III-Nitride Switches - Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. | 07-10-2014 |
20140191337 | Stacked Half-Bridge Package - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source. | 07-10-2014 |
20140175630 | Semiconductor Package with Multiple Conductive Clips - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 06-26-2014 |
20140169052 | III-Nitride Power Conversion Circuit - According to an exemplary embodiment, a III-nitride power conversion circuit includes a gate driver having a plurality of cascaded inverters, each of the plurality of cascaded inverters including at least one III-nitride transistor. At least one of the plurality of cascaded inverters has a cutoff switch and a III-nitride depletion mode load where the cutoff switch is configured to disconnect the III-nitride depletion mode load so as to prevent current from flowing from a supply voltage of the at least one of the plurality of cascaded inverters. The cutoff switch of the at least one of the plurality of cascaded inverters can be driven by one of the plurality of cascaded inverters. The III-nitride power conversion circuit can also include an output driver driven by the gate driver where the output driver has a segmented III-nitride transistor. Furthermore, a selector circuit can be configured to selectively disable at least one segment of the segmented III-nitride transistor. | 06-19-2014 |
20140167153 | Trench Fet Having Merged Gate Dielectric - In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode. | 06-19-2014 |
20140167152 | Reduced Gate Charge Trench Field-Effect Transistor - In one implementation, a trench field-effect transistor (trench FET) can include a semiconductor substrate including a drain region, a drift zone over the drain region, and first and second gate trenches including a gate dielectric and respective gate electrodes disposed therein, also over the drain region. The trench FET can further include a depletion trench situated between the first and second gate trenches, the depletion trench including a trench insulator. The trench insulator adjoins the gate electrodes and the gate dielectric so as to reduce a gate charge of the trench FET. | 06-19-2014 |
20140167112 | Cascode Circuit Integration of Group III-N and Group IV Devices - In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can he situated over the group IV transistor die. | 06-19-2014 |
20140159116 | III-Nitride Device Having an Enhanced Field Plate - In an exemplary implementation, a semiconductor device includes a III-nitride heterojunction including a III-nitride barrier layer situated over a III-nitride channel layer to form a conduction channel including a two-dimensional electron gas. The semiconductor device further includes a gate electrode coupled to a field plate. The field plate includes a plurality of steps insulated from the conduction channel by a dielectric body and the III-nitride barrier layer. The dielectric body under each one of the plurality of steps contributes to a breakdown voltage that is at least twice a breakdown voltage of the semiconductor device at each corresponding step. The breakdown voltage can correspond to a breakdown voltage of the dielectric body and the III-nitride barrier layer. | 06-12-2014 |
20140147998 | Ion Implantation at High Temperature Surface Equilibrium Conditions - There are disclosed herein various implementations of a method and system for ion implantation at high temperature surface equilibrium conditions. The method may include situating a III-Nitride semiconductor body in a surface equilibrium chamber, establishing a gas pressure greater than or approximately equal to a surface equilibrium pressure of the III-Nitride semiconductor body, and heating the III-Nitride semiconductor body to an elevated implantation temperature in the surface equilibrium chamber while substantially maintaining the gas pressure. The method also includes implanting the III-Nitride semiconductor body in the surface equilibrium at the elevated implantation temperature chamber while substantially maintaining the gas pressure, the implanting being performed using an ion implanter interfacing with the surface equilibrium chamber. | 05-29-2014 |
20140131767 | Dual Compartment Semiconductor Package - According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package. | 05-15-2014 |
20140131709 | Semiconductor Package with Temperature Sensor - According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package. | 05-15-2014 |
20140131659 | Gallium Nitride Devices With Aluminum Nitride Intermediate Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 05-15-2014 |
20140127861 | Semiconductor Packages Utilizing Leadframe Panels with Grooves in Connecting Bars - According to an exemplary implementation, a method includes utilizing a leadframe panel comprising a plurality of leadframe modules, each of the plurality of leadframe modules having a leadframe pad. The leadframe panel has a plurality of bars each having a plurality of grooves, where the plurality of bars connect the plurality of leadframe modules. The method further includes attaching a device to the leadframe pad. The method also includes molding the leadframe panel while leaving a bottom of the leadframe pad exposed. Furthermore, the method includes sawing through the plurality of grooves of the plurality of bars to singulate the plurality of leadframe modules into separate packaged modules. | 05-08-2014 |
20140126256 | Semiconductor Package Having an Over-Temperature Protection Circuit Utilizing Multiple Temperature Threshold Values - According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes an over-temperature protection circuit configured to reduce current through the power switches based on multiple temperature threshold values of the power switches and a sensed temperature of the power switches. The over-temperature protection circuit can be configured to enter first and second modes based on the multiple temperature threshold values and the sensed temperature, where the second mode reduces current through the power switches to a greater extent than the first mode. | 05-08-2014 |
20140124890 | Semiconductor Package Having Multi-Phase Power Inverter with Internal Temperature Sensor - According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes a temperature sensor situated on the leadframe, where the temperature sensor is configured to generate a sensed temperature of the power switches. The semiconductor package also includes a driver circuit configured to drive the power switches of the multi-phase power inverter responsive to the sensed temperature. The temperature sensor can be on a common IC with the driver circuit. Furthermore, the semiconductor package can include an over-temperature protection circuit configured to provide over-temperature protection to the multi-phase power inverter using the sensed temperature. | 05-08-2014 |
20140118032 | Buck Converter Power Package - One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip. | 05-01-2014 |
20140117518 | Control and Driver Circuits on a Power Quad Flat No-Lead (PQFN) Leadframe - According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase and W-phase power switches situated on the PQFN leadframe and respectively connected to a U-phase output strip and a W-phase output pad of the PQFN leadframe. The PQFN leadframe further includes a common integrated circuit (IC) including a driver circuit and a control circuit where the common IC is connected to the U-phase output strip and to the W-phase output pad of the PQFN leadframe. The PQFN leadframe can also include a V-phase power switch situated on the PQFN leadframe where the V-phase power switch is connected to a V-phase output strip of the PQFN leadframe. | 05-01-2014 |
20140117517 | Power Quad Flat No-Lead (PQFN) Package Having Control and Driver Circuits - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase power inverter, a control circuit, and a driver circuit. The driver circuit is configured to drive the multi-phase power inverter responsive to a control signal from the control circuit. The multi-phase power inverter, the control circuit, and the driver circuit are each situated on a PQFN leadframe of the PQFN package. The control circuit and the driver circuit can be in a common integrated circuit (IC). Furthermore, the control circuit can be configured to reconstruct at least two phase currents of the multi-phase power inverter from a combined phase current. | 05-01-2014 |
20140110863 | Power Converter Package Including Vertically Stacked Driver IC - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. | 04-24-2014 |
20140110796 | Semiconductor Package with Conductive Carrier Integrated Heat Spreader - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier. | 04-24-2014 |
20140110788 | Power Converter Package Including Top-Drain Configured Power FET - In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET. | 04-24-2014 |
20140110776 | Semiconductor Package Including Conductive Carrier Coupled Power Switches - In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain. | 04-24-2014 |
20140106548 | Fabrication of III-Nitride Semiconductor Device and Related Structures - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 04-17-2014 |
20140103514 | Power Quad Flat No-Lead (PQFN) Package Having Bootstrap Diodes on a Common Integrated Circuit (IC) - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase inverter situated on a leadframe. The PQFN package further includes drivers situated on the leadframe and configured to drive the multi-phase inverter. The PQFN package also includes bootstrap diodes respectively coupled to the drivers. The bootstrap diodes are in a common integrated circuit (IC) that is situated on the leadframe. The common IC can include the drivers. The drivers can be high side drivers that are coupled to high side power switches of the multi-phase inverter. Also, the bootstrap diodes can be coupled to a supply voltage terminal of the PQFN package. Furthermore, the PQFN package can include wirebonds coupling the common IC to bootstrap supply voltage terminals of the PQFN package. | 04-17-2014 |
20140103393 | Surface Mountable Power Components - According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device. | 04-17-2014 |
20140097531 | Power Quad Flat No-Lead (PQFN) Package in a Single Shunt Inverter Circuit - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC. | 04-10-2014 |
20140097498 | Open Source Power Quad Flat No-Lead (PQFN) Leadframe - According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase power switch is connected to a U-phase output strip of the PQFN leadframe. A source of the U-phase power switch is connected to a U-phase current sense terminal. The U-phase output strip can substantially traverse across the PQFN leadframe. Another U-phase power switch is situated on the PQFN leadframe with a source of the another U-phase power switch connected to the U-phase output strip of the PQFN leadframe. The PQFN leadframe can include a leadframe island within the U-phase output strip. At least one wirebond may be connected to the U-phase output strip. | 04-10-2014 |
20140097471 | Active Area Shaping of III-Nitride Devices Utilizing A Field Plate Defined By A Dielectric Body - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. The III-nitride semiconductor device also includes a gate arrangement situated in the gate well and including a gate electrode and a field plate. The field plate includes at least two steps, the at least two steps being defined in the dielectric body. | 04-10-2014 |
20140097446 | Gallium Nitride Devices with Gallium Nitride Alloy Intermediate Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 04-10-2014 |
20140091449 | Power Quad Flat No-Lead (PQFN) Semiconductor Package with Leadframe Islands for Multi-Phase Power Inverter - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a U-phase output node situated on a first leadframe island of a leadframe, a V-phase output node situated on a second leadframe island of said leadframe, and a W-phase output node situated on a W-phase die pad of said leadframe. The first leadframe island can be on a first leadframe strip of the leadframe, where the first leadframe strip is connected to a U-phase die pad of the leadframe. The second leadframe island can be on a second leadframe strip of the leadframe, where the second leadframe strip is connected to a V-phase die pad of the leadframe. A first W-phase power switch is situated on the W-phase die pad. Furthermore, at least one wirebond is connected to the W-phase die pad and to a source of a second W-phase power switch. The W-phase die pad can be a W-phase output terminal of the PQFN package. | 04-03-2014 |
20140084431 | Semiconductor Package with Heat Spreader - A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. | 03-27-2014 |
20140077222 | Gallium Nitride Devices with Aluminum Nitride Alloy Intermediate Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 03-20-2014 |
20140070786 | Power Converter Including Integrated Driver Providing Overcurrent Protection - In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die. | 03-13-2014 |
20140070627 | Integrated Group III-V Power Stage - In one implementation, an integrated group III-V power stage includes a control switch including a first group III-V transistor coupled to a sync switch including a second group III-V transistor. The integrated group III-V power stage may also include one or more driver stages, which may be fabricated in a group die or dies. The driver stage or driver stages, the control switch, and the sync switch may all be situated in a single semiconductor package. | 03-13-2014 |
20140070280 | Active Area Shaping of III-Nitride Devices Utilizing Steps of Source-Side and Drain-Side Field Plates - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include one or more steps, where the drain-side field plate has a different number of the one or more steps than the source-side field plate. | 03-13-2014 |
20140070279 | Active Area Shaping of III-Nitride Devices Utilizing a Source-Side Field Plate and a Wider Drain-Side Field Plate - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include steps, and the drain-side field plate is wider than the source-side field plate. | 03-13-2014 |
20140070278 | Active Area Shaping of III-Nitride Devices Utilizing Multiple Dielectric Materials - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a dielectric body situated over the III-nitride heterojunction and including a first dielectric layer of a first dielectric material and a second dielectric layer of a second dielectric material different than the first dielectric material. A gate well of a first width is defined by the first dielectric layer, and is of a second width defined by the second dielectric layer, where the second width is greater than the first width. The III-nitride semiconductor device further includes a gate arrangement situated in the gate well and including a gate electrode integrated with a field plate. | 03-13-2014 |
20140061885 | Power Quad Flat No-Lead (PQFN) Package - Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes. | 03-06-2014 |
20140055109 | Power Converter Including Integrated Driver for Depletion Mode Group III-V Transistor - In one implementation, a power converter includes an output stage integrated circuit (IC) on a group III-V die, and a driver IC for driving the output stage IC, the driver IC fabricated on a group IV die. The power converter also includes a composite power switch split between the group III-V die and the group IV die, wherein a depletion mode group III-V transistor of the composite power switch is monolithically integrated in the group III-V die, and a group IV control switch of the composite power switch is monolithically integrated in the group IV die. As a result, the depletion mode group III-V transistor may be operated as an enhancement mode transistor. | 02-27-2014 |
20140054607 | Group III-V Device with Strain-Relieving Layers - According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer. | 02-27-2014 |
20140048923 | Semiconductor Package for High Power Devices - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 02-20-2014 |
20140038391 | III-Nitride Wafer Fabrication - A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof. | 02-06-2014 |
20140035005 | Monolithic Integrated Group III-V and Group IV Device - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT). | 02-06-2014 |
20140034959 | III-Nitride Semiconductor Device with Stepped Gate - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. | 02-06-2014 |
20140030858 | Enhancement Mode III-Nitride Device - A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device. | 01-30-2014 |
20140030854 | High Voltage Cascoded III-Nitride Rectifier Package - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing. | 01-30-2014 |
20140028369 | Level Shifter Utilizing Bidirectional Signaling Through a Capacitive Isolation Barrier - According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal. | 01-30-2014 |
20140008663 | Integrated Composite Group III-V and Group IV Semiconductor Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 01-09-2014 |
20140001614 | Thermally Enhanced Semiconductor Package | 01-02-2014 |
20130337626 | Monolithic Group III-V and Group IV Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in. the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a side-wall of the trench. | 12-19-2013 |
20130337611 | Thermally Enhanced Semiconductor Package with Conductive Clip - One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation. | 12-19-2013 |
20130334574 | Monolithic Integrated Composite Group III-V and Group IV Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 12-19-2013 |
20130316527 | Multi-Chip-Scale Package - Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT. | 11-28-2013 |
20130299877 | Integrated III-Nitride and Silicon Device - A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body. | 11-14-2013 |
20130278181 | Reverse Rotation of a Motor Configured for Operation in a Forward Direction - There are disclosed herein various implementations of a method and a system enabling operation of a motor in reverse. Such a method includes applying a first drive signal to begin rotating the motor in a reverse direction, the first drive signal being applied for a predetermined period of time. The method also includes using a position sensor signal for the motor to control motor drive in the reverse direction when the motor reaches a predetermined reverse speed, and operating the motor in the reverse direction. | 10-24-2013 |
20130277711 | Oscillation Free Fast-Recovery Diode - In one implementation, a diode providing a substantially oscillation free fast-recovery includes at least one anode diffusion formed at a front side of a semiconductor die, and a cathode layer formed at a back side of the semiconductor die. The diode also includes a drift region and a buffer layer situated between the drift region and the cathode layer to enable the substantially oscillation free fast-recovery by the diode. In one implementation, the buffer layer is N type doped using hydrogen as a dopant. | 10-24-2013 |
20130277362 | Power Converter with Over-Voltage Protection - In one implementation, a power converter with over-voltage protection includes a power switch coupled to a power supply through a tank circuit, and a control circuit coupled to a gate of the power switch. The control circuit is configured to turn the power switch OFF based on a current from the tank circuit, thereby providing the over-voltage protection to the power converter. In one implementation, the power converter is a class-E power converter. In one implementation, the control circuit is configured to sense the current from the tank circuit based on a voltage drop across a sense resistor coupled to the power switch. | 10-24-2013 |
20130271201 | System on Chip for Power Inverter - According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value. | 10-17-2013 |
20130264968 | Power Converter Having an Advanced Control IC - There are disclosed herein various implementations of a power converter having an advanced control integrated circuit (IC). The power converter includes the control IC and a power switch. The control IC includes a driving stage for driving the power switch, and a sensing stage coupled to the driving stage. The sensing stage is configured to produce a control signal for the driving stage based on an output current of the power converter sensed at a high side bus of the power converter. | 10-10-2013 |
20130264636 | Trench FET with Ruggedness Enhancement Regions - According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches. | 10-10-2013 |
20130264579 | III-Nitride Heterojunction Device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. | 10-10-2013 |
20130256905 | Monolithic Power Converter Package with Through Substrate Vias - According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. The high side power input and a power output of the half-bridge each are disposed on a top surface of the monolithic die. The high side power input is electrically coupled to the substrate through a high side power connection. The power output is electrically coupled to the substrate through a power output connection. The low side power input of the half-bridge comprises a plurality of through substrate vias that extend through the monolithic die to electrically connect a low side power pad to the monolithic die. | 10-03-2013 |
20130256894 | Porous Metallic Film as Die Attach and Interconnect - One exemplary disclosed embodiment comprises a sintered porous metallic film as a die attach mechanically connecting a backside of a semiconductor die to a substrate of a package. Another exemplary disclosed embodiment comprises a sintered porous metallic film as an electrical connection between an electrode on an active surface of a semiconductor die and a substrate of a package. The porous metallic film may be integrated as a prefabricated film or may be created at the wafer or substrate level. By providing a conformal bond through the presence of pores in the metallic film, the sintered connection can provide a reliable mechanical connection with a lower effective elastic modulus. Thermal expansion stresses between die and substrate are thereby accommodated for robustness against thermal cycling, which is of particular relevance for high performance power modules and automotive applications. | 10-03-2013 |
20130256859 | Dual Power Converter Package Using External Driver IC - A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively. | 10-03-2013 |
20130256807 | Integrated Dual Power Converter Package Having Internal Driver IC - An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. | 10-03-2013 |
20130256745 | Deep Gate Trench IGBT - There are disclosed herein various implementations of an insulated-gate bipolar transistor (IGBT) with buried depletion electrode. Such an IGBT may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region. The IGBT also includes a plurality of deep insulated trenches with a buried depletion electrode and at least one gate electrode disposed therein. In addition, the IGBT includes an active cell including an emitter adjacent the gate electrode, and an implant zone, situated between adjacent deep insulated trenches. The implant zone is formed below the base layer and has the first conductivity type. In one implementation, the IGBT may also include a dummy cell neighboring the active cell. | 10-03-2013 |
20130256744 | IGBT with Buried Emitter Electrode - There are disclosed herein various implementations of an insulated gate bipolar transistor (IGBT) with buried emitter electrodes. Such an IGBT may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region. In addition, such an IGBT may include deep insulated trenches extending from a semiconductor surface above the base layer, into the drift region, each of the deep insulated trenches having a buried emitter electrode disposed therein. The IGBT may further include an active cell including an emitter, a gate trench with a gate electrode disposed therein, and an implant zone situated, between adjacent deep insulated trenches. The implant zone is formed below the base layer and has the first conductivity type. | 10-03-2013 |
20130249508 | Voltage Regulator Having an Emulated Ripple Generator - According to an exemplary implementation, a voltage regulator includes an emulated ripple generator. The emulated ripple generator includes a high side switch configured to control charging of an emulated ripple. The emulated ripple generator further includes a low side switch configured to control discharging of the emulated ripple. The high side switch and the low side switch are configured to control the charging and the discharging such that the emulated ripple is substantially in-phase with an inductor current of the voltage regulator. The high side switch can be configured to control the charging by selectively enabling a high side current source. Furthermore, the low side switch can be configured to control the discharging by selectively enabling a low side current source. | 09-26-2013 |
20130249072 | Direct Contact Package for Power Transistors - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 09-26-2013 |
20130248884 | III-Nitride Power Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 09-26-2013 |
20130240911 | III-Nitride Multi-Channel Heterojunction Device - A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions. | 09-19-2013 |
20130240898 | Group III-V and Group IV Composite Switch - In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die. | 09-19-2013 |
20130234208 | Composite Semiconductor Device with Active Oscillation Prevention - There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000. | 09-12-2013 |
20130229126 | Electronic Ballast with Power Factor Correction - According to an exemplary implementation, an electronic ballast includes an input filter coupled to a resonant tank. The resonant tank is configured to generate a resonant current. The input filter is configured to receive an AC input voltage and to generate an AC input current from the resonant current by smoothing the resonant current. The electronic ballast also includes a half-bridge configured to feed the resonant tank so as to generate the resonant current and to receive a supply voltage that is in phase with the AC input voltage. The electronic ballast can also include a controller configured to control a power factor of the electronic ballast by switching the half-bridge. The controller can be configured to adjust a shape of the AC input current by adjusting switching of the half-bridge to thereby adjust a power factor of the electronic ballast. | 09-05-2013 |
20130228794 | Stacked Half-Bridge Package with a Common Leadframe - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. | 09-05-2013 |
20130214330 | Transistor Having Increased Breakdown Voltage - There are disclosed herein various implementations of a transistor having an increased breakdown voltage. Such a transistor includes a source finger electrode having a source finger electrode beginning and a source finger electrode end. The transistor also includes a drain finger electrode with a curved drain finger electrode end having an increased radius of curvature. The resulting decreased electric field at the curved drain finger electrode end allows for an increased breakdown voltage and a more robust and reliable transistor. In some implementations, the curved drain finger electrode end may be extended beyond the source finger electrode beginning to achieve the increased breakdown voltage. | 08-22-2013 |
20130214283 | Power Transistor Having Segmented Gate - There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off. | 08-22-2013 |
20130207120 | Power Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson. | 08-15-2013 |
20130196490 | Method and Apparatus for Growing a III-Nitride Layer - A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method. | 08-01-2013 |
20130182470 | Power Module Package Having a Multi-Phase Inverter and Power Factor Correction - According to an exemplary implementation, a power module package includes a multi-phase inverter. The power module package also includes a multi-phase inverter driver configured to drive the multi-phase inverter. The power module package further includes a power factor correction (PFC) circuit where the PFC circuit is configured to regulate a bus voltage of the multi-phase inverter and a PFC driver configured to drive the PFC circuit. The multi-phase inverter, the multi-phase inverter driver, the PFC circuit, and the PFC driver are situated on a package substrate of the power module package. The multi-phase inverter driver and the PFC driver can be in a common driver integrated circuit (IC). | 07-18-2013 |
20130175690 | Power Semiconductor Device with Reduced Contact Resistance - A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device. | 07-11-2013 |
20130175542 | Group III-V and Group IV Composite Diode - In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die. | 07-11-2013 |
20130161803 | Semiconductor Package with Conductive Heat Spreader - A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. | 06-27-2013 |
20130147016 | Semiconductor Package Having Internal Shunt and Solder Stop Dimples - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 06-13-2013 |
20130143399 | Method for Forming a Reliable Solderable Contact - A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites. | 06-06-2013 |
20130140701 | Solderable Contact and Passivation for Semiconductor Dies - A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites. | 06-06-2013 |
20130140684 | Semiconductor Device Assembly Utilizing a DBC Substrate - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 06-06-2013 |
20130140602 | Power Semiconductor Package with Conductive Clip - According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively. | 06-06-2013 |
20130134524 | Multi-Transistor Exposed Conductive Clip for Semiconductor Packages - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 05-30-2013 |
20130134437 | METHOD FOR FORMING GALLIUM NITRIDE DEVICES WITH CONDUCTIVE REGIONS - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 05-30-2013 |
20130126895 | Gallium Nitride Devices with Vias - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 05-23-2013 |
20130115746 | Method for Fabricating a Vertical LDMOS Device - A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body. | 05-09-2013 |
20130112990 | Gallium Nitride Devices with Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of o semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 05-09-2013 |
20130105958 | Compact Wirebonded Power Quad Flat No-Lead (PQFN) Package | 05-02-2013 |
20130105814 | Active Area Shaping for III-Nitride Devices | 05-02-2013 |
20130099579 | System and Method for Providing Active Power Balancing - According to one embodiment, a system for actively balancing power between several power units is disclosed. Each of the power units includes a corresponding group of cascoded energy cells. The system for actively balancing power comprises a group of buck/boost circuits used in each of the power units for maintaining an internal power balance among the corresponding group of cascoded energy cells, and an energy distribution circuit for responding to a respective energy need in each of the power units. The energy distribution circuit is configured to transfer energy between the power units to balance power among the power units according to their respective energy needs. In one embodiment, a method for actively balancing power between several power units comprises maintaining the internal power balance among the group of cascoded energy cells within each of the power units, and transferring energy between the power units as needed. | 04-25-2013 |
20130093356 | Flyback Driver for Use in a Flyback Power Converter and Related Method - According to one embodiment, a flyback power converter comprises a primary circuit including a flyback driver, and an isolated output circuit responsive to the primary circuit. The isolated output circuit is used to power a load. The flyback driver is configured to identify a load current in the isolated output circuit from an input power to the primary circuit, and to regulate the load current according to the input power. In one embodiment, the flyback driver is configured to sense an input voltage to the flyback power converter, to identify an average current value corresponding to a current through a converter switch in the primary circuit, and to multiply the average current value and the input voltage to determine the input power to the primary circuit. | 04-18-2013 |
20130076311 | System for Actively Managing Energy Banks During Energy Transfer and Related Method - According to one embodiment, a system for actively managing energy banks during an energy transfer process comprises a plurality of energy banks configured for use as a group of energy banks and characterized by a desired state-of-charge (SOC), and a power management system coupled across each of the energy banks. The power management system is configured to selectively drive at least one of the energy banks to a modified SOC different from the desired SOC without interrupting the energy transfer process. In one embodiment, the power management system is further configured to return the energy bank or banks driven to the modified SOC to the desired SOC of the group of energy banks. | 03-28-2013 |
20130069208 | Group III-V Device Structure Having a Selectively Reduced Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 03-21-2013 |
20130049079 | Small-Outline Package for a Power Transistor - According to an exemplary embodiment, a small-outline package includes a power transistor having a source and a drain, the power transistor situated on a paddle of a leadframe of the small-outline package. The source of the power transistor is electrically connected to a plurality of source leads. The drain of the power transistor is electrically and thermally connected to a top side of the paddle of the leadframe, the paddle of the leadframe being exposed from a bottom surface of the small-outline package, thereby providing a direct electrical contact to the drain from a bottom side of the paddle of the leadframe. | 02-28-2013 |
20130026822 | Energy Storage System and Related Method - Disclosed herein is an energy storage system and related method. According to one embodiment, such a system comprises a power management system and a plurality of energy banks coupled to the power management system, wherein each of the plurality of energy banks is capable of being independently discharged through the power management system. The power management system is configured to select at least one of the plurality of energy banks to transfer energy between the energy storage system and a machine powered using the energy storage system. According to one embodiment, the method comprises determining an energy transfer requirement of the machine powered by the energy storage system, selecting at least one of the plurality of energy banks for responding to the energy transfer requirement, and transferring energy between the selected energy bank(s) and the machine according to the energy transfer requirement. | 01-31-2013 |
20130015905 | Nested Composite Switch - There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor. | 01-17-2013 |
20130015501 | Nested Composite Diode - There are disclosed herein various implementations of nested composite diodes. In one implementation, a nested composite diode includes a primary transistor coupled to a composite diode. The composite diode includes a low voltage (LV) diode cascoded with an intermediate transistor having a breakdown voltage greater than the LV diode and less than the primary transistor. In one implementation, the primary transistor may be a group III-V transistor and the LV diode may be an LV group IV diode. | 01-17-2013 |
20130015499 | Composite Semiconductor Device with a SOI Substrate Having an Integrated Diode - There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a semiconductor on insulator (SOI) substrate including a diode and an insulator layer. The composite semiconductor device also includes a transition body formed over the diode, and a transistor formed over the transition body. The diode is connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two. | 01-17-2013 |
20130015495 | Stacked Half-Bridge Power Module - According to an exemplary embodiment, a stacked half-bridge power module includes a high side device having a high side power terminal coupled to a high side substrate and a low side device having a low side power terminal coupled to a low side substrate. The high side and low side devices are stacked on opposite sides of a common conductive interface. The common conductive interface electrically, mechanically, and thermally couples a high side output terminal of the high side device to a low side output terminal of the low side device. The high side device and the low side device can each include an insulated-gate bipolar transistor (IGBT) in parallel with a diode. | 01-17-2013 |
20130001648 | Gated AlGaN/GaN Schottky Device - Some exemplary embodiments of a semiconductor device using a III-nitride heterojunction and a novel Schottky structure and related method resulting in such a semiconductor device, suitable for high voltage circuit designs, have been disclosed. One exemplary structure comprises a first layer comprising a first III-nitride material, a second layer comprising a second III-nitride material forming a heterojunction with said first layer to generate a two dimensional electron gas (2DEG) within said first layer, an anode comprising at least a first metal section forming a Schottky contact on a surface of said second layer, a cathode forming an ohmic contact on said surface of said second layer, a field dielectric layer on said surface of said second layer for isolating said anode and said cathode, and an insulating material on said surface of said second layer and in contact with said anode. | 01-03-2013 |
20120314372 | Power Semiconductor Package with Double-Sided Cooling - According to an exemplary embodiment, a power semiconductor package includes a power module having a plurality of power devices. Each of the plurality of power devices can be a power switch. The power semiconductor package also includes a double-sided heat sink with a top side in contact with a plurality of power device top surfaces and a bottom side in contact with a bottom surface of the power module. The power semiconductor package can include at least one fastening clamp pressing the top side and the bottom side of the double-sided heat sink into the power module. The double-sided heat sink can also include a water-cooling element. | 12-13-2012 |
20120313106 | Enhancement Mode Group III-V High Electron Mobility Transistor (HEMT) and Method for Fabrication - According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer. | 12-13-2012 |
20120306072 | Semiconductor Wafer with Reduced Thickness Variation and Method for Fabricating Same - According to one embodiment, a semiconductor wafer comprises a plurality of solder bumps for providing device contacts formed over a functional region of the semiconductor wafer, and one or more support rings surrounding the functional region. The one or more support rings and the plurality of solder bumps are formed so as to have substantially matching heights. The presence of the one or more support rings causes the semiconductor wafer to have a substantially uniform thickness in the functional region after a thinning process is performed on the semiconductor wafer. A method for fabricating the semiconductor wafer comprises forming the plurality of solder bumps over the functional region, and forming the one or more support rings surrounding the functional region before performing the thinning process on the semiconductor wafer. | 12-06-2012 |
20120292754 | Common Drain Exposed Conductive Clip for High Power Semiconductor Packages - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors having a common drain coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors for various power applications. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 11-22-2012 |
20120292753 | MULTI-TRANSISTOR EXPOSED CONDUCTIVE CLIP FOR HIGH POWER SEMICONDUCTOR PACKAGES - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 11-22-2012 |
20120292752 | Thermally Enhanced Semiconductor Package with Exposed Parallel Conductive Clip - One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation. | 11-22-2012 |
20120280247 | High Voltage Cascoded III-Nitride Rectifier Package Utilizing Clips on Package Support Surface - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing. | 11-08-2012 |
20120280246 | High Voltage Cascoded III-Nitride Rectifier Package with Etched Leadframe - Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts. | 11-08-2012 |
20120280245 | High Voltage Cascoded III-Nitride Rectifier Package with Stamped Leadframe - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts. | 11-08-2012 |
20120275121 | Power Module with Press-Fit Clamps - According to an exemplary embodiment, a bondwireless power module residing on a top surface of a substrate includes at least one input power pad providing power to the module and at least one output current pad providing output current from the module. At least one press-fit input power clamp engages a top side of the at least one input power pad, and engages a bottom surface of the substrate. Also, at least one press-fit output current clamp engages a top side of the at least one output current pad, and engages the bottom surface of the substrate. The at least one press-fit input power clamp can include at least one top prong and at least one bottom prong. Furthermore, the at least one bottom prong can press the input power pad into the at least one top prong. | 11-01-2012 |
20120274366 | Integrated Power Stage - In one implementation, an integrated power stage includes a common die situated over a load stage, the common die includes a driver stage and power switches. The power switches include a control transistor and a sync transistor. A drain of the control transistor receives an input voltage of the common die on one side (e.g., on a top surface) of the common die. A source of the control transistor is coupled to a drain of the sync transistor and provides an output voltage of the common die on an opposite side (e.g., on a bottom surface) of the common die. An interposer may be included under the power stage and includes an output inductor and optionally an output capacitor coupled to the output voltage of the common die on the opposite side of the common die. | 11-01-2012 |
20120262100 | Bondwireless Power Module with Three-Dimensional Current Routing - According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module. | 10-18-2012 |
20120256190 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Diode - In one implementation, a stacked composite device comprises a group IV diode and a group III-V transistor stacked over the group IV diode. A cathode of the group IV diode is in contact with a source of the group III-V transistor, an anode of the group IV diode is coupled to a gate of the group III-V transistor to provide a composite anode on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite cathode on a top side of the stacked composite device. | 10-11-2012 |
20120256189 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Vertical Transistor - In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device. | 10-11-2012 |
20120256188 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Lateral Transistor - In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device. | 10-11-2012 |
20120248564 | Dual Compartment Semiconductor Package with Temperature Sensor - According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package. | 10-04-2012 |
20120241820 | III-Nitride Transistor with Passive Oscillation Prevention - There are disclosed herein various implementations of semiconductor devices having passive oscillation control. In one exemplary implementation, such a device is implemented to include a III-nitride transistor having a source electrode, a gate electrode and a drain electrode. A damping resistor is configured to provide the passive oscillation control for the III-nitride transistor. In one implementation, the damping resistor includes at least one lumped resistor. | 09-27-2012 |
20120241819 | Composite Semiconductor Device with Turn-On Prevention Control - There are disclosed herein various implementations of composite III-nitride semiconductor devices having turn-on prevention control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device is configured to have a noise-resistant threshold voltage to provide the turn-on prevention control for the normally OFF composite semiconductor device by preventing noise current from flowing through a channel of the normally ON III-nitride power transistor in a noisy system. | 09-27-2012 |
20120241756 | High Voltage Composite Semiconductor Device with Protection for a Low Voltage Device - There are disclosed herein various implementations of composite semiconductor devices including a voltage protected device. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor having a first output capacitance, and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device, the LV device having a second output capacitance. A ratio of the first output capacitance to the second output capacitance is set based on a ratio of a drain voltage of the normally ON III-nitride power transistor to a breakdown voltage of the LV device so as to provide voltage protection for the LV device. | 09-27-2012 |
20120235209 | High Voltage Rectifier and Switching Circuits - According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor. | 09-20-2012 |
20120223415 | IGBT Power Semiconductor Package Having a Conductive Clip - According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively. | 09-06-2012 |
20120223365 | III-Nitride Semiconductor Structures with Strain Absorbing Interlayer Transition Modules - There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure. | 09-06-2012 |
20120223322 | III-Nitride Transistor Stacked with Diode in a Package - One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages. | 09-06-2012 |
20120223321 | III-Nitride Transistor Stacked with FET in a Package - One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages. | 09-06-2012 |
20120211825 | Trench MOSFET and Method for Fabricating Same - According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode. | 08-23-2012 |
20120200547 | Gate Driver with Multiple Slopes for Plasma Display Panels - According to an exemplary embodiment, a driver circuit for generating a reset pulse of an output waveform includes a plurality of ramp paths, each ramp path being configured to control the slope of the reset pulse. The driver circuit also includes a falling switch configured to selectively hold the output waveform low. The driver circuit further includes a switch controller for selectively enabling the plurality of ramp paths and the falling switch to generate the reset pulse. The switch controller can selectively enable the plurality of ramp paths responsive to a reference setting signal to select the slope of the reset pulse. The driver circuit can also generate a sustain pulse. The driver circuit is can generate the reset pulse and the sustain pulse by driving a transistor. | 08-09-2012 |
20120200275 | Integrated High-Voltage Power Supply Start-Up Circuit - According to an exemplary embodiment, an integrated start-up circuit for a power supply includes a converter, which in one embodiment can be a buck converter. In one embodiment, the buck converter includes a gate driver configured to drive a power switch, where the power switch is coupled across a DC bus node and a switching node of the buck converter. The power switch is configured to provide a start-up voltage to the buck converter from the DC bus node during start-up of the buck converter. In one embodiment, the buck converter includes a bootstrap switch coupled across the gate driver and a Vcc node and a Schottky diode coupled across the bootstrap switch and the switching node, where the start-up voltage is provided at the Vcc node through the bootstrap switch. | 08-09-2012 |
20120194170 | Load Detection for Switched-Mode Power Converters - In one embodiment, a method for detecting a load in a switched-mode power converter is provided. The switched-mode power converter includes high and low-side power switches which are configured to be driven respectively by high and low-side drive signals to provide a switching voltage. The high and low-side drive signals include a plurality of dead-time periods. The method includes monitoring a waveform of the switching voltage and at least one of the high and low-side drive signals. The monitored waveform of the switching voltage is compared to the monitored waveform of the at least one of the high and low-side drive signals to determine whether the switching voltage is high or low during at least one of the dead-time periods. A current measurement of the load is determined based on whether the switching voltage is high or low during the at least one of the dead-time periods. | 08-02-2012 |
20120187928 | Synchronous Buck Converter Including Multi-Mode Control for Light Load Efficiency and Related Method - According to one embodiment, a synchronous buck converter comprises a multi-mode control circuit for detecting a load condition of a variable load, an output stage driven by the multi-mode control circuit, wherein the variable load is coupled to the output stage, and a feedback circuit connected between the output stage and the multi-mode control circuit. The multi-mode control circuit is configured to adjust a current provided by the output stage to the variable load based on the load condition. In one embodiment, the multi-mode control circuit selectably uses one of at least a first control mode and a second control mode according to the load condition, wherein the first control mode is a pulse-width modulation (PWM) mode selected for switching efficiency when the load condition is heavy and the second control mode is an adaptive ON-time (AOT) mode selected for switching efficiency when the load condition is light. | 07-26-2012 |
20120181681 | Stacked Half-Bridge Package with a Current Carrying Layer - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source. | 07-19-2012 |
20120181674 | Stacked Half-Bridge Package with a Common Conductive Leadframe - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. | 07-19-2012 |
20120181624 | Stacked Half-Bridge Package with a Common Conductive Clip - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe. | 07-19-2012 |
20120175688 | Semiconductor Package with Reduced On-Resistance and Top Metal Spreading Resistance with Application to Power Transistor Packaging - Some exemplary embodiments of a semiconductor package including a semiconductor device having electrodes on opposite major surfaces connectable to a planar support surface without a bondwire and a control electrode disposed in a corner position for reducing top-metal spreading resistance and device on-resistance have been disclosed. One exemplary structure comprises a semiconductor device having a first major surface including a first electrode and a second major surface including a second electrode and a control electrode, wherein the control electrode is disposed in a corner of the second major surface, and wherein the first electrode, the second electrode, and the control electrode are electrically connectable to a planar support surface without a bondwire. The pads of the device may be arranged in a balanced grid to maintain device stability during integration. A minimum gap distance between die pads allows the placement of vias in the planar support surface. | 07-12-2012 |
20120168926 | High Power Semiconductor Package with Conductive Clip and Flip Chip Driver IC with Integrated Control Transistor - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages. Moreover, by integrating only the control transistor rather than both the control and sync transistor within the flip chip driver IC, the sync transistor may remain separate, simplifying manufacture and providing greater total surface area for thermal dissipation. | 07-05-2012 |
20120168925 | High Power Semiconductor Package with Conductive Clips and Flip Chip Driver IC - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168924 | High Power Semiconductor Package with Multiple Conductive Clips - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168923 | High Power Semiconductor Package with Conductive Clip on Multiple Transistors - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168922 | High Power Semiconductor Package with Conductive Clip - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120153351 | Stress modulated group III-V semiconductor device and related method - According to one embodiment, a group III-V semiconductor device comprises a compositionally graded body disposed over a substrate and below a buffer layer supporting an active area of the group III-V semiconductor device. The compositionally graded body includes a first region applying compressive stress to the substrate. The compositionally graded body further includes a stress modulating region over the first region, where the stress modulating region applies tensile stress to the substrate. In one embodiment, a method for fabricating a group III-V semiconductor device comprises providing a substrate for the group III-V semiconductor device and forming a first region of a compositionally graded body over the substrate to apply compressive stress to the substrate. The method further comprises forming a stress modulating region of the compositionally graded body over the first region, where the stress modulating region applies tensile stress to the substrate. | 06-21-2012 |
20120146205 | Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Semiconductor Package Utilizing a Leadframe for Electrical Interconnections - Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes. | 06-14-2012 |
20120104586 | Direct Contact Flip Chip Package with Power Transistors - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 05-03-2012 |
20120025713 | System using shunt circuits to selectively bypass open loads - According to an exemplary embodiment, a shunt circuit includes a floating shunt switch configured to bypass at least one load, for example at least one LED, among a plurality of series-connected loads, such as a plurality of series-connected LEDs in a lighting system, responsive to a high-side control signal. The at least one load has terminals connected across the shunt circuit. The shunt circuit further includes a high-voltage level-shift up circuit configured to shift a low-side control signal up to the high-side control signal using a voltage of at least one of the terminals of the at least one load. The floating shunt switch can be configured to bypass the at least one load responsive to a failure of the at least one load. | 02-02-2012 |
20110284950 | Method for fabricating a shallow and narrow trench FETand related structures - Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed. | 11-24-2011 |