| INTERNATIONAL RECTIFIER CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20120104586 | Direct Contact Flip Chip Package with Power Transistors - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 05-03-2012 |
| 20120025713 | System using shunt circuits to selectively bypass open loads - According to an exemplary embodiment, a shunt circuit includes a floating shunt switch configured to bypass at least one load, for example at least one LED, among a plurality of series-connected loads, such as a plurality of series-connected LEDs in a lighting system, responsive to a high-side control signal. The at least one load has terminals connected across the shunt circuit. The shunt circuit further includes a high-voltage level-shift up circuit configured to shift a low-side control signal up to the high-side control signal using a voltage of at least one of the terminals of the at least one load. The floating shunt switch can be configured to bypass the at least one load responsive to a failure of the at least one load. | 02-02-2012 |
| 20110284950 | Method for fabricating a shallow and narrow trench FETand related structures - Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed. | 11-24-2011 |
| 20110284862 | III-nitride switching device with an emulated diode - Some exemplary embodiments of a III-nitride switching device with an emulated diode have been disclosed. One exemplary embodiment comprises a GaN switching device fabricated on a substrate comprising a high threshold GaN transistor coupled across a low threshold GaN transistor, wherein a gate and a source of the low threshold GaN transistor are shorted with an interconnect metal to function as a parallel diode in a reverse mode. The high threshold GaN transistor is configured to provide noise immunity for the GaN switching device when in a forward mode. The high threshold GaN transistor and the low threshold GaN transistor are typically fabricated on the same substrate, and with significantly different thresholds. As a result, the superior switching characteristics of III-nitride devices may be leveraged while retaining the functionality and the monolithic structure of the inherent body diode in traditional silicon FETs. | 11-24-2011 |
| 20110278711 | Leadless Package for High Current Devices - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 11-17-2011 |
| 20110278710 | Direct Contact Leadless Package - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 11-17-2011 |
| 20110272759 | Vertical LDMOS device and method for fabricating same - A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body. | 11-10-2011 |
| 20110260668 | Low frequency drive control circuit and method for driving an inductive load - According to one embodiment, a low frequency drive control circuit for use with an inductive load comprises a comparator configured to receive a high frequency signal at a first input and a smoothly varying low frequency signal for modulating the high frequency signal at a second input. The comparator is further configured to produce a pulse width modulated output of the low frequency drive control circuit for use in generating a smoothly varying low frequency load current in the inductive load. In one embodiment, the inductive load can comprise a DC brushed motor. In one embodiment, the low frequency drive control circuit can be implemented as part of an integrated circuit further comprising a switching circuit configured to use the pulse width modulated output of the comparator to generate the smoothly varying low frequency load current, which may be a substantially sinusoidal load current, for example. | 10-27-2011 |
| 20110260322 | "Semiconductor on semiconductor substrate multi-chip-scale package" - Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT. | 10-27-2011 |
| 20110227090 | Programmable III-Nitride Transistor with Aluminum-Doped Gate - Disclosed is a III-nitride heterojunction device that includes a conduction channel having a two dimensional electron gas formed at an interface between a first III-nitride material and a second III-nitride material. A modification including a contact insulator, for example, a gate insulator formed under a gate contact, is disposed over the conduction channel, wherein the contact insulator includes aluminum to alter formation of the two dimensional electron gas at the interface. The contact insulator can include AlSiN, or can be SiN doped with aluminum. The modification results in programming the threshold voltage of the III-nitride heterojunction device to, for example, make the device an enhancement mode device. The modification can further include a recess, an ion implanted region, a diffused region, an oxidation region, and/or a nitridation region. In one embodiment, the first III-nitride material comprises GaN and the second III-nitride material comprises AlGaN. | 09-22-2011 |
| 20110210338 | Efficient High Voltage Switching Circuits and Monolithic Integration of Same - A high voltage switching circuit includes first and second group III-V transistors, the second group III-V transistor having a greater breakdown voltage than the first group III-V transistor. The circuit further includes a silicon diode in a parallel arrangement with the first group III-V transistor, the parallel arrangement being in cascade with the second group III-V transistor. The circuit is effectively a three-terminal device, where a first terminal is coupled to a gate of the second III-V transistor, a source of the first III-V transistor, and an anode of the silicon diode. A second terminal is coupled to a gate of the first group III-V transistor, and a third terminal is coupled to a drain of the second group III-V transistor. The first group III-V transistor might be an enhancement mode transistor. The second group III-V transistor might be a depletion mode transistor. The first and second group III-V transistors can be GaN HEMTs. | 09-01-2011 |
| 20110210337 | Monolithic integration of silicon and group III-V devices - Disclosed is a monolithically integrated silicon and group III-V device that includes a group III-V transistor formed in a III-V semiconductor body disposed over a silicon substrate. At least one via extends through the III-V semiconductor body to couple at least one terminal of the group III-V transistor to a silicon device formed in the silicon substrate. The silicon device can be a Schottky diode, and the group III-V transistor can be a GaN HEMT. In one embodiment an anode of the Schottky diode is formed in the silicon substrate. In another embodiment, the anode of the Schottky diode is formed in a lightly doped epitaxial silicon layer atop the silicon substrate. In one embodiment a parallel combination of the Schottky diode and the group III-V transistor is formed, while in another embodiment is series combination is formed. | 09-01-2011 |
| 20110198611 | III-Nitride Power Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson. | 08-18-2011 |
| 20110163373 | Semiconductor device including a voltage controlled termination structure and method for fabricating same - According to one embodiment, a semiconductor device including a voltage controlled termination structure comprises an active area including a base region of a first conductivity type formed in a semiconductor body of a second conductivity type formed over a first major surface of a substrate of the second conductivity type, a termination region formed in the semiconductor body adjacent the active area and including the voltage controlled termination structure. The voltage controlled termination structure includes an electrode electrically connected to a terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a gate terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a source terminal of the semiconductor device. | 07-07-2011 |
| 20110157949 | Highly Efficient III-Nitride Power Conversion Circuit - According to an exemplary embodiment, a III-nitride power conversion circuit includes a gate driver having a plurality of cascaded inverters, each of the plurality of cascaded inverters including at least one III-nitride transistor. At least one of the plurality of cascaded inverters has a cutoff switch and a III-nitride depletion mode load where the cutoff switch is configured to disconnect the III-nitride depletion mode load so as to prevent current from flowing from a supply voltage of the at least one of the plurality of cascaded inverters. The cutoff switch of the at least one of the plurality of cascaded inverters can be driven by one of the plurality of cascaded inverters. The III-nitride power conversion circuit can also include an output driver driven by the gate driver where the output driver has a segmented III-nitride transistor. Furthermore, a selector circuit can be configured to selectively disable at least one segment of the segmented III-nitride transistor. | 06-30-2011 |
| 20110140176 | Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 06-16-2011 |
| 20110140169 | Highly conductive source/drain contacts in III-nitride transistors - In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed. | 06-16-2011 |
| 20110136325 | Method for fabricating a monolithic integrated composite group III-V and group IV semiconductor device - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT). | 06-09-2011 |
| 20110134576 | Power delivery circuit having protection switch for reverse battery condition - According to one disclosed embodiment, a power delivery circuit includes a switch for protection of a load in a reverse battery condition. The load is coupled in cascade with the protection switch, where the protection switch disconnects the load from the battery in the reverse battery condition. The protection switch does not include p-n junction diodes present in conventional protection switches using FETs. The protection switch utilizes, for example, a GaN HEMT, that does not include a p-n junction diode. Thus, the threat of internal conduction in the protection switch during a reverse battery condition is eliminated. The power delivery circuit also protects the load in a load dump condition. | 06-09-2011 |
| 20110133251 | Gated algan/gan heterojunction schottky device - Some exemplary embodiments of a semiconductor device using a III-nitride heterojunction and a novel Schottky structure and related method resulting in such a semiconductor device, suitable for high voltage circuit designs, have been disclosed. One exemplary structure comprises a first layer comprising a first III-nitride material, a second layer comprising a second III-nitride material forming a heterojunction with said first layer to generate a two dimensional electron gas (2DEG) within said first layer, an anode comprising at least a first metal section forming a Schottky contact on a surface of said second layer, a cathode forming an ohmic contact on said surface of said second layer, a field dielectric layer on said surface of said second layer for isolating said anode and said cathode, and an insulating material on said surface of said second layer and in contact with said anode. | 06-09-2011 |
| 20110121313 | Enhancement Mode III-Nitride Transistors with Single Gate Dielectric Structure - According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge. | 05-26-2011 |
| 20110101880 | Driver circuit with an increased power factor - According to one exemplary embodiment, driver circuit coupled between an AC line and a load includes a first semiconductor switch interposed between a bus voltage and a resonant circuit and a second semiconductor switch interposed between the resonant circuit and a ground, where the resonant circuit drives the load. In the driver circuit, the bus voltage has a shape substantially corresponding to a shape of a rectified AC line voltage, thereby increasing a power factor of the driver circuit. The driver circuit can further include a full-bridge rectifier disposed between the resonant circuit and the load. The load can include at least one LED. | 05-05-2011 |
| 20110084311 | Group III-V semiconductor device with strain-relieving interlayers - According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer. | 04-14-2011 |
| 20110080156 | DC/DC converter with depletion-mode III-nitride switches - Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up. | 04-07-2011 |
| 20110057300 | Direct contact leadless flip chip package for high current devices - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 03-10-2011 |
| 20110049720 | Refractory metal nitride capped electrical contact and method for frabricating same - According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device. | 03-03-2011 |
| 20110049690 | Direct contract leadless package for high current devices - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 03-03-2011 |
| 20110049569 | Semiconductor structure including a field modulation body and method for fabricating same - According to one embodiment, a semiconductor structure including an equipotential field modulation body comprises a trench surrounding an active region of a group III-V power device fabricated in the semiconductor structure, and the equipotential field modulation body formed in the trench and extending over a portion of the active region. The equipotential field modulation body is electrically coupled to a terminal of the group III-V power device. In one embodiment, a method for fabricating a semiconductor structure including an equipotential field modulation body comprises fabricating a trench surrounding an active region of the semiconductor structure, forming the equipotential field modulation body in the trench, the equipotential field modulation body extending over a portion of the active region, and electrically coupling the equipotential field modulation body to a terminal of a group III-V power device fabricated in the active region. | 03-03-2011 |
| 20100314695 | Self-aligned vertical group III-V transistor and method for fabricated same - In one embodiment a self-aligned vertical group III-V transistor comprises a group III-V layer having a first conductivity type formed over a group III-V drift body having a second conductivity type opposite the first conductivity type, a pinch-off region formed by dopant implantation of the group III-V layer. The pinch-off region is doped so as to have the second conductivity type, and extends through the group III-V layer to the group III-V drift body. The self-aligned vertical group III-V transistor also comprises a pinch-off insulation body formed over the pinch-off region, the pinch-off region and the pinch-off insulation body being self-aligned. In one embodiment, the present invention may take the form of a self-aligned vertical N-channel field-effect transistor (FET) in gallium nitride GaN. | 12-16-2010 |
| 20100308375 | Rare earth enhanced high electron mobility transistor and method for fabricating same - According to one embodiment, a high electron mobility transistor (HEMT) comprises an insulator layer comprising a first group III-V intrinsic layer doped with a rare earth additive. The HEMT also comprises a second group III-V intrinsic layer formed over the insulator layer, and a group III-V semiconductor layer formed over the second group III-V intrinsic layer. In one embodiment, a method for fabricating a HEMT comprises forming a first group III-V intrinsic layer and doping the first group III-V intrinsic layer with a rare earth additive to produce an insulator layer. The method also comprises forming a second group III-V intrinsic layer over the insulator layer, and further forming a group III-V semiconductor layer over the second group III-V intrinsic layer. A two-dimensional electron gas (2DEG) is formed at a heterojunction interface of the group III-V semiconductor layer and the second group III-V intrinsic layer. | 12-09-2010 |
| 20100301396 | Monolithic Vertically Integrated Composite Group III-V and Group IV Semiconductor Deviceand Method for Fabricating same - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT). | 12-02-2010 |
| 20100259186 | Buck converter with III-nitride switch for substantially increased input-to-output voltage ratio - According to one exemplary embodiment, a buck converter for converting a high voltage at an input of the buck converter to a low voltage at an output of the buck converter includes a III-nitride switch interposed between the input and the output of the buck converter and a low resistance switch interposed between the output of the buck converter and a ground. The buck converter further includes a control circuit configured to control a duty cycle of the III-nitride switch. The III-nitride switch has a sufficiently high switching speed so as to allow a ratio of the input high voltage to the output low voltage of the buck converter to be substantially greater than 10. | 10-14-2010 |
| 20100171126 | In situ dopant implantation and growth of a Ill-nitride semiconductor body - In one embodiment a method enabling in situ dopant implantation during growth of a III-nitride semiconductor body, comprises establishing a growth environment for the III-nitride semiconductor body in a composite III-nitride chamber having a dopant implanter and a growth chamber, growing the III-nitride semiconductor body in the growth chamber, and implanting the III-nitride semiconductor body in situ in the growth chamber using the dopant implanter. A semiconductor device produced using the disclosed method comprises a III-nitride semiconductor body having a first conductivity type formed over a support substrate, and at least one doped region produced by in situ dopant implantation of the III-nitride semiconductor body during its growth, that at least one doped region having a second conductivity type. | 07-08-2010 |
| 20100096668 | High voltage durability III-Nitride semiconductor device - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT. | 04-22-2010 |
| 20100090608 | END-OF-LAMP LIFE DETECTION CIRCUIT - An end of life (EOL) detection circuit for a gas discharge lamp. The circuit includes a comparator for comparing an input voltage to first and second threshold voltages and providing an EOL signal; a sensing circuit for sensing a DC offset in the lamp-voltage during the EOL of the lamp; and a reference voltage setting circuit responsive to the DC offset including a reference diode for setting an adjustable reference voltage as said input voltage to the comparator. | 04-15-2010 |
| 20100065856 | Semiconductor package with integrated passives and method for fabricating same - According to one disclosed embodiment, a semiconductor package for integrated passives and a semiconductor device comprises a high permeability structure formed over a surface of the semiconductor package and surrounding a contact body of the semiconductor package, the contact body being connected to an output of the semiconductor device. The contact body can be, for example, a solder bump. The high permeability structure causes a substantial increase in inductance of the contact body so as to form an increased inductance inductor coupled to the output of the semiconductor device. In one embodiment, the semiconductor package further comprises a blanket insulator formed over the high permeability structure, and a capacitor stack formed over the blanket insulator. In one embodiment, the semiconductor device comprises a group III-V power semiconductor device. | 03-18-2010 |
| 20100033261 | MINIMUM PULSE WIDTH FOR PULSE WIDTH MODULATION CONTROL - The rising edge of a pulse width modulated output signal occurs after an input ramp signal starts to rise. The ramp signal starts to rise after the rising edge of a periodic set signal and before the falling edge of a periodic set signal. A feedback control signal intersects a substantially linear region of the ramp signal to generate a reset signal using a PWM comparator. The periodic set signal and reset signal are input to a latching circuit to generate the pulse width modulated output signal. The minimum pulse width can approach zero while having adequate overdrive to the PWM comparator. Having the rising edge of the reset signal rise before the falling edge of the set signal can allow a zero percent duty cycle without the need for a ramp offset voltage. | 02-11-2010 |
| 20100001706 | CONVERTER HAVING PWM RAMP ADJUSTABLE IN DISCONTINUOUS MODE OPERATION - A ramp adjustment circuit for a voltage converter including a gate driver for controlling series connected high- and low-side switches connected across DC voltage and coupled at an output node connected to a load through an inductor such that the converter operates in a continuous conduction mode (CCM) or a discontinuous conduction mode (DCM). The circuit includes a first current generating circuit for providing a first current signal for generating a first ramp signal; a second current generating circuit for providing a second reduced current signal for generating a second ramp signal having a reduced slope when the first current generating circuit is disabled and the second current generating circuit is enabled; and a circuit for enabling the first current generating circuit and disabling the second current generating circuit when the converter is in CCM and enabling the second current generating circuit and disabling the first current generating circuit when the converter is in DCM thereby providing the first current signal when the converter is in CCM to provide the first ramp signal and providing the second reduced current signal when the converter is in DCM to provide the second reduced slope ramp signal. | 01-07-2010 |
| 20090273330 | MERGED RAMP/OSCILLATOR FOR PRECISE RAMP CONTROL IN ONE CYCLE PFC CONVERTER - A one cycle power factor correction converter circuit comprising a switch for controlling a DC output voltage of the converter circuit, the switch being switched by a drive signal having a frequency determined by a clock signal; the converter circuit being provided with a DC input voltage and producing the DC output voltage, the DC input voltage being rectified from an AC input; a controller circuit for controlling an on-time or off-time of the switch to set the output voltage and to achieve power factor correction at the AC input; the controller circuit comprising an error amplifier receiving a feedback voltage from the output of the converter circuit and a reference voltage and producing an error signal; a ramp generator receiving the error signal and generating a first ramp signal by integrating a signal related to the error signal; a pulse width modulation circuit receiving the first ramp signal and a signal related to the error signal and producing a pulse width modulated signal by comparing the first ramp signal and the signal related to the error signal; the pulse width modulated signal determining the on-time or off-time of the switch to control the output voltage with power factor correction; further comprising a circuit for terminating the first ramp signal when a predetermined inequality exists between the first ramp signal and a reference signal and for developing the clock signal from the first ramp signal. | 11-05-2009 |
| 20090207883 | PRECISION TEMPERATURE SENSOR - A temperature sensor circuit in accordance with an embodiment of the present invention includes a temperature sensing element operable to provide a temperature voltage that is linearly related to the absolute temperature of the circuit. The temperature sensing element includes a first bi-polar junction transistor and a second bipolar junction transistor connected between a supply voltage and a common ground, wherein the base of first bipolar junction transistor is connected to the base of the second bipolar junction transistor, a first resistor connected between an emitter of the first bipolar junction transistor and the common ground and a second resistor connected between the common ground and a first node, wherein the temperature voltage is provided to the first node across the second resistor. The temperature sensor circuit also includes a current supply element operable to supply a common current to a collector of the first bipolar junction transistor, the second bipolar junction transistor and to the second resistor, respectively, an early voltage element operable to compensate for variations in voltage, a base current element operable to provide a steady base current to the bases of the first and second bipolar junction transistors, a channel modulation element operable to compensate for channel modulation and a leakage element operable to compensate for epi-substrate leakage between the circuit and a substrate on which it is formed. | 08-20-2009 |
| 20090174341 | COLD-CATHODE FLUORESCENT LAMP (CCFL) CURRENT CONTROL CIRCUIT - A circuit to control an AC lamp current provided by an input AC voltage supply to a cold-cathode fluorescent lamp (CCFL). The circuit includes a capacitor connected in series between the AC voltage supply and one terminal of the CCFL, the capacitor biasing the CCFL with the AC lamp current; a switch having first, second, and control terminals, the first terminal being connected to the CCFL and the second terminal being connected to the other side of the supply; a diode connected in parallel to the switch; and a resistor connected in parallel to the diode, wherein the AC lamp current is controlled by controlling the switch to add and remove resistance in series with the CCFL. | 07-09-2009 |
| 20090108829 | CONTROL INTEGRATED CIRCUIT WITH COMBINED OUTPUT AND INPUT - A control circuit for a voltage converter including a power switch for providing power to a load in accordance with an embodiment of the present application includes a driver circuit operable to provide a first control signal to the power switch to turn the power switch on and off such that a desired voltage is provided to the load, an output terminal connected to the driver circuit and operable to connect the driver circuit to the power switch; and a controller operable to control the driver circuit. The output terminal operates as an input terminal to receive external data under predetermined conditions, and the controller controls the driver circuit based on the external data. | 04-30-2009 |
| 20090102488 | GROUND FAULT DETECTION CIRCUIT FOR USE IN HIGH VOLTAGE MOTOR DRIVE APPLICATIONS - An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal. | 04-23-2009 |
| 20090096289 | INTERPOSER FOR AN INTEGRATED DC-DC CONVERTER - An interposer electrical interface for placing a DC-DC converter in close proximity with an IC powered by the converter, the DC-DC converter including at least one switching node power supply stage, the at least one switching node power supply stage providing regulated power to the IC, the close proximity of the DC-DC converter and IC allowing for high efficiency in provision of the regulated power from the DC-DC converter to the IC, the interposer electrical interface comprising at least one electrical energy storage element. | 04-16-2009 |
| 20090066523 | SWITCHED MODE POWER CONVERTER WITH OVER TEMPERATURE DETECTION - An over temperature detector circuit for use in a switching converter including one or more power switches in accordance with an embodiment of the present application includes a silent sense generator connected to at least one power switch and operable to detect a noise level of the switch and to provide a generator output signal indicative of absence of switching noise and a comparator operable to compare a temperature sensor signal from a temperature sensor with a reference voltage to provide an alarm signal indicating an over temperature condition when the temperature sensor signal exceeds the reference voltage, wherein the alarm signal does not indicate an over temperature condition when the generator output signal does not indicate absence of switching noise | 03-12-2009 |
| 20090051225 | GATE DRIVING SCHEME FOR DEPLETION MODE DEVICES IN BUCK CONVERTERS - A circuit for driving a switching stage including control and sync switches series connected at a switching node, at least one of the control and sync switches being a normal ON depletion mode device, the circuit comprising a gate driver including first and second switching stages for generating gate drive signals for the sync and control switches, respectively, the first switching stage having a first driver output node and the second switching stage having a second driver output node, a signal from the first node driving the sync switch and a signal from the second node driving the control switch and a circuit connected to the first and second switching stages, the circuit including a first circuit providing a first voltage source, the first circuit being coupled to the first switching stage and to the sync switch, a first bias voltage from the first voltage source being switched by the first switching stage, the first switching stage having a first state wherein the sync switch is on, and a second state wherein the first bias voltage is switched to the gate of the sync switch to turn the sync switch off and a second circuit including a first energy storage device for charging with a second bias voltage, the second switching circuit having a first state, wherein the control switch is on when the sync switch is off and having a second state wherein the control switch is switched off when the sync switch is on by switching the second bias voltage to the gate of the control switch. | 02-26-2009 |
| 20090045868 | DOUBLE STAGE COMPACT CHARGE PUMP CIRCUIT - A charge pump circuit comprising a plurality of charge pumps each having their outputs connected in parallel, each charge pump receiving a plurality of clock signals, a clock signal oscillator for providing the plurality of clock signals, the clock signals being out of phase, each charge pump having an output (VCP) that is coupled to the output of the at least one other charge pump, further comprising a first capacitor in each charge pump, the first capacitor being charged by a switching circuit receiving the clock signals to charge the first capacitor to a voltage between a supply voltage and a reference potential, and further comprising a second capacitor coupled in series with the first capacitor, the second capacitor provided between a first terminal (IN) of the charge pump and a second terminal (OUT) of the charge pump, wherein the first terminal (IN) of the charge pump is connected to a second terminal (OUT) of another charge pump and the second terminal (OUT) of the charge pump is connected to the first terminal (IN) of another charge pump, and wherein when the first capacitor is charged by the switching circuit, the second capacitor is charged by its connection to another charge pump, the switching circuit connecting a first terminal of the first capacitor to the supply voltage thereby elevating a second terminal of the first capacitor to an elevated voltage, the second terminal of the first capacitor being connected to a first terminal of the second capacitor, and thereby elevating a second terminal of the second capacitor to a further elevated voltage elevated above the elevated voltage on the first capacitor, the further elevated voltage on the second terminal of the second capacitor being provided to the charge pump output. | 02-19-2009 |
| 20090039817 | AUDIBLE NOISE REDUCTION FOR SINGLE CURRENT SHUNT PLATFORM - A method for reducing audible motor noise in a motor drive, wherein the motor drive includes a motor controller driving a PWM space vector modulator providing gating pulses to an inverter providing phase currents to the phase windings of the motor, and wherein phase currents of the motor are determined by taking samples of the DC link current in a DC link powering the inverter. The method comprises determining the speed of the motor and comparing the speed to a preset threshold, the preset threshold defining a speed at which audible noise is generated by the motor due to a minimum pulse constraint being imposed on the motor phase currents in order to reliably sample the DC link current to measure the phase current. If the speed is below the threshold, the DC link current in the DC link is sampled using a reduced number of current samples for a PWM cycle of the PWM space vector modulator to reduce audible motor noise. | 02-12-2009 |
| 20090015331 | CURRENT SENSE AMPLIFIER FOR VOLTAGE CONVERTER - A variable gain amplifier comprising a differential input amplifier comprising a pair of transistors each having an input across which an input voltage is provided, the transistors being coupled such that each transistor is provided in series with a respective current source providing a reference current and whereby a current is developed across a resistor element coupling the transistors that is proportional to the voltage between the inputs; further comprising further transistors each coupled in series with a transistor of the transistor pair, and wherein the further transistors are arranged such that a current is developed in each further transistor due to the voltage provided across the inputs that is substantially equal to, in one further transistor, a sum of the reference current and the current in the resistor element, and in the other further transistor, a difference between the reference current and the current in the resistor element; further comprising a gain stage for developing currents equal to a gain factor multiplied by the sum and difference currents and for developing an output signal proportional to the gain factor multiplied by the current through the resistor element; further comprising an interface for selectively providing a signal proportional to a variable across the inputs of the differential amplifier to drive the output signal to an output value; and a gain setting circuit responsive to the output value that produces a gain setting signal to adjust the gain of the variable gain amplifier. | 01-15-2009 |
| 20090009254 | CURRENT SENSE AMPLIFIER FOR VOLTAGE CONVERTER - A thermal calibration circuit for adjusting the gain of a variable gain amplifier, the thermal calibration circuit comprising an interface for receiving a signal that varies with temperature and for providing a signal related to the variation of the temperature; a variable gain amplifier having an input and an output; the signal related to the variation of the temperature being selectively coupled to the input; a circuit at the output of the variable gain amplifier for developing a first current proportional to a difference between a current developed at the output of the variable gain amplifier and a reference current; and the first circuit driving a further circuit to produce a gain control signal for adjusting the gain of the variable gain amplifier. | 01-08-2009 |
| 20090002060 | NEGATIVE N-EPI BIASING SENSING AND HIGH SIDE GATE DRIVER OUTPUT SPURIOUS TURN-ON PREVENTION DUE TO N-EPI P-SUB DIODE CONDUCTION DURING N-EPI NEGATIVE TRANSIENT VOLTAGE - A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device. The high-side driver including first and second complementary switched MOSFET series connected at a high-side node, driving the high-side power switching device, one of the MOSFETs having a parasitic bipolar transistor formed between the substrate, an N+ epitaxial region connected to the high-side driver supply voltage and the switched node, with the parasitic transistor having a base electrode formed by the N+ epitaxial region, an emitter electrode formed by the substrate and a collector electrode formed by the switched node, such that if a transient voltage that is negative with respect to the substrate is present at the high-side driver supply voltage, the parasitic transistor will conduct a short circuit current between the switched node and the substrate; a first circuit for controlling the conduction of the first and second MOSFETs to switch the high-side switching device ON and OFF; a diffusion in the N+ epitaxial region in which a terminal connected to the switched node is provided by the diffusion forming the collector of the parasitic transistor; and a second circuit coupled to the diffusion for sensing the high-side driver supply voltage at the epitaxial region and providing a signal to the controller circuit to prevent turn-ON of the high-side power switching device. | 01-01-2009 |
| 20080298455 | CLOCK GENERATOR INCLUDING A RING OSCILLATOR WITH PRECISE FREQUENCY CONTROL - A clock generator for providing a desired system clock signal in accordance with an embodiment of the present application includes a ring oscillator operable to provide an oscillator output signal having a first frequency, a divider operable to divide the oscillator output signal by a predetermined divisor and to output the divided signal as the desired system clock signal, a reference device operable to provide a reference signal with a known second frequency and a ratio device operable to provide a ratio value indicative of a relationship between the oscillator output signal and the reference signal, wherein the predetermined divisor of the divider is determined based on the ratio value such that the desired system clock signal has a desired frequency. | 12-04-2008 |
| 20080298101 | INTELLIGENT DEAD TIME CONTROL - A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit including a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to achieve minimal power loss. | 12-04-2008 |
| 20080297248 | CLASS D AMPLIFIER CIRCUIT WITH BI-DIRECTIONAL POWER SWITCH - A Class D amplifier circuit in accordance with an embodiment of the present application includes a converter stage operable to provide a desired AC voltage and a Class D amplifier stage, connected to the converter stage. The Class D amplifier stage includes a first bi-directional switch connected to the converter stage, a second bi-directional switch, connected in series with the first bi-directional switch, wherein the first and second bi-directional switches are connected across the desired AC voltage provided by the converter stage and a controller operable to turn the first and second bi-directional switches ON and OFF such that a desired voltage is provided at a midpoint node positioned between the first bi-directional switch and the second bi-directional switch. | 12-04-2008 |
| 20080297223 | LEVEL SHIFT CIRCUIT WITH IMPROVED DV/DT SENSING AND NOISE BLOCKING - A level shift circuit in accordance with the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. A dv/dt sensing circuit is provided to detect any slew in offset between negative supply voltages and ground in a circuit. This detection is used to control a noise canceling circuit to ensure that noise that results from that offset is not propagated to the output of the level shift circuit. A parasitic emulator is preferably used to provide dv/dt sensing. The output of the parasitic emulator is used to activate a noise canceling circuit to prevent noise from reaching the output terminal of the level shift circuit. | 12-04-2008 |
| 20080297212 | START-UP CIRCUITY FOR PROVIDING A START-UP VOLTAGE TO AN APPLICATION CIRCUIT - A startup circuit for providing a startup voltage from a high voltage DC bus voltage to an application circuit, the startup circuit comprising an integrated circuit package for at least a control circuit for driving at least one power switch of the application circuit having a low voltage terminal; a dropping resistor in the integrated circuit package having a first terminal for coupling to the high voltage DC bus and a second terminal, the dropping resistor dropping the high voltage DC bus voltage to a reduced voltage and providing the reduced voltage at the second terminal; further comprising a low voltage regulator coupled to the second terminal for using the reduced voltage for enabling generation of a regulated startup low voltage DC output at a preset level at the low voltage terminal for powering at least one part of the application circuit during startup of the application circuit, wherein the high voltage DC bus voltage is the only voltage source provided externally to the integrated circuit package. | 12-04-2008 |
| 20080278985 | BI-DIRECTIONAL HEMT/GaN HALF-BRIDGE CIRCUIT - A half-bridge circuit in accordance with an embodiment of the present application includes an input voltage terminal operable to receive an input voltage, a first bi-directional switch, a second bi-directional switch connected in series with the first bi-directional switch, wherein the first and second bi-directional switches are connected to the input voltage terminal such that the input voltage is provided across the first and second bi-directional switches and a controller operable to turn the first and second bi-directional switches ON and OFF such that a desired voltage is provided at an midpoint node positioned between the first bi-directional switch and the second bi-directional switch. The first bi-directional switch and the second bi-directional switch are high electron mobility transistors structured to allow for conduction in two directions when ON and to prevent conduction in any direction when OFF. | 11-13-2008 |
| 20080278213 | HIGH OHMIC INTEGRATED RESISTOR WITH IMPROVED LINEARITY - An integrated circuit that includes a resistor module with improved linearity is disclosed. The resistor module includes a diffused resistor body of a first conductivity type; a first terminal and a second terminal, each making direct electrical contact with the diffused resistor body; a doped well of a second conductivity type substantially surrounding the diffused resistor body on all but one major surface of the diffused resistor body, the doped well having contact regions; a first amplifier connected to the first terminal and to one contact region of the doped well; and a second amplifier connected to the second terminal and to another contact region of the well, such that the first amplifier and the second amplifier are connected for power supply only to the first terminal and second terminal, respectively. The first and second amplifiers may be unity gain buffer amplifiers or inverting opamps. | 11-13-2008 |
| 20080266043 | PLANAR TRANSFORMER ARRANGEMENT - A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings. | 10-30-2008 |
| 20080265817 | SENSORLESS SPEED DETECTION DURING ZERO VECTOR - A speed estimation method for determining the speed of a sensorless permanent magnet brushless motor having one or more phases driven by one or more stages of an inverter, each stage including high- and low-switches connected in series across a DC Bus and having a respective common switched node, the respective switched node being coupled to a respective motor phase terminal. The method includes the steps of applying an alternating sequence of Zero Vectors to the inverter, the sequence alternating between a first Zero Vector whereby motor current does not flow in the DC Bus and a second Zero Vector wherein the high and low side switches of the inverter are alternately turned on with active vector components being injected by the inverter for each inverter stage thereby to allow motor current to flow in the DC Bus, whereby the terminals of the motor during the first and second Zero Vectors are shorted to brake the motor without substantially raising the voltage of the DC Bus during the braking time; and the speed of the motor can be determined by measuring the current in a sensor of the DC bus during the time when the second Zero Vector is applied without using a sensor in the motor. | 10-30-2008 |
| 20080265815 | HARMONIC PROCESSOR - A harmonic processor receiving an input signal and providing an output signal, the input signal comprising a first analog signal having amplitude, frequency and phase components and being converted to an instantaneous magnitude output signal, or the input signal comprising an instantaneous magnitude signal for inverse conversion to an output analog signal having amplitude, frequency and phase components, comprising a first component comprising a resistive plane, the first component having a first zone and a second zone, the first zone comprising a first set of first electrodes contacting the resistive plane at first defined locations and the second zone comprising a second set of electrodes contacting the resistive plane at second defined locations; the first electrodes comprising a first subset of first electrodes permanently connected to external terminals; and a second subset of first electrodes for connection to external terminals during controlled time periods; the second electrodes comprising a first subset of second electrodes permanently connected to external terminals and a second subset of second electrodes connected to external terminals during controlled time periods; wherein one of the first set of electrodes and second set of electrodes comprises signal injection electrodes and the other of the first set of electrodes and second set of electrodes comprises sensor electrodes; the signal injection electrodes being provided to allow a pattern of bias to be applied to the resistive plane and injecting currents or forcing potential at either the first or second defined locations; the sensor electrodes being provided for sensing a potential on a surface of the resistive plane at the other of the first or second defined locations. | 10-30-2008 |
| 20080258808 | CIRCUIT TO OPTIMIZE CHARGING OF BOOTSTRAP CAPACITOR WITH BOOTSTRAP DIODE EMULATOR - A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having high- and low-side driver circuits for driving high- and low-side switches connected at the switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and the low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing the high-side floating supply voltage for the high-side driver circuit, the optimizing circuit comprising a bootstrap diode emulator circuit comprising a bootstrap diode emulator driver circuit driving a first switch, the first switch connected between the first terminal of the bootstrap capacitor and a supply voltage for the low side driver circuit; and a phase sense comparator circuit responsive to the voltage at the switched node and turning ON the first switch when the voltage at the switched node is LOW, whereby charging of the bootstrap capacitor is optimized when the phase sense comparator circuit is enabled, the phase sense comparator circuit turning OFF or keeping OFF the first switch when the first control voltage goes to a level to turn ON the high-side switch or remains at such level or the bootstrap capacitor supply voltage goes high or remains high such that it is a fixed amount above the low-side driver supply voltage; further wherein the phase sense comparator circuit turns the first switch ON when: the second control voltage is at a level adapted to turn ON the low-side switch and the bootstrap capacitor supply voltage is low such that it is below the fixed amount above the low side driver supply voltage; or the first and second control voltages are both at a level such that the high-side and low-side switches are OFF after the second control voltage transitions from an ON state to an OFF state and the bootstrap capacitor supply voltage goes below the fixed amount above the low-side driver supply voltage; or the first and second control voltages are both at a level such that the high-side and low-side switches are OFF after the first control voltage transitions from an ON state to an OFF state and the bootstrap capacitor supply voltage goes below the fixed amount above the low-side driver supply voltage. | 10-23-2008 |
| 20080253151 | METHOD AND APPARATUS TO REDUCE DYNAMIC Rdson IN A POWER SWITCHING CIRCUIT HAVING A III-NITRIDE DEVICE - A method of preventing the Rdson of a III-V Nitride power switching circuit from varying over time. The method includes biasing the switch to a pre-bias voltage level just below turn ON when the switch is OFF, wherein traps are discharged when the switch is biased to the pre-bias voltage level just below turn ON and the varying of the Rdson over time due to traps is reduced. The method can be employed in DC-DC converter circuits having III-V Nitride control and synchronous switches connected at a switching node. | 10-16-2008 |
| 20080252244 | SENSORLESS SPEED DETECTION OF A PM BRUSHLESS MOTOR WITH PHASE TERMINALS SHORTED - A method of determining the speed of a spinning sensorless brushless motor driven by an inverter when the phase terminals of the motor are shorted including determining a voltage related to the voltage developed in a phase leg of the inverter; from the determined voltage, determining the direction of current and providing a first signal determining transitions between current flowing in each of two directions; and from the first signal, determining the frequency of the current and thus the motor speed. | 10-16-2008 |
| 20080248634 | ENHANCEMENT MODE III-NITRIDE FET - A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device. | 10-09-2008 |
| 20080247209 | INTEGRATED SYNCHRONOUS RECTIFIER PACKAGE - A controller for controlling a controlled switching device functioning as a synchronous rectifier of alternating current, the controller comprising a control circuit for sensing the direction of current through the controlled switching device, the controlled switching device comprising a MOSFET having a conduction channel and a parasitic body diode and having two main current carrying terminals and a control terminal, the control circuit generating a control signal provided to the control terminal to turn on the controlled switching device approximately when current begins to flow in a first direction through the controlled switching device and turn off the controlled switching device approximately when current begins to flow in a second opposite direction through the controlled switching device, further wherein the control circuit for sensing the direction of current through the controlled switching device main current carrying terminals comprises a sensing circuit coupled across the controlled switching device for comparing a voltage across the controlled switching device to first and second thresholds, the sensing circuit causing the control signal to be generated to turn off the controlled switching device at the first threshold and to turn on the controlled switching device at the second threshold. | 10-09-2008 |
| 20080238904 | CURRENT SENSING BI-DIRECTIONAL SWITCH AND PLASMA DISPLAY DRIVER CIRCUIT - A discharge sustain driver circuit for a plasma display device, the driver circuit comprising a first transistor switching circuit for switching a DC bus voltage across the plasma display device; a storage capacitance; at least one inductor; and first and second bi-directional switching circuits coupled in series and being coupled to the first switching circuit to transfer charge from the plasma display device through the at least one inductor to the storage capacitance, and back to the plasma display device; and a controller for the bi-directional switching circuits to control the bi-directional switching circuits so as to receive the charge on the storage capacitance and return the charge in an opposite charge direction to the plasma display device. | 10-02-2008 |
| 20080224677 | DEAD TIME TRIMMING IN A CO-PACKAGE DEVICE - A method of obtaining an optimized dead time for a synchronous switching power supply comprising a control IC and two series-connected switches, comprising packaging the control IC and the series-connected switches in a co-packaged module; providing a dead time delay circuit within the control IC circuit which has variable dead time; testing the switching power supply; varying the dead time in a defined sequence during the step of testing; monitoring a parameter during testing of the switching power supply as the dead time is varied; determining an optimal dead time based upon monitoring the parameter; and setting the dead time at the optimal dead time. | 09-18-2008 |
| 20080211476 | HIGH VOLTAGE SHUNT-REGULATOR CIRCUIT WITH VOLTAGE-DEPENDENT RESISTOR - A voltage regulator circuit comprising a first circuit functioning as a voltage dependent resistor, the first circuit having an input coupled to a voltage source and an output and having a resistance dependent on the voltage applied across the circuit by the voltage source such that the resistance increases as the applied voltage increases; and a regulator coupled to the output of the first circuit for providing a regulated output voltage. | 09-04-2008 |
| 20080211440 | MEASUREMENT OF SPEED AND DIRECTION OF COASTING PERMANENT MAGNET SYNCHRONOUS MOTOR - A method for determining the speed of rotation of an unpowered, coasting electric motor, driven, when powered, by an electronic inverter, and without activating switches of the inverter. The steps include determining an electrical frequency of a back emf signal generated at a terminal of the motor or switching node of the inverter when the motor is coasting and determining the mechanical motor frequency and thus speed of rotation by dividing the electrical frequency by the number of motor pole pairs. | 09-04-2008 |
| 20080211425 | AUTOMOTIVE HID HEADLAMP BALLAST CONTROL IC - A ballast control integrated circuit for a ballast driving a high intensity discharge (HID) lamp. The control integrated circuit has a first circuit for controlling a DC to DC converter receiving a first DC voltage and providing an increased DC voltage. The first circuit includes a driver for providing a pulsed signal to drive a first switch coupled to a flyback transformer of the DC to DC converter. A second circuit controls a DC to AC converter, the second circuit controlling a switching circuit receiving the increased DC voltage and driving the HID lamp with an AC voltage. The second circuit has a driver circuit for driving the switching circuit. The switching circuit is an H-bridge switching circuit coupled to drive the HID lamp. | 09-04-2008 |
| 20080203997 | DIGITAL CURRENT SENSE - A circuit for measuring a current in an output inductor of at least one switching power supply having high- and low-side switches connected at a switching node, the output inductor having input and output terminals, the input terminal being connected to the switching node. The circuit including a sensing circuit for detecting a direction of current through the inductor, the sensing circuit generating a sense voltage related to the direction of current; a comparator circuit having an output terminal and input terminals coupled to the sensing circuit and receiving the sense voltage, the comparator circuit providing a comparison output of the sense voltage and an output voltage of the output inductor; and a switched current source circuit controlled by the comparison output for providing a reference current to the sensing circuit, the comparison output turning the switched current source circuit ON and OFF depending on the comparison output and having a duty cycle, whereby the average current flowing through the switched current source circuit is substantially equal to the average current in the sensing circuit and proportional to the duty cycle, the duty cycle being proportional to the inductor current. | 08-28-2008 |
| 20080197823 | CONVERTER CIRCUIT - A multiphase converter comprising a plurality of converter circuits, each converter circuit having series connected high and low side switches connected across a voltage bus with a common node provided therebetween, each of the common nodes connected through a respective inductor to an output node of the converter coupled to a load, the high and low side switches each being controlled by a control circuit to provide a desired output voltage at the output node, the control circuit including a first circuit for disabling and enabling at least one phase in response to a condition of the load, the circuit causing the high side switch to be turned on prior to the lower side switch when a disabled phase is enabled. | 08-21-2008 |
