| Intermolecular, Inc. Patent applications |
| Patent application number | Title | Published |
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| 20120122291 | Nonvolatile Memory Elements - Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer. | 05-17-2012 |
| 20120094503 | COMBINATORIAL PLASMA ENHANCED DEPOSITION TECHNIQUES - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 04-19-2012 |
| 20120094034 | COMBINATORIAL PLASMA ENHANCED DEPOSITION TECHNIQUES - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 04-19-2012 |
| 20120091590 | Electroless Deposition of Platinum on Copper - Embodiments of the current invention describe a method of plating platinum selectively on a copper film using a self-initiated electroless process. In particular, platinum films are plated onto very thin copper films having a thickness of less than 300 angstroms. The electroless plating solution and the resulting structure are also described. This process has applications in the semiconductor processing of logic devices, memory devices, and photovoltaic devices. | 04-19-2012 |
| 20120091417 | MULTISTATE NONVOLATILE MEMORY ELEMENTS - Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers. | 04-19-2012 |
| 20120090987 | COMBINATORIAL ELECTROCHEMICAL DEPOSITION - Combinatorial electrochemical deposition is described, including dividing a wafer into a plurality of substrates for combinatorial processing, immersing the plurality of substrates at least partially into a plurality of cells, within one integrated tool, including electrolytes, the cells also including electrodes immersed in the electrolytes, depositing layers on the substrates by applying potentials across the substrates and the electrodes, and varying characteristics of the depositing to perform the combinatorial processing. | 04-19-2012 |
| 20120090688 | DUAL PATH GAS DISTRIBUTION DEVICE - An apparatus for deploying two fluids separately into a reaction chamber is provided. The apparatus includes a first distribution network that is formed on a plate having a distribution face and a dispensing face. The first distribution network is defined by a plurality of recessed channels on the distribution face. The plurality of recessed channels includes a plurality of thru-ports that extend from the plurality of recessed channels to the dispensing face. The apparatus further includes a second distribution network that has passages formed below the plurality of recessed channels and above the dispensing face. A first set of ports extends from the passages to the distribution face and a second set of ports extends from a top surface of the distribution face to the dispensing face. | 04-19-2012 |
| 20120090545 | VAPOR BASED COMBINATORIAL PROCESSING - A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings. | 04-19-2012 |
| 20120088328 | NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm | 04-12-2012 |
| 20120077338 | COMBINATORIAL PLASMA ENHANCED DEPOSITION TECHNIQUES - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 03-29-2012 |
| 20120074376 | NONVOLATILE MEMORY ELEMENTS WITH METAL DEFICIENT RESISTIVE SWITCHING METAL OXIDES - Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal. | 03-29-2012 |
| 20120046202 | STIRRING APPARATUS FOR COMBINATORIAL PROCESSING - An apparatus and system for stirring liquid inside a flow cell. In one implementation, the apparatus includes a rotatable disc configured to receive liquid at a top side of the disc and distribute the liquid substantially evenly around a periphery of the flow cell. The disc has a triangular cross sectional area. The apparatus may further include a set of fins attached to a bottom side of the disc, wherein the set of fins is configured to draw the liquid from the periphery of the flow cell into the center of the flow cell. | 02-23-2012 |
| 20120044751 | BIPOLAR RESISTIVE-SWITCHING MEMORY WITH A SINGLE DIODE PER MEMORY CELL - According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell. | 02-23-2012 |
| 20120043298 | METHODS FOR DISCRETIZED PROCESSING AND PROCESS SEQUENCE INTEGRATION OF REGIONS OF A SUBSTRATE - The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate. | 02-23-2012 |
| 20120035878 | Combinatorial Process Optimization Methodology and System - A method for obtaining an optimized process solution from a set of design of experiments in a cost effective manner is provided. An actual experiment is performed and data from the experiments is obtained. Through statistical analysis of the data, coefficients are obtained. These coefficients are input into an experiment simulator where input parameters and conditions are combined with the coefficients to predict an output for the input parameters and conditions. From simulated results, conclusions can be drawn as to sets of input parameters and conditions providing desired results. Thereafter, physical experiments utilizing the input parameters and conditions may be performed to verify the simulated results. | 02-09-2012 |
| 20120032133 | SURFACE TREATMENT TO IMPROVE RESISTIVE-SWITCHING CHARACTERISTICS - This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution. | 02-09-2012 |
| 20120025164 | VARIABLE RESISTANCE MEMORY WITH A SELECT DEVICE - According to various embodiments, a variable resistance memory element and memory element array that uses variable resistance changes includes a select device, such as an ovonic threshold switch. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element. | 02-02-2012 |
| 20120021553 | METHODS FOR DISCRETIZED PROCESSING AND PROCESS SEQUENCE INTEGRATION OF REGIONS OF A SUBSTRATE - The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate. | 01-26-2012 |
| 20120001148 | STRESS-ENGINEERED RESISTANCE-CHANGE MEMORY DEVICE - A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode | 01-05-2012 |
| 20110303696 | MAINTAINING FLOW RATE OF A FLUID - A pressure gauge may be coupled to a supply line which carries liquid from a bottle to either one or more mixing vessels and/or one or more reactors in a combinatorial processing tool. A control device may monitor the pressure measured by the pressure gauge, and the control device may be configured to change the pressure supplied to the bottle based on a comparison of the measured pressure to a predetermined pressure value. The control device may adjust the pressure provided to the bottle using a pressure regulator coupled to the pressure source. By changing the pressure provided to the bottle, the control device may maintain a relatively constant flow rate of fluids from the liquid source into one or more mixing vessels and/or the one or more reactors. | 12-15-2011 |
| 20110281773 | ADVANCED MIXING SYSTEM FOR INTEGRATED TOOL HAVING SITE-ISOLATED REACTORS - An integrated processing tool is described comprising a full-wafer processing module and a combinatorial processing module. Chemicals for use in the combinatorial processing module are fed from a delivery system including a set of first manifolds. An output of each first manifold is coupled to at least one mixing vessel. An output of each mixing vessel feeds more than one of a set of second manifolds. An output of each set of second manifolds feeds one of multiple site-isolated reactors of the combinatorial processing module. | 11-17-2011 |
| 20110281402 | FORMATION OF A MASKING LAYER ON A DIELECTRIC REGION TO FACILITATE FORMATION OF A CAPPING LAYER ON ELECTRICALLY CONDUCTIVE REGIONS SEPARATED BY THE DIELECTRIC REGION - A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition. | 11-17-2011 |
| 20110269267 | ALD PROCESSING TECHNIQUES FOR FORMING NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer. | 11-03-2011 |
| 20110264252 | COMBINATORIAL PROCESSING MANAGEMENT SYSTEM - A combinatorial processing management system is described, including determining an identification for a substrate, retrieving data from tools operating on the substrate, generating an analysis of the data in response to the retrieving, and storing the data and the analysis in a database indexed by the identification. The analysis may include comparisons between multiple processes performed on multiple regions of the substrate. The multiple processes may process at least one region of the substrate differently from at least one other region of the substrate. | 10-27-2011 |
| 20110262644 | METHOD AND SYSTEM FOR MASK HANDLING IN HIGH PRODUCTIVITY CHAMBER - A structure for independently supporting a wafer and a mask in a processing chamber is provided. The structure includes a set of extensions for supporting the wafer and a set of extensions supporting the mask. The set of extensions for the wafer and the set of extensions for the mask enable independent movement of the wafer and the mask. In one embodiment, the extensions are affixed to an annular ring which is capable of moving in a vertical direction within the processing chamber. A processing chamber, a mask, and a method for combinatorially processing a substrate are also provided. | 10-27-2011 |
| 20110209663 | Multi-Region Processing System and Heads - The various embodiments of the invention provide for relative movement of the substrate and a process head to access the entire wafer in a minimal space to conduct combinatorial processing on various regions of the substrate. The heads enable site isolated processing within the chamber described and method of using the same are described. | 09-01-2011 |
| 20110207320 | Noble Metal Activation Layer - Processes for minimizing contact resistance when using nickel silicide (NiSi) and other similar contact materials are described. These processes include optimizing silicide surface cleaning, silicide surface passivation against oxidation and techniques for diffusion barrier/catalyst layer deposition. Additionally, processes for generating a noble metal (for example platinum, iridium, rhenium, ruthenium, and alloys thereof) activation layer that enables the electroless barrier layer deposition on a NiSi-based contact material are described. The processes may be employed when using NiSi-based materials in other end products. The processes may be employed on silicon-based materials | 08-25-2011 |
| 20110204475 | ENHANCED WORK FUNCTION LAYER SUPPORTING GROWTH OF RUTILE PHASE TITANIUM OXIDE - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO | 08-25-2011 |
| 20110204312 | CONFINEMENT TECHNIQUES FOR NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - Confirment techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode. | 08-25-2011 |
| 20110204311 | NON-VOLATILE RESISTIVE-SWITCHING MEMORIES FORMED USING ANODIZATION - Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element. | 08-25-2011 |
| 20110203085 | TITANIUM-BASED HIGH-K DIELECTRIC FILMS - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO | 08-25-2011 |
| 20110201149 | METHODS FOR FORMING RESISTIVE SWITCHING MEMORY ELEMENTS - Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication. | 08-18-2011 |
| 20110201136 | COMBINATORIAL EVALUATION OF DRY SEMICONDUCTOR PROCESSES - Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions. | 08-18-2011 |
| 20110199853 | Combinatorial Processing Including Stirring - Combinatorial processing including stirring is described, including defining multiple regions of a substrate, processing the multiple regions of the substrate in a combinatorial manner, introducing a fluid into a first aperture at a first end of a body to dispense the fluid out of a second aperture at a second end of the body and into one of the multiple regions, and agitating the fluid using an impeller at a second end of the body to facilitate interaction of the fluid with a surface of the substrate. | 08-18-2011 |
| 20110179999 | SYSTEMS AND METHODS FOR SEALING IN SITE-ISOLATED REACTORS - Substrate processing systems and methods are described for site-isolated processing of substrates. The processing systems include numerous site-isolated reactors (SIRs). The processing systems include a reactor block having a cell array that includes numerous SIRs. A sleeve is coupled to an interior of each of the SIRs. The sleeve includes a compliance device configured to dynamically control a vertical position of the sleeve in the SIR. A sealing system is configured to provide a seal between a region of a substrate and the interior of each of the SIRs. The processing system can include numerous modules that comprise one or more site-isolated reactors (SIRs) configured for one or more of molecular self-assembly and combinatorial processing of substrates. | 07-28-2011 |
| 20110177236 | MOLECULAR SELF-ASSEMBLY IN SUBSTRATE PROCESSING - Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming. | 07-21-2011 |
| 20110175228 | MOLECULAR SELF-ASSEMBLY IN SUBSTRATE PROCESSING - Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming. | 07-21-2011 |
| 20110163424 | Molecular Self-Assembly In Substrate Processing - Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming. | 07-07-2011 |
