Intemational Business Machines Corporation Patent applications |
Patent application number | Title | Published |
20150270373 | REPLACEMENT METAL GATE - A replacement metal gate process which includes forming a fin on a semiconductor substrate; forming a dummy gate structure on the fin; removing the dummy gate structure to leave an opening that is to be filled with a permanent gate structure; depositing a high dielectric constant (high-k) dielectric material in the opening and over the fin; depositing a work function metal in the opening and over the fin so as to be in contact with the high-k dielectric material, the high k dielectric material and the work function metal only partially filling the opening; filling a remainder of the opening with an organic material; etching the organic material until it is partially removed from the opening; etching the work function metal until it is at a same level as the organic material; removing the organic material; and filling the opening with a metal until the opening is completely filled. | 09-24-2015 |
20150056792 | FINFET AND METHOD OF FABRICATION - An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit. | 02-26-2015 |
20150054082 | SEMICONDUCTOR STRUCTURE WITH DEEP TRENCH THERMAL CONDUCTION - Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches. | 02-26-2015 |
20140325514 | Maintenance of Offline Virtual Machines Based on a Maintenance Register - A solution is proposed for maintaining virtual machines being available in a data-processing system. A mechanism determines a list of software components installed on each virtual machine, retrieves a set of maintenance policies for each software component, each maintenance policy being indicative of a patch to be applied to the corresponding software component. The mechanism determines a set of old virtual machines having at least one old software component thereof requiring the application of at least a new one of the corresponding patches according to a comparison among the maintenance policies and a maintenance register indicative of a current state of the software components of the virtual machines. The mechanism applies the corresponding at least one new patch to each old software component of each old virtual machine and updates the maintenance register according to the application of said at least one new patch to each old software component of each old virtual machine. | 10-30-2014 |
20140175375 | HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE - A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer. | 06-26-2014 |
20140175374 | HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE - A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins. | 06-26-2014 |
20140013235 | REPRESENTING A GRAPHICAL USER INTERFACE USING A TOPIC TREE STRUCTURE - A method, computer program product, and system for a quality-of-service history database is described. A first input associated with a change to a component of a graphical user interface is received, wherein a portion of the component is represented as a first node of a tree structure representing a portion of the graphical user interface. A first characteristic of the change is determined. The first characteristic of the change is associated with a second node of the topic tree structure. The associated first characteristic is transmitted to a first computing device, wherein transmission of the associated first characteristic allows one or more of the first computing device and a second computing device to determine a first aspect of the change based upon, at least in part, the topic tree structure. | 01-09-2014 |
20130097611 | UNIFIED, WORKLOAD-OPTIMIZED, ADAPTIVE RAS FOR HYBRID SYSTEMS - A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes performing a first data computation by a first set of processors, the first set of processors having a first computer processor architecture. The method continues by performing a second data computation by a second processor coupled to the first set of processors, the second processor having a second computer processor architecture, the first computer processor architecture being different than the second computer processor architecture. Finally, the method includes dynamically allocating computational resources of the first set of processors and the second processor based on at least one metric while the first set of processors and the second processor are in operation such that the accuracy and processing speed of the first data computation and the second data computation are optimized. | 04-18-2013 |
20090109780 | HYBRID STATIC AND DYNAMIC SENSING FOR MEMORY ARRAYS - A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit. | 04-30-2009 |