| INTEL CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20120137334 | HOME MEDIA SERVER CONTROL - A home media server includes a processor, a storage medium; and machine-readable code, stored on the non-transitory storage medium, the non-transitory storage medium includes instructions which when executed, cause the home media server to receive downloadable instructions, an edited set of data and analysis data. The downloadable instructions, when executed by the processor cause the home media server to search for and obtain media content associated with an edited video program. The instructions also cause the home media server to receive the edited set of data corresponding to editing steps for assembly of the edited video program, and to emulate assembly of the edited video program utilizing the media content obtained by the home media server to created an emulated video program. | 05-31-2012 |
| 20120131010 | TECHNIQUES TO DETECT VIDEO COPIES - Some embodiments include a video copy detection approach based on speeded up robust features (SURF) trajectory building, local sensitive hash (LSH) indexing, and spatial-temporal-scale registration. First, interesting points' trajectories are extracted by SURF. Next, an efficient voting based spatial-temporal-scale registration approach is applied to estimate the optimal transformation parameters (shift and scale) and achieve the final video copy detection results by propagations of video segments in both spatial-temporal and scale directions. To speed up the detection speed, local sensitive hash (LSH) indexing is used to index trajectories for fast queries of candidate trajectories. | 05-24-2012 |
| 20120126286 | MONOLITHIC THREE TERMINAL PHOTODETECTOR - Photodetectors operable to achieve multiplication of photogenerated carriers at ultralow voltages. Embodiments include a first p-i-n semiconductor junction combined with a second p-i-n semiconductor junction to form a monolithic photodetector having at least three terminals. The two p-i-n structures may share either the p-type region or the n-type region as a first terminal. Regions of the two p-i-n structures doped complementary to that of the shared terminal form second and third terminals so that the first and second p-i-n structures are operable in parallel. A multiplication region of the first p-i-n structure is to multiply charge carriers photogenerated within an absorption region of the second p-i-n structure with voltage drops between the shared first terminal and each of the second and third terminals being noncumulative. | 05-24-2012 |
| 20120112961 | METHOD AND APPARATUS FOR FASTER GLOBAL POSITIONING SYSTEM (GPS) LOCATION USING A PRE-COMPUTED SPATIAL LOCATION FOR TRACKING GPS SATELLITES - A method and apparatus for faster global positioning system (GPS) location using pre-computed spatial location data are described. In one embodiment, a method includes acquiring a pre-computed spatial location of a mobile platform device (MPD) that is computed when a GPS receiver is disabled due to the spatial location of the MPD. In one embodiment, the pre-computed spatial location is determined by a non-GPS based spatial location technology when a receiver is disabled due to the spatial location of the MPD, During the periodic computation of spatial location data, the GPS receiver may be monitored. In one embodiment, in response to activation of the GPS receiver, the pre-computed spatial location data is provided to the GPS receiver for identification and lock onto a predetermined number of visible satellites to reduce a time to first fix (TTFF) a current spatial location of the MPD. Other embodiments are described and claimed. | 05-10-2012 |
| 20120096379 | USER INTERFACE TO FACILITATE EXCHANGING FILES AMONG PROCESSOR-BASED DEVICES - A first processor-based device (PBD), such as a personal computer functioning as a host and containing digital media files, may share a selected file with a second PBD. Media file-sharing may be facilitated by an automated technique including graphical user interfaces (GUIs). In one embodiment, when a device user wishes to transfer a file to another device, the user hovers the file over a particular desktop icon and drops it, causing it to be automatically transmitted to a corresponding destination. Optionally, in response to hovering, a software program automatically generates a GUI indicating potential destinations. The user then selects a destination, and the system automatically transfers the file to that destination. In another embodiment, media sharing can be initiated from a digital appliance, such as a digital picture frame, and a file can be sent to another PBD, such as another digital picture frame via an intermediary PBD. | 04-19-2012 |
| 20120096370 | USER INTERFACE TO FACILITATE EXCHANGING FILES AMONG PROCESSOR-BASED DEVICES - A first processor-based device (PBD), such as a personal computer functioning as a host and containing digital media files, may share a selected file with a second PBD. Media file-sharing may be facilitated by an automated technique including graphical user interfaces (GUIs). In one embodiment, when a device user wishes to transfer a file to another device, the user hovers the file over a particular desktop icon and drops it, causing it to be automatically transmitted to a corresponding destination. Optionally, in response to hovering, a software program automatically generates a GUI indicating potential destinations. The user then selects a destination, and the system automatically transfers the file to that destination. In another embodiment, media sharing can be initiated from a digital appliance, such as a digital picture frame, and a file can be sent to another PBD, such as another digital picture frame via an intermediary PBD. | 04-19-2012 |
| 20120088451 | DEVICE, SYSTEM, AND METHOD OF WIRELESS TRANSFER OF FILES - Device, system, and method of wireless transfer of files. For example, a method includes: identifying a selection of a representation of a digital object stored in a mobile device by detecting contact on a touch-sensitive surface of the mobile device at a contact position that corresponds to said representation; identifying a directional movement of said contact position on the touch-sensitive surface; and in response to said directional movement, wirelessly transferring data corresponding to the digital object to a nearby computing device. | 04-12-2012 |
| 20120079564 | METHOD AND APPARATUS FOR PERFORMING AN AUTHENTICATION AFTER CIPHER OPERATION IN A NETWORK PROCESSOR - A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets. | 03-29-2012 |
| 20120060159 | METHOD AND APPARATUS FOR SCHEDULING THE PROCESSING OF COMMANDS FOR EXECUTION BY CRYPTOGRAPHIC ALGORITHM CORES IN A PROGRAMMABLE NETWORK PROCESSOR - A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor. | 03-08-2012 |
| 20120036134 | PERFORMING CONCURRENT REHASHING OF A HASH TABLE FOR MULTITHREADED APPLICATIONS - In one embodiment, the present invention includes a method for allocating a second number of buckets for a hash table shared concurrently by a plurality of threads, where the second number of buckets are logically mapped onto a corresponding parent one of the first number of buckets, and publishing an updated capacity of the hash table to complete the allocation, without performing any rehashing, such that the rehashing can later be performed in an on-demand, per bucket basis. Other embodiments are described and claimed. | 02-09-2012 |
| 20120030457 | OFFLOADING THE PROCESSING OF A NETWORK PROTOCOL STACK - A computer system is partitioned during a pre-boot phase of the computer system between a first partition and a second partition, wherein the first partition to include a first processing unit and the second partition to include a second processing unit. An Input/Output (I/O) operating system is booted on the first partition. A general purpose operating system is booted on the second partition. Network transactions are issued by the general purpose operating system to be performed by the I/O operating system. The network transactions are performed by the I/O operating system. | 02-02-2012 |
| 20120023502 | ESTABLISHING THREAD PRIORITY IN A PROCESSOR OR THE LIKE - In a multi-threaded processor, one or more variables are set up in memory (e.g., a register) to indicate which of a plurality of executable threads has a higher priority. Once the variable is set, several embodiments are presented for granting higher priority processing to the designated thread. For example, more instructions from the higher priority thread may be executed as compared to the lower priority thread. Also, a higher priority thread may be given comparatively more access to a given resource, such as memory or a bus. | 01-26-2012 |
| 20120020340 | SYSTEM AND METHOD FOR TRANSFERRING WIRELESS NETWORK ACCESS PASSWORDS - The present disclosure provides an access node for transferring and/or assigning network passwords. The access node includes a first interface for sending and receiving communication of a first type to and from a first node operating in a wireless local area network (WLAN). The access node also includes a second interface for sending and receiving communication of a second type to and from a second node in a mobile network, such as a GSM/GPRS network. The access node further includes a short messaging service (SMS) module for sending and receiving. SMS messages to the second node carrying an OTP allocated. The access node also includes a mechanism to verify a precondition before the OTP is sent to the second node. | 01-26-2012 |
| 20120019285 | METHOD AND APPARATUS FOR FAST WAKE-UP OF ANALOG BIASES - Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal. | 01-26-2012 |
| 20120013762 | DETERMINING A FINAL EXPOSURE SETTING AUTOMATICALLY FOR A SOLID STATE CAMERA WITHOUT A SEPARATE LIGHT METERING CIRCUIT - An embodiment of the invention is a method of generating a final exposure setting, including, (a) selecting one of a number of predetermined exposure settings as a current exposure setting for a solid state camera having a camera imager, (b) generating a captured scene by the camera imager using the current exposure setting, (c) selecting according to an automated search methodology another one of the exposure settings to be the current setting in response to the captured scene being underexposed or overexposed, and, (d) repeating (b) and (c) until the captured scene is neither underexposed or overexposed. | 01-19-2012 |
| 20120000640 | METHOD AND AN APPARATUS FOR COOLING A COMPUTER - A heat exchanging system comprising circulating fluid through a tube coupled to an electronic component in a first part of a computing device and to a heat transfer plate in a second part of the computing device. | 01-05-2012 |
| 20110307878 | SYSTEM FOR ATOMICALLY UPDATING A PLURALITY OF FILES - A method for updating platform firmware is disclosed. This capability is facilitated by a standard software abstraction for a firmware storage device, known as Firmware Volume (FV) that is managed through a Firmware File System (FFS). The FFS enables firmware files to be created, deleted, and updated individually. The FFS also enables a plurality of firmware files to be updated atomically by managing file state information via state bits stored in a file header of each firmware file, whereby an atomic change to a single state bit simultaneously causes the FFS to use an updated set of firmware files in place of an original set of firmware files. | 12-15-2011 |
| 20110296457 | CONVERGED COMMUNICATION SERVER WITH TRANSACTION MANAGEMENT - A communications server increases the value of cable and communication services by enabling the integration of packet network content with directed advertising in a managed environment. Such services may include Video On Demand and videoconferencing running on a Converged Communication Platform. Content processing within the server enables the combining of streaming content with different types of ads. Content integration is controlled through software negotiations between subscriber, advertiser, and content provider software agents. The rate, selection, placement, and number of advertisements within a television program or videoconference can also be determined. The ability to custom tailor content and advertisements increases the value of advertising, lowers costs to subscribers, improves the viewing experience, and disburdens transaction participants from the manual tasks that would otherwise be required during transaction setup. | 12-01-2011 |
| 20110294264 | HEAT SPREADER AS MECHANICAL REINFORCEMENT FOR ULTRA-THIN DIE - A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer layer is diced into a plurality of WSS-supported thin dice. A WSS-supported thin die is bonded to a first heat spreader (HS) to form a HS-reinforced thin die. | 12-01-2011 |
| 20110294048 | MOUNTING A PELLICLE TO A FRAME - A pellicle membrane is mounted between an outer frame and an inner frame. At least one of the frames is attached to the reticle without using conventional adhesives. The pellicle and reticle may be used in a lithography system. The pellicle allows radiation to pass through the pellicle to the reticle and may prevent particles from passing through the pellicle. | 12-01-2011 |
| 20110291304 | METHOD OF MAKING MICROELECTRONIC PACKAGE USING INTEGRATED HEAT SPREADER STIFFENER PANEL AND MICROELECTRONIC PACKAGE FORMED ACCORDING TO THE METHOD - A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel; mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel; and singulating the combination to yield a plurality of microelectronic packages, each of the packages including: an IHS component of the IHS panel, one of the plurality IC dies bonded and thermally coupled to said IHS component, and one of the plurality of package substrates, said IHS component and said one of the plurality of IC dies being mounted to said one of the plurality of package substrates to form said each of the packages. | 12-01-2011 |
| 20110277980 | MICROFINS FOR COOLING AN ULTRAMOBILE DEVICE - The present invention discloses a method of cooling an ultramobile device with microfins attached to an external wall of an enclosure surrounding the ultramobile device. | 11-17-2011 |
| 20110258444 | Network Controller Decryption - A system for selectively transmitting packets involves marking a plurality of packets coming into a transmit queue with an indicator of a packet type. Some packet types may take longer to process than others. For example, packets associated with security protocols may take a longer time to process than those that do not involve security processing. A dispatcher may determine based on the marking of the packet whether it is a security or a non-security packet and may determine when to transmit the packet based on that information. | 10-20-2011 |
| 20110224092 | METHOD AND APPARATUS FOR COMBINED ELECTROCHEMICAL SYNTHESIS AND DETECTION OF ANALYTES - Described are devices and methods for detecting binding on an electrode surface. In addition, devices and methods for electrochemically synthesizing polymers and devices and methods for synthesizing and detecting binding to the polymer on a common integrated device surface are described. | 09-15-2011 |
| 20110208874 | PACKET AGGREGATION - A system includes logic to store multiple descriptors, each of the multiple descriptors to be associated with a different set of multiple Transmission Control Protocol/Internet Protocol (TCP/IP) packets received by the network controller, each of the multiple descriptors including a count of the number of packets in the set of multiple packets associated with a respective descriptor. For each of the respective receive packets, the system determines a one of the multiple descriptors based on the network source address, network destination address, source port, and destination port of the respective packet; includes the respective packet in the set of multiple packets associated with the determine one of the multiple descriptors; and updates the one of the multiple descriptors by incrementing the count of the number of packets in the set of multiple packets; and provides data from within the packets to the host. | 08-25-2011 |
| 20110208871 | QUEUING BASED ON PACKET CLASSIFICATION - A system includes a host and a network controller coupled to the host by a bus. The system includes logic to classify Transmission Control Protocol/Internet Protocol (TCP/IP) receive packets based on the network source, network destination, port source, and port destination of the respective receive packets; and cause queuing of the receive packets in a one of multiple receive queues based on the classifying such that receive packets having the same network source, network destination, port source, and port destination are to be queued to the same one of the multiple queues for processing. | 08-25-2011 |
| 20110183696 | Electronic System Location Determination - A lost or stolen computing device is recovered. A trusted server is requested to locate the computing device. The trusted server requests coarse location information from the computing device, and the computing device reports its coarse location. The trusted server then requests that the computing device transmit wireless local area networks signal so that it may be recovered. | 07-28-2011 |
| 20110179295 | METHOD, APPARATUS AND SYSTEM TO DYNAMICALLY CHOOSE AN OPTIMUM POWER STATE - Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described. | 07-21-2011 |
| 20110173232 | STRING SEARCH SCHEME IN A DISTRIBUTED ARCHITECTURE - Methods and apparatuses for searching network data for one or more predetermined strings are disclosed. In one embodiment, the string search is a multi-stage search where the stages of the search are performed by different hardware components. In one embodiment in a first search stage, a first processor performs a comparison of blocks of incoming data to determine whether the blocks potentially represent the beginning of one of the predetermined strings. If a potential predetermined string is identified, a second processor performs a further search to determine whether the string matches one of the predetermined strings. Because the first processor searches only for the beginning of the predetermined strings, the first stage comparison can be performed quickly, which improves network performance as compared to more detailed searching. The second stage is performed by second processor, which allows the first processor to search for potential matching strings. Because many strings do not match the one or more predetermined strings, the more detailed search performed by the second processor is performed selectively, which increases network performance as compared to more detailed searches on all network data. | 07-14-2011 |
| 20110161551 | VIRTUAL AND HIDDEN SERVICE PARTITION AND DYNAMIC ENHANCED THIRD PARTY DATA STORE - A system reserves and manages a hidden service partition through components of the hardware platform of a computing device. The hidden partition is not accessible by way of a host operating system on the computing device. A hardware platform controller provisions a portion of nonvolatile storage through configuration settings of the hardware platform controller. When the host system requests settings related to storage in the system, the request is routed through the interfaces of the hardware platform, and the hardware platform controller reports in accordance with the configuration settings, hiding the service partition. The hidden partition is dynamically modifiable through secure remote access to the hardware platform controller, not through the host system such as operating system or BIOS. | 06-30-2011 |
| 20110153908 | ADAPTIVE ADDRESS MAPPING WITH DYNAMIC RUNTIME MEMORY MAPPING SELECTION - A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel. | 06-23-2011 |
| 20110141976 | FAST PATH PACKET DESTINATION MECHANISM FOR NETWORK MOBILITY VIA SECURE PKI CHANNEL - Disclosed is a method for reducing routing overheads during data transmission to a destination mobile router of a plurality of mobile routers roaming in a network. The method comprises registering by top level mobile routers with a central authority server, sending data packets by a corresponding node of the network to the destination mobile router operationally attached to a corresponding top level mobile router, locating a position of the destination mobile router by identifying attachment of the destination mobile router to the corresponding top level mobile router from the information registered by the plurality of mobile routers with the central authority server, routing the data packet directly to the corresponding top level mobile router to which the destination mobile router is operationally attached and receiving the data packet by the destination mobile router from the corresponding top level mobile router, thereby reducing routing overheads in the network. | 06-16-2011 |
| 20110119751 | SYSTEM AND METHOD FOR REGULATING COMMUNICATIONS TO OR FROM AN APPLICATION - The flow of information to or from an application on a host machine is regulated by a trusted agent operating in conjunction with at least one security element, such as a firewall or a policy server. When a communication to or from the application is detected by the trusted agent, the trusted agent gathers information about the attempted communication, and formulates and sends a message based upon the gathered information to at least one security element. The security element makes a decision to permit or block at least part of the attempted communication based upon the message received from the trusted agent. | 05-19-2011 |
| 20110113222 | METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR OR THE LIKE - In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor. | 05-12-2011 |
| 20110113197 | QUEUE ARRAYS IN NETWORK DEVICES - A queue descriptor including a head pointer pointing to the first element in a queue and a tail pointer pointing to the last element in the queue is stored in memory. In response to a command to perform an enqueue or dequeue operation with respect to the queue, fetching from the memory to a cache only one of either the head pointer or tail pointer and returning to the memory from the cache portions of the queue descriptor modified by the operation. | 05-12-2011 |
| 20110103438 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 05-05-2011 |
| 20110103170 | NOVEL FUSE PROGRAMMING SCHEMES FOR ROBUST YIELD - An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession. | 05-05-2011 |
| 20110099308 | SPLIT TRANSACTION PROTOCOL FOR A BUS SYSTEM - A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction. | 04-28-2011 |
| 20110078835 | SEEK-SCAN PROBE (SSP) MEMORY WITH SHARP PROBE TIPS FORMED AT CMOS-COMPATIBLE TEMPERATURES - Embodiments of a process comprising forming one or more micro-electro-mechanical (MEMS) probe on a conductive metal oxide semiconductor (CMOS) wafer, wherein each MEMS probe comprises a cantilever beam with a fixed end and a free end and wherein the CMOS wafer has circuitry thereon; forming an unsharpened tip at or near the free end of each cantilever beam; depositing a silicide-forming material over the tip; annealing the wafer to sharpen the tip; and exposing the sharpened tip. Embodiments of an apparatus comprising a conductive metal oxide semiconductor (CMOS) wafer including circuitry therein; one or more micro-electro-mechanical (MEMS) probes integrally formed on the CMOS wafer, wherein each MEMS probe comprises a cantilever beam with a fixed end and a free end and a sharpened tip at or near the free end, the sharpened tip formed by a process comprising forming an unsharpened tip at or near the free end of each cantilever beam, depositing a silicide-forming material over the unsharpened tip, annealing the wafer to sharpen the unsharpened tip, and exposing the sharpened tip. | 03-31-2011 |
| 20110075034 | METHOD AND APPARATUS TO SUPPORT MULTI-CHANNEL RECEPTION - In accordance with various aspects of the disclosure, a method and apparatus for receiving multiple channels from a broadcast source and interfacing to multiple demodulators within a common silicon implementation is disclosed. A receiver apparatus is disclosed that may aggregate multiple channels output by multiple tuners into at least one composite signal. The at least one composite signal may be passed to a single ADC. The channels may then be extracted from the at least one composite signal in the digital domain prior to demodulation in separate demodulators. | 03-31-2011 |
| 20110064157 | Spectrally flat delay diversity transmission - Delay diversity is implemented within a wireless system in a manner that can achieve a relatively flat spectrum in a receiving device. In at least one embodiment, phase shift values from an orthogonal P×N matrix A are used to provide phase shifts to a data packet to be transmitted from N transmit antennas, in a single spatial stream, to a remote wireless device. The matrix A is an orthogonal matrix with A·A | 03-17-2011 |
| 20110059766 | COMPACT ALPHANUMERIC KEYBOARD - An apparatus comprises an input keypad having a plurality of keys. The input keypad outputs an output signal that is indicative of either a single depressed key or a plurality of depressed keys. The apparatus includes a processor for receiving the output signal by the input keypad and associating an alphabetic character with the output signal. | 03-10-2011 |
| 20110047376 | METHOD AND APPARATUS FOR SECURE EXECUTION USING A SECURE MEMORY PARTITION - A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code. | 02-24-2011 |
| 20110045659 | SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBSTRATES - A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×10 | 02-24-2011 |
| 20110022866 | METHOD AND APPARATUS FOR THERMAL SENSITIVITY BASED DYNAMIC POWER CONTROL - A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance. | 01-27-2011 |
| 20100330467 | PELLICLE FRAME AND LITHOGRAPHIC PELLICLE - A pellicle frame is provided that includes a pellicle frame bar having a cross-section with a shape that has a curved line-containing recess in at least one side edge of a quadrilateral having an upper edge and a lower edge parallel to each other and an area of no greater than 20 mm | 12-30-2010 |
| 20100330466 | PELLICLE FRAME AND LITHOGRAPHIC PELLICLE - A pellicle frame is provided that comprises a pellicle frame bar having a quadrilateral cross-section, wherein an upper edge and a lower edge of a basic quadrilateral forming said cross-section are parallel to each other and each of side edges of the basic quadrilateral has one quadrilateral recess. There is also provided a lithographic pellicle that includes a pellicle film stretched over one end face of the pellicle frame via a pellicle film adhesive, and that includes an exposure master plate adhesive on the other end face. | 12-30-2010 |
| 20100329285 | MECHANISM FOR CLOCK SYNCHRONIZATION - A method and apparatus for synchronizing time between a master device and a target device arranged across a network, wherein the target device communicates to the master device through a PCIe interconnect includes transmitting a first message at a first time from the master device to the target device, the first message including a message indicator; and receiving a reply message at a subsequent time from the target device to the master device, the reply message including the message indicator. | 12-30-2010 |
| 20100329254 | MULTICAST SUPPORT ON A SWITCH FOR PCIe ENDPOINT DEVICES - Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system. | 12-30-2010 |
| 20100328641 | PELLICLE FRAME AND LITHOGRAPHIC PELLICLE - A pellicle frame is provided that includes a pellicle frame bar having a cross-section with a shape that has at least one triangular recess in at least one side edge of a quadrilateral having an upper edge and a lower edge parallel to each other and a cross-sectional area of no greater than 20 mm | 12-30-2010 |
| 20100327261 | HIGH HOLE MOBILITY P-CHANNEL GE TRANSISTOR STRUCTURE ON SI SUBSTRATE - The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 12-30-2010 |
| 20100318656 | MULTIPLE-CHANNEL, SHORT-RANGE NETWORKING BETWEEN WIRELESS DEVICES - Multiple-channel, short-range networking between wireless devices. An embodiment of a method includes sending a request from a mobile device, the request asking external devices to provide an announcement, the request being sent via a first wireless channel, and receiving announcements from one or more external devices including a first device. The method further includes transmitting data from the mobile device to the first device via the first wireless channel to negotiate a secure network, establishing the secure network connection on a second wireless channel, and transferring data securely from the mobile device to the first device via the second wireless channel using the secure network connection. | 12-16-2010 |
| 20100315531 | DETERMINING A FINAL EXPOSURE SETTING AUTOMATICALLY FOR A SOLID STATE CAMERA WITHOUT A SEPARATE LIGHT METERING CIRCUIT - An embodiment of the invention is a method of generating a final exposure setting, including, (a) selecting one of a number of predetermined exposure settings as a current exposure setting for a solid state camera having a camera imager, (b) generating a captured scene by the camera imager using the current exposure setting, (c) selecting according to an automated search methodology another one of the exposure settings to be the current setting in response to the captured scene being underexposed or overexposed, and, (d) repeating (b) and (c) until the captured scene is neither underexposed or overexposed. | 12-16-2010 |
| 20100267013 | METHODS TO INCREASE NUCLEOTIDE SIGNALS BY RAMAN SCATTERING - The methods and apparatus disclosed herein concern nucleic acid sequencing by enhanced Raman spectroscopy. In certain embodiments of the invention, nucleotides are covalently attached to Raman labels before incorporation into a nucleic acid. In other embodiments, unlabeled nucleic acids are used. Exonuclease treatment of the nucleic acid results in the release of labeled or unlabeled nucleotides that are detected by Raman spectroscopy. In alternative embodiments of the invention, nucleotides released from a nucleic acid by exonuclease treatment are covalently cross-linked to nanoparticles and detected by surface enhanced Raman spectroscopy (SERS), surface enhanced resonance Raman spectroscopy (SERRS) and/or coherent anti-Stokes Raman spectroscopy (CARS). Other embodiments of the invention concern apparatus for nucleic acid sequencing. | 10-21-2010 |
| 20100213581 | DIELECTRIC FILM WITH LOW COEFFICIENT OF THERMAL EXPANSION (CTE) USING LIQUID CRYSTALLINE RESIN - An embodiment of the present invention is a technique to provide a dielectric film material with controllable coefficient of thermal expansion (CTE). A first compound containing a first liquid crystalline component is formed. The first compound is cast into a first film. The first film is oriented in an magnetic or electromagnetic field in a first direction. The first film is cured at a first temperature. | 08-26-2010 |
| 20100210072 | Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer - Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein. | 08-19-2010 |
| 20100208579 | ADAPTIVE USE OF A TRANSMIT OPPORTUNITY - Various embodiments are described to adaptively use a transmit opportunity. | 08-19-2010 |
| 20100193173 | HEAT SINKS AND METHOD OF FORMATION - A heat sink (and method of forming a heat sink) is provided that includes a core having a central axis and a plurality of cooling fins arranged about the core. Each fin has a base and a tip. The fins may be shaped to capture a tangential component of air from the fan. At least one portion (such as upper portion) of the fins may be bent. A lower portion of each fin may also be bent. | 08-05-2010 |
| 20100191997 | PREDICT COMPUTING PLATFORM MEMORY POWER UTILIZATION - A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model. | 07-29-2010 |
| 20100174965 | LDPC CODES WITH SMALL AMOUNT OF WIRING - The embodiments herein relate to Low Density Parity Check (LDPC) codes, their corresponding matrices, and with an LDPC decoder architecture used to decode those codes. Embodiments herein relate to methods to generate a set of LDPC codes (typically of different rates) that share their wires as much as possible and therefore reduce the silicon area and ease the routing. | 07-08-2010 |
| 20100171950 | METHODS FOR UNIFORM METAL IMPREGNATION INTO A NANOPOROUS MATERIAL - The methods, systems | 07-08-2010 |
| 20100164802 | Arrangements for beam refinement in a wireless network - In some embodiments a beamforming method is disclosed. The method can include transmitting a beam having a channel defined by a maximum ration transmission vector (MRT) and receiving a first response from a receiver, where the first response has first information such as parameters related to the transmitted beam. Using the parameters and the initial MRT another directional transmission can be made. A similar process can determine a maximum combining ratio for a receiver. Set up communications between the transmitter and the receiver can be reduced by omitting data from transmission that can be acquired by other means such as from memory or calculations. Additional embodiments are also disclosed. | 07-01-2010 |
| 20100161271 | TECHNIQUES FOR DETERMINING ORIENTATION OF A THREE-AXIS ACCELEROMETER - A method, apparatus, and article containing computer instructions are described. Embodiments may use accelerometer data regarding forward motion by a wearer of a three-axis on-body accelerometer. Embodiments may further measure an acceleration due to gravity on each axis x, y, z of the accelerometer and use the direction of gravity to associate or align the x axis of the accelerometer with gravity. Embodiments may then use the acceleration not due to gravity to identify the forward motion and associate or align the forward direction with the y axis. The remaining direction may be identified as the sideways direction, which may be associated or aligned with the z axis. Additional activities may then be performed using the now-known orientation of the accelerometer. Other embodiments are described and claimed. | 06-24-2010 |
| 20100158141 | METHODS AND SYSTEMS TO ESTIMATE CHANNEL FREQUENCY RESPONSE IN MULTI-CARRIER SIGNALS - Methods and systems to determine channel frequency responses corresponding to multi-carrier signals, such as OFDM signals, including to filter or mask noise from channel frequency response estimates in a time domain. | 06-24-2010 |
| 20100150264 | Precoder Design for Different Channel Lengths - Apparatus and methods construct parameters for a unit associated with a precoder to a channel. Embodiments include forming a plurality of values for precoder constructions, where the values may be obtained from applying a transmission quality criterion to each precoder construction for varying channels lengths. Each precoder construction may be built for a predetermined channel length with a different channel length for each precoder construction. A subset of the precoder constructions operate substantially over the entire distance range covered by the varying channels lengths. | 06-17-2010 |
| 20100146360 | Unified Decoder for Convolutional, Turbo, and LDPC Codes - A unified decoder ( | 06-10-2010 |
| 20100146311 | Method and Apparatus for a Zero Voltage Processor Sleep State - Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. | 06-10-2010 |
| 20100126631 | CARBON NANOTUBES SOLDER COMPOSITE FOR HIGH PERFORMANCE INTERCONNECT - An embodiment of the present invention is an interconnect technique. Carbon nanotubes (CNTs) are prepared. A CNT-solder composite paste is formed containing the CNTs and solder with a pre-defined volume fraction. | 05-27-2010 |
| 20100120132 | Bioassays by direct optical detection of nanoparticles - Embodiments of the invention relate to detecting biological molecules with ultra-sensitivity and convenience. The embodiments are especially directed to utilizing nanoparticles as tags and identifying the tags using dark-field microscopy. The probes containing the nanoparticles can be used in solution or attached to a substrate. | 05-13-2010 |
| 20100118875 | INTERCONNECTING NETWORK PROCESSORS WITH HETEROGENEOUS FABRICS - A method and apparatus to perform protocol translation for a modular system may be described. | 05-13-2010 |
| 20100118028 | Method and Mechanism for Programmable Filtering of Texture Map Data in 3D Graphics Subsystems - A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program. | 05-13-2010 |
| 20100111013 | FREQUENCY SELECTION FOR FEMTO ACCESS POINT - Briefly, in accordance with one or more embodiments, a femto access point scans an area of a network to find a serving base station in the area, requests one or more physical link profiles from a network server on the network, receives one or more physical link profiles from the network server in response to the requesting, determines which one of the physical link profiles exhibit a lower amount of interference with the serving base station, and then operates with the physical link profile determined to exhibit a lower amount of interference with the serving base station. | 05-06-2010 |
| 20100100790 | ENCODING OF LDPC CODES - A method and apparatus are disclosed that include encoding a codeword using a systematic low density parity check matrix using an encoder, the low density parity check matrix comprising a first sub-matrix associated with information symbols, a second sub-matrix having a block triangular structure associated with a first subset of parity check symbols and a third sub-matrix that is invertible and associated with a second subset of parity check symbols, the encoding performed over the second sub-matrix before the third sub-matrix. | 04-22-2010 |
| 20100088756 | MULTI-PATTERN PACKET CONTENT INSPECTION MECHANISMS EMPLOYING TAGGED VALUES - Methods and apparatus for performing content inspection using multi-pattern packet content inspection mechanisms employing tagged values. Pattern data structures are employed to facilitate multi-pattern searches via corresponding string-search algorithm machines. The pattern data structures include tagged values defining search offsets and depths for corresponding search patterns. Incoming packets are classified to flows, and stored in corresponding flow queues. Flow table entries are used to identify the pattern data structure for a given flow. During content inspection, the algorithm machine employs the tagged values to effectively skip portions of a data stream up to the offset for each search pattern and to cease searching for a pattern upon reaching the depth for the pattern. | 04-08-2010 |
| 20100082718 | COMBINED SET BIT COUNT AND DETECTOR LOGIC - A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word). | 04-01-2010 |
| 20100081485 | APPARATUS, SYSTEM AND METHOD CAPABLE OF INTEGRATING A CELLULAR PHONE STACK IN AN EXTENDED FIRMWARE INTERFACE (EFI) LAYER - An embodiment of the present invention provides an apparatus, comprising a wireless device capable of integrating a cellular phone stack in an extended firmware interface (EFI) layer, wherein the cellular phone stack within the EFI layer may include TDMA or CDMA0-based technology. An embodiment of the present invention may further provide at least one agent running under an OS/EFI continuously monitoring said wireless device status, OS availability and remaining power and wherein anytime events occur where said OS is unavailable, missing, infected, corrupted or when the remaining power is less than threshold, the wireless device may switch itself to the low power secure EFI mode where it may continue to use basic cell phone services and applications seamlessly. | 04-01-2010 |
| 20100081379 | WIRELESSLY POWERED SPEAKER - In accordance with various aspects of the disclosure, a method and apparatus is disclosed that includes features of wirelessly powering a speaker. A system of coupled magnetic resonators may be used to deliver both power and audio wirelessly to a receiver/radio receiver/speaker. | 04-01-2010 |
| 20100073892 | CIRCUIT BOARD INCLUDING STUBLESS SIGNAL PATHS AND METHOD OF MAKING SAME - A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment. | 03-25-2010 |
| 20100072580 | ULTRA-THIN OXIDE BONDING FOR SI TO SI DUAL ORIENTATION BONDING - A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms. | 03-25-2010 |
| 20100072043 | ELECTROMECHANICAL SWITCH WITH PARTIALLY RIGIDIFIED ELECTRODE - An electromechanical switch with a rigidified electrode includes an actuation electrode, a suspended electrode, a contact, and a signal line. The actuation electrode is disposed on a substrate. The suspended electrode is suspended proximate to the actuation electrode and includes a rigidification structure. The contact is mounted to the suspended electrode. The signal line is positioned proximate to the suspended electrode to form a closed circuit with the contact when an actuation voltage is applied between the actuation electrode and the suspended electrode. | 03-25-2010 |
| 20100068633 | SUB-RESOLUTION ASSIST FEATURES - Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature. | 03-18-2010 |
| 20100066303 | METHOD AND DEVICE FOR CHARGING PERIPHERALS - The invention includes a peripheral charging system for a computer. The peripheral charging system comprises a retention mechanism configured to retain a peripheral having a battery, the retention mechanism comprising a charging mechanism, and a system battery electrically connected to the charging mechanism. When the peripheral is retained by the retention mechanism, the peripheral contacts the charging mechanism of the retention mechanism to charge the peripheral battery. The invention also comprises a method for charging a peripheral for a mobile computing device. The method comprises retaining the peripheral in a retention mechanism of the mobile computing device, and charging a battery of the peripheral device from a battery of the mobile computing device. The retention mechanism of the mobile computing device includes a charging mechanism configured to supply charge to a charging mechanism of the peripheral. | 03-18-2010 |
| 20100061377 | FLEXIBLE AND EXTENSIBLE RECEIVE SIDE SCALING - In an embodiment, a method is provided. The method of this embodiment provides in response to receiving a packet, looking up a packet characteristic in one of at least one protocol table to determine one or more fields of the packet to use as a hash value, applying a hash function to the hash value to obtain a hash result, and using the hash result to determine one of a plurality of processors on which to process the packet. | 03-11-2010 |
| 20100045261 | DESIGN FOR TESTABILITY TECHNIQUE FOR PHASE DETECTORS USED IN DIGITAL FEEDBACK DELAY LOCKED LOOPS - A circuit for testing phase detectors in a delay locked loop is provided. The circuit uses a second phase detector arranged to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester. | 02-25-2010 |
| 20100030930 | BANDWIDTH CONSERVING PROTOCOL FOR COMMAND-RESPONSE BUS SYSTEM - A command-response bus protocol reduces the number of response transactions generated on a bus. According to an embodiment, an array of data is divided into a number of packets and transmitted over the bus in respective transactions. The transactions each include a writeback flag, which is enabled for the last packet but otherwise disabled. When a receiver of the packets observes the enabled writeback flag, it generates a response transaction. The response transaction indicates either that all packets of the array were received properly or that the commanded operation has been completed for the entire array. Overall, the number of bus transactions are reduced with respect to alternative schemes that require a response transaction for each transmitted packet. | 02-04-2010 |
| 20100022083 | CARBON NANOTUBE INTERCONNECT STRUCTURES - A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles. | 01-28-2010 |
| 20100017549 | MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS - A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed. | 01-21-2010 |
| 20100011872 | METHOD AND APPARATUS FOR A SELF-POWERED RFID-READABLE PEDOMETER - A device, system and method for analyzing a user's motion using a piezoelectric film to generate a plurality of deformation signals based upon an associated plurality of deformations, an EEPROM to record data associated with the plurality of deformation signals, and a transceiver to receive at least a portion of the recorded data from the EEPROM and to transmit data, wherein the analysis may determine an abnormality in the user's gait. | 01-21-2010 |
| 20090327792 | BUS FREQUENCY ADJUSTMENT CIRCUITRY FOR USE IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE - The present disclosure relates to clock divider circuitry for use in a dynamic random access memory device. In accordance with at least one embodiment the disclosure includes a method having a number of operations. Some operations may include receiving a clock input signal having a first frequency from a clock input receiver at clock divider circuitry, the clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and the clock input signal. The output signal may have a second frequency that is a fraction of the first frequency. The method may further include receiving said clock input signal and said output signal at a multiplexer and generating a multiplexed output. The method may additionally include receiving said multiplexed output at a first bus configured to receive said multiplexed output and to reduce an operational frequency of said first bus in response to an increase in an operational frequency of a second bus associated with said memory device. | 12-31-2009 |
| 20090327596 | MEMORY CONTROLLER USING TIME-STAGGERED LOCKSTEP SUB-CHANNELS WITH BUFFERED MEMORY - Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations. | 12-31-2009 |
| 20090322403 | MULTIPLE-PHASE, DIFFERENTIAL SAMPLING AND STEERING - Methods and systems to controllably steer multiple phases of a differential signal, including to generate a differential current in response to a differential voltage, to controllably steer the differential current between multiple output circuits in response to corresponding control signals, which may be out of phase with respect to one another, and to generate multiple corresponding outputs corresponding to the multiple steered phases of the current. A differential input circuit and a current steering circuit may be common to multiple output circuits, and a common offset compensation may be provided to compensate for a substantial portion of offset associated with the multiple outputs. | 12-31-2009 |
| 20090316800 | Low speed access to dram - Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver. | 12-24-2009 |
| 20090316658 | MOBILE NETWORK HANDOVER INITIATION - Methods and systems to monitor wireless signal strengths associated with wireless access points, and to initiate a handover procedure upon one or more thresholds. A handover may be initiated prior to a loss of an existing network connection. | 12-24-2009 |
| 20090316374 | Reduced Porosity High-K Thin Film Mixed Grains for Thin Film Capacitor Applications - A method including forming a layer of a first ceramic material on a substrate; and after forming the layer, forming a second ceramic material on the layer of the first ceramic material, the formed second ceramic material including an average grain size less than a grain size of the first ceramic material. An apparatus including a first electrode; a second electrode; and a sintered ceramic material, wherein the ceramic material comprises first ceramic grains defining grain boundaries therebetween and second ceramic grains having an average grain size smaller than a grain size of the first ceramic grains. A system including a device including a microprocessor, the microprocessor coupled to a circuit board through a substrate, the substrate including a capacitor structure formed on a surface, the capacitor structure including a first electrode, a second electrode, and a sintered ceramic material disposed between the first electrode and the second electrode. | 12-24-2009 |
| 20090315114 | STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS - Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device. | 12-24-2009 |
| 20090310506 | SWITCHING SCHEMES FOR MULTIPLE ANTENNAS - Signals from multiple antennas are evaluated in a wireless device having one receiver chain and the antenna receiving the highest quality signals is selected. The signal quality from the multiple antennas may be evaluated using the short symbols in the preamble or the beacon signals and the antennas dynamically selected to improve the performance of the wireless communications device. | 12-17-2009 |
| 20090309884 | APPARATUS AND METHOD FOR SELECTABLE HARDWARE ACCELERATORS IN A DATA DRIVEN ARCHITECTURE - A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit. | 12-17-2009 |
| 20090307493 | SYSTEM AND METHOD FOR COMBINING USER AND PLATFORM AUTHENTICATION IN NEGOTIATED CHANNEL SECURITY PROTOCOLS - A network security handshake exchange for combining user and platform authentication. The security handshake exchange performs operations on a pre-master secret to increase identity verification and security. The pre-master secret is augmented and authenticated with platform identity and user identity credentials of one endpoint. A second phase of exchanges may include exchange of a master secret that is the pre-master secret modified with platform identity and user identity of the other endpoint. | 12-10-2009 |
| 20090307469 | REGISTER SET USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE - A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread. | 12-10-2009 |
| 20090307108 | BUSINESS PROCESS AND APPARATUS FOR ONLINE PURCHASES USING A RULE-BASED TRANSFERABLE SHOPPING BASKET - An online shopping basket is acquired by a buyer from an online store and is customized according to rules specified by the buyer. The buyer places zero or more items in the online shopping basket(s) before they are given to at least one shopper by the online store. The shopper(s) may further customize the online shopping basket(s) with rules that do not conflict with those specified by the buyer. The shopper(s) then place zero or more items in the online shopping basket(s) and return the basket(s) to the online store. Multiple online shopping baskets are merged into a single basket, and the buyer reviews the items in the merged online shopping basket and adds or removes items as necessary. The buyer then purchases the remaining items from the online store. | 12-10-2009 |
| 20090303147 | SECTORIZED, MILLIMETER-WAVE ANTENNA ARRAYS WITH OPTIMIZABLE BEAM COVERAGE FOR WIRELESS NETWORK APPLICATIONS - Planar, sectorized, millimeter-wave antenna arrays may include one or more of housings of dielectric material, such as split-blocks of a plastic material, having metallized plastic horns and waveguides formed, etched, and/or cut therein, waveguide-to-planar-transmission-line transition devices and planar structures embedded therein, and one or more integrated circuits coupled thereto. | 12-10-2009 |
| 20090303132 | PLANAR ANTENNAS AND BANDWIDTH EXTENSION APERTURES - Methods and systems to implement planar antennas and bandwidth extension apertures, including planar antennas etched in metal clad printed circuit board materials, relatively small-scale planar antennas having dimensions in a range of centimeters and/or millimeters, planar antennas to operate in GHz frequency ranges, and bandwidth extension apertures to alter an antenna impedance, reduce an antenna return loss, reduce an antenna Q factor, and/or increase an antenna frequency bandwidth. | 12-10-2009 |
| 20090296938 | Methods and apparatus for protecting digital content - A processing system to serve as a source device for protected digital content comprises a processor and control logic. When used by the processor, the control logic causes the processing system to receive a digital certificate from a presentation device. The processing system then uses public key infrastructure (PKI) to determine Whether the presentation device has been authorized by a certificate authority (CA) to receive protected content. The processing system may also generate a session key and use the session key to encrypt data. The processing system may transmit the encrypted data to the presentation device only if the presentation device has been authorized by the CA to receive protected content. Presentation devices and repeaters may perform corresponding operations, thereby allowing content to be transmitted and presented in a protected manner. Other embodiments are described and claimed. | 12-03-2009 |
| 20090294992 | EMBEDDING DEVICE IN SUBSTRATE CAVITY - An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device. | 12-03-2009 |
| 20090289353 | COVERED DEVICES IN A SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface. | 11-26-2009 |
| 20090285303 | MOTION ESTIMATION FOR VIDEO PROCESSING USING 2-D (SPATIAL) CONVOLUTION - A device including a two-dimensional convolution unit to perform spatial image filtering. A reference frame mirroring unit is connected to the two-dimensional convolution unit. A mean square error (MSE) decision unit is connected to the two-dimensional convolution unit to perform motion estimation by selecting the displacement that minimizes MSE. | 11-19-2009 |
| 20090279779 | Image Selection Based on Image Content - An image capture system comprises an image input and processing unit. The image input obtains image information which is then passed to the processing unit. The processing unit is coupled to the image input for determining image metrics on the image information. The processing unit initiates a capture sequence when the image metrics meet a predetermined condition. The capture sequence may store one or more images, or it may indicate that one or more images have been detected. In one embodiment, the image input is a CMOS or CCD sensor. | 11-12-2009 |
| 20090279355 | LOW POWER FLOATING BODY MEMORY CELL BASED ON LOW BANDGAP MATERIAL QUANTUM WELL - Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell. | 11-12-2009 |
| 20090276581 | METHOD, SYSTEM AND APPARATUS FOR REDUCING MEMORY TRAFFIC IN A DISTRIBUTED MEMORY SYSTEM - The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a directory of a memory slice, said presence vector indicating whether a line in local memory has been cached. The method may further include protecting said memory slice from cache coherency violations via a home agent configured to transmit and receive data from said memory slice, said home agent configured to store a copy of said presence vector. The method may also include receiving a request for a block of data from at least one processing node at said home agent and comparing said presence vector with said copy of said presence vector stored in said home agent. The method may additionally include eliminating a write update operation between said home agent and said directory if said presence vector and said copy are equivalent. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 11-05-2009 |
| 20090254760 | DATA SECURITY - In one embodiment, a method is provided that may include encrypting, based least in part upon at least one key, one or more respective portions of input data to generate one or more respective portions of output data to be stored in one or more locations in storage. The method of this embodiment also may include generating, based at least in part upon the one or more respective portions of the output data, check data to be stored in the storage, and/or selecting the one or more locations in the storage so as to permit the one or more respective portions of the output data to be distributed among two or more storage devices comprised in the storage. Many modifications, variations, and alternatives are possible without departing from this embodiment. | 10-08-2009 |
| 20090254714 | Method and Apparatus for Exploiting Parallelism Across Multiple Traffic Streams Through a Single Channel - Methods of obtaining, enqueueing and executing several memory transactions are described, where the memory transactions may be generated in a first order but executed in a second order. Despite the relaxed ordering, essential programming paradigms such as producer-consumer relationships are not affected. Chipsets and systems using the methods are also described and claimed. | 10-08-2009 |
| 20090249364 | DETERMINING COMPONENT ACCESSIBILITY USING COMPONENT DESCRIPTORS - Embodiments of methods and apparatuses for providing a substantially platform independent firmware module that can operate on multiple platforms incorporating various components, whether provided or known to the firmware/platform provider are disclosed. Other embodiments may also be disclosed. | 10-01-2009 |
| 20090249102 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN MULTI-CHANNEL MEMORY CONTROLLER SYSTEMS - Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel. | 10-01-2009 |
| 20090245133 | BROADCAST/MULTICAST BASED NETWORK DISCOVERY - Embodiments of the invention relate to apparatus, system and method for use of WLAN access enabled mobile devices such as notebooks and handheld communication devices. In particular, embodiments of the invention relate to methodology whereby WiFi enabled devices can automatically select the appropriate service provider, in a power efficient manner, thereby taking advantage of different services offered by different service providers. | 10-01-2009 |
| 20090240894 | METHOD AND APARATUS FOR THE SYNCHRONIZATION OF DISTRIBUTED CACHES - A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub. | 09-24-2009 |
| 20090237884 | Electromagnetically-actuated micropump for liquid metal alloy - The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the liquid metal alloy in the cavity towards the electromagnet to expand the flexible sidewalls; inducing a second portion of the liquid metal alloy to enter the cavity from an inlet end of a pipe within the closed-loop system; turning off the electromagnet; repelling the liquid metal alloy in the cavity away from the electromagnet to contract the flexible sidewalls; and inducing a third portion of the liquid metal alloy to exit the cavity to an outlet end of the pipe. | 09-24-2009 |
| 20090237398 | DETERMINING A NODE PATH THROUGH A NODE GRAPH - Determining a node path through a node graph includes modifying the node graph in accordance with a predetermined platform performance, performing a path finding process through the node graph to obtain the node path, determining if the platform performance has changed, adjusting the node graph to compensate for a change in the platform performance, and re-performing the path finding process through the adjusted node graph to obtain the node path. | 09-24-2009 |
| 20090216981 | POWER EFFICIENT FLOW CONTROL MODEL FOR USB ASYNCHRONOUS TRANSFERS - Embodiments comprising a memory and a USB host controller coupled to the memory. The power efficiency of a USB during asynchronous transfers is increased by limiting usage of an asynchronous schedule stored in the memory when servicing a scheduled asynchronous transfer endpoint. Other embodiments may be described and claimed. | 08-27-2009 |
| 20090216900 | SCALABLE NETWORK APPARATUS FOR CONTENT BASED SWITCHING OR VALIDATION ACCELERATION - A network apparatus is provided that may include one or more security accelerators. The network apparatus also includes a plurality of network units cascaded together. According to one embodiment, the plurality of network units comprise a plurality of content based message directors, each to route or direct received messages to one of a plurality of application servers based upon the application data in the message. According to another embodiment, the plurality of network units comprise a plurality of validation accelerators, each validation accelerator to validate at least a portion of a message before outputting the message. | 08-27-2009 |
| 20090207576 | SLOTTED MAGNETIC MATERIAL FOR INTEGRATED CIRCUIT INDUCTORS - An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers. | 08-20-2009 |
| 20090199024 | METHOD, APPARATUS AND SYSTEM TO DYNAMICALLY CHOOSE AN AOPTIMUM POWER STATE - Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described. | 08-06-2009 |
| 20090198567 | Method of adaptive browsing for digital content - Providing adaptive visual browsing of digital content may be accomplished by presenting a scrolling ticker on a display for browsing of digital content available for viewing by a user of a processing system, the ticker having a plurality of items, each item including an image representing at least one of a content title and a content service provider; receiving a user input selection from a remote control device operated by the user, the user input selection selecting one of the ticker items to indicate the user's interest in the selected item; and changing at least one of the items in the ticker to another item in response to the user input selection, wherein the other item has metatags similar to or related to metatags of the selected item. | 08-06-2009 |
| 20090197436 | NON-INTRUSIVE INTERPOSER FOR ACCESSING INTEGRATED CIRCUIT PACKAGE SIGNALS - Disclosed is an interposer for accessing one or more signals from an Integrated Circuit (IC) package. The interposer is disposed between the IC package and a socket body. The interposer comprises a plurality of clearance holes and at least one connecting element. The plurality of clearance holes allows an array of contacts on a first surface of the socket body to pass through the interposer and make electrical contact with a first set of contacts of a plurality of contacts of the IC package. The at least one connecting element is configured to make electrical contact with a second set of contacts of the plurality of contacts of the IC package. The electrical contact between the at least one connecting element and the second set of contacts of the plurality of contacts of the IC package provides access to the one or more signals from the IC package. | 08-06-2009 |
| 20090193274 | System And Method of Coherent Data Transfer During Processor Idle States - Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state. | 07-30-2009 |
| 20090189910 | DELIVERING PIXELS RECEIVED AT A LOWER DATA TRANSFER RATE OVER AN INTERFACE THAT OPERATES AT A HIGHER DATA TRANSFER RATE - A number of pixels are received at a pixel rate that corresponds to a lower data transfer rate. The received pixels are delivered for display on a display device, over an interface that operates at a higher data transfer rate. These pixels are delivered as part of a stream that includes one or more codes that have been inserted between each adjacent pair of pixels so that the pixels in the stream are still delivered at the pixel rate. Other embodiments are also described and claimed. | 07-30-2009 |
| 20090189193 | SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE - A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class. | 07-30-2009 |
| 20090182989 | MULTITHREADED MICROPROCESSOR WITH REGISTER ALLOCATION BASED ON NUMBER OF ACTIVE THREADS - A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use. | 07-16-2009 |
| 20090176516 | REPETITIVE PAGING FROM A WIRELESS DATA BASE STATION HAVING A SMART ANTENNA SYSTEM - A method, system, and machine-readable medium for transmitting a downlink signal in a substantially non directional manner from a communication station to a first remote communication device on a downlink channel. The communication station includes a smart antenna system having an array of antenna elements. The method includes determining a first downlink smart antenna processing strategy for transmitting in a first non-directional manner, transmitting a first downlink message from the communication station in the first non-directional manner using the first downlink smart antenna processing strategy, and repeating transmitting the first downlink message from the communication station in a second non-directional manner. The repeated transmitting is non-identical repetition to facilitate the interference environment being different in the repetition. | 07-09-2009 |
| 20090175168 | PACKET FLOW CONTROL - Packet flow control techniques are disclosed. In one example case, a flow control method is provided that includes transmitting a plurality of packets with an inter-packet gap disposed between neighboring packets, and increasing the length of the inter-packet gap to decrease packet rate, wherein the increased length is selected based on severity of a congestion condition. In another example case, a flow control system is provided that includes circuitry for transmitting and/or receiving a plurality of packets with an inter-packet gap disposed between neighboring packets, and circuitry for increasing the length of the inter-packet gap to decrease packet rate, wherein the increased length is selected based on severity of a congestion condition. The techniques can be carried out at one node of a communication system (such as in a backplane switch) or multiple nodes (such as between a backplane switch and a circuit board operatively coupled to the backplane). | 07-09-2009 |
| 20090172410 | PERSONAL VAULT - In some embodiments data input to an input device is encrypted before it is received by any software, and information is stored securely so that the information is not accessible to any software. Other embodiments are described and claimed. | 07-02-2009 |
| 20090172396 | SECURE INPUT - In some embodiments input information received at an input device is encrypted before it is sent to a computer to be coupled to the input device. Other embodiments are described and claimed. | 07-02-2009 |
| 20090172389 | SECURE CLIENT/SERVER TRANSACTIONS - In some embodiments a controller establishes a secured connection between a remote computer and a user input device and/or a user output device of a computer. Information is securely transmitted in both directions between the remote computer and the user input device and/or user output device in a manner such that a user of the user input device and/or the user output device securely interacts with the remote computer in a manner that cannot be maliciously interfered with by software running on the computer. Other embodiments are described and claimed. | 07-02-2009 |
| 20090172388 | PERSONAL GUARD - In some embodiments data input to an input device is encrypted before it is received by any software. Other embodiments are described and claimed. | 07-02-2009 |
| 20090172280 | SYSTEMS AND METHODS FOR FAST STATE MODIFICATION OF AT LEAST A PORTION OF NON-VOLATILE MEMORY - A method is provided for reducing the number of writes in a non-volatile memory ( | 07-02-2009 |
| 20090172214 | USB HOST CONTROLLER - In some embodiments, a USB host controller interface interfaces with a USB device at a device level by presenting a pipe of the USB device as a work queue to system software. Other embodiments are described and claimed. | 07-02-2009 |
| 20090172056 | RANDOM NUMBER GENERATOR - Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure. | 07-02-2009 |
| 20090172048 | MEMORY STORAGE OF FILE FRAGMENTS - In some embodiments a beginning portion of a disk drive file fragment is stored in a memory, and the beginning portion of the disk drive file fragment is accessed from the memory. Other embodiments are described and claimed. | 07-02-2009 |
| 20090169130 | ACCELERATING THE HOUGH TRANSFORM - The present disclosure describes a method and apparatus for accelerating computation of a Hough transform of a plurality of digital images of known width and height dimensions. The method includes determining a plurality of Hough values for each pixel location based on the width and height dimensions. The method further includes generating a lookup table comprising an array of Hough values corresponding to one or more Hough parameters of at least one geometric shape in at least one digital image. Each element in the array of Hough values may be based on a value of one or more Hough parameters and at least one of a height value or a width value. The method may include receiving a plurality of digital images having known width and height dimensions. The method may further include selecting, for at least one nonzero pixel of at least one of the plurality of digital images, the Hough values from the lookup table. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 07-02-2009 |
| 20090169011 | APPARATUS AND METHOD FOR NEGOTIATING PAIRWISE MASTER KEY FOR SECURING PEER LINKS IN WIRELESS MESH NETWORKS - A system and method for negotiating a pairwise master key (“PMK”) in wireless mesh networks. The system includes a plurality of mesh points that are configured to perform an abbreviated handshake protocol in negotiating a PMK and establishing a secure connection. The method for establishing a negotiated PMK is based on selecting a PMK before transmitting any data, and arranging available PMKs in a predetermined list so that a PMK can be negotiated in a limited number of exchanges. | 07-02-2009 |
| 20090168845 | HOPPED ULTRAWIDEBAND WIRELESS - In some embodiments a transceiver includes a quadrature phase-shift keying modulator and/or demodulator to transmit and/or receive a frequency-hopping ultrawideband radio signal. Other embodiments are described and claimed. | 07-02-2009 |
| 20090167484 | RFID ENABLED LIGHT SWITCHES - An embodiment of the invention relates to a for remote control of an electrical circuit, comprising an RFID source, a remotely-mounted switch operatively coupled to an RFID tag, and an RFID receiver operatively coupled to an electrical circuit, wherein a change in state of the remotely-mounted switch is detected by the RFID tag and transmitted to the RFID receiver to control the electrical circuit. | 07-02-2009 |
| 20090166804 | FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS - Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another. | 07-02-2009 |
| 20090166769 | METHODS FOR FABRICATING PMOS METAL GATE STRUCTURES - Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air. | 07-02-2009 |
| 20090161802 | RECEIVER WITH ADAPTIVE POWER CONSUMPTION AND A METHOD IMPLEMENTED THEREIN - A receiver and a method for controlling power consumption therein are disclosed. The receiver comprises at least one front-end module, an amplifier, an Analog to Digital Converter (ADC) module, a spectrum analyzer and a control module. The at least one front-module is configured to receive and process a RF signal to obtain an IF signal. The amplifier is configured to amplify the IF signal received from the at least one front-end module with a variable gain. The ADC module receives the amplified IF signal and converts into a digital signal. Further, the spectrum analyzer estimates a power level of a signal information and a power level of a noise in the digital signal. Thereafter, the control module controls a variable gain of the amplifier and a variable dynamic range of the ADC based on the power level of the signal information and the noise in the digital signal. | 06-25-2009 |
| 20090160068 | FLIP-CHIP PACKAGE AND METHOD OF FORMING THEREOF - A flip-chip package is disclosed. The flip-chip package includes a substrate comprising at least one build-up layer. At least one longitudinal trench is formed in at least one build-up layer of the substrate. The at least one longitudinal trench filled with a conductive material. A conductive plane may be disposed at least partially on the at least one longitudinal trench. An insulating layer may cover the conductive plane and, at least in part, at least one build-up layer of the substrate. The solder resist layer may include a plurality of openings partially exposing the conductive plane. A plurality of conductive pads may be disposed on the conductive plane through the plurality of openings. A method for fabricating the flip-chip package is also disclosed. | 06-25-2009 |
| 20090159975 | INTEGRATION OF PLANAR AND TRI-GATE DEVICES ON THE SAME SUBSTRATE - An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed. | 06-25-2009 |
| 20090154825 | REDUCTION FILTER BASED ON SMART NEIGHBOR SELECTION AND WEIGHTING (NRF-SNSW) - The present disclosure describes a method and apparatus for filtering noise in a video image, comprising receiving a first video image, a second video image and motion information wherein the first image may be an image to be filtered and the second image may be a filtered image wherein the second image may be temporally related to said first image. The method may further include, for at least one pixel in the first video image, selecting at least one neighbor of the pixel from the first video image and selecting at least one neighbor of the pixel from said second video image, wherein selection of the neighbors from the first video image and the second video image may be based on said motion information; selecting a subset of the neighbors wherein the subset may be less than or equal to a sum of neighbors from the first video image and the second video image; determining a weighted average of the subset of said neighbors and the pixel; and outputting the weighted average as a filtered pixel of the first video image. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 06-18-2009 |
| 20090148675 | MICELLE-CONTROLLED NANOPARTICLE SYNTHESIS FOR SERS - The methods and apparatus disclosed herein concern nanoparticle layers uniformly distributed on a surface or substrate. In certain embodiments of the invention, the nanoparticle layers are of use for Raman spectroscopy. In certain embodiments of the invention, a micelle-metal ion complex is formed and deposited on a surface. The polymer component of the micelle-metal ion complex may be removed resulting in formation of nanoparticles of a uniform size and distribution. The polymers may contain one or more ligands. The number and type of ligands in a micelle will determine the type and amount of metal ion bound to the micelle, in turn determining the metal composition and size of the nanoparticles. The distribution micelle-metal ion complexes on a surface may determine the distribution and periodicity of the nanoparticle layer. In other embodiments, rod or columnar-shaped nanoparticles may be generated. Other embodiments concern the generation of uniform alloy nanoparticles. | 06-11-2009 |
| 20090146474 | System and Device for Monitoring and Assisting Human Gross Motor Skills - A system includes a lift chair having sensors embedded therein to determine various factors such as the amount of pressure exerted in various portions of the chair, the activity level of the chair user, whether the chair is occupied and which user is currently occupying the chair, and how much assistance the chair provides the user. The information detected by the sensors can be transmitted via the Internet, for example, to a third party device, such as a doctor's personal computer, which is also hooked up to the internet and is capable of receiving periodic updates to monitor use of the chair or modify the rules that govern the use of the chair. The user can override the pre-set rules for use of the chair by using an override button on a user control device. | 06-11-2009 |
| 20090145579 | METHOD AND AN APPARATUS FOR COOLING A COMPUTER - A heat exchanging system comprising circulating fluid through a tube coupled to an electronic component in a first part of a computing device and to a heat transfer plate in a second part of the computing device. | 06-11-2009 |
| 20090144525 | APPARATUS AND METHOD FOR SCHEDULING THREADS IN MULTI-THREADING PROCESSORS - An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly. | 06-04-2009 |
| 20090138681 | SYNCHRONIZATION OF PARALLEL PROCESSES - A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to facilitate synchronization between parallel processes. According to an aspect, an instruction set architecture includes circuitry that handles a speculative execution instruction and a speculation termination instruction. The speculative execution instruction may be an instruction that takes first and second operands, causes the processor to speculatively execute additional instructions if a memory location contains a value, and causes the processor to start executing instructions from an address indicated by the second operand if a mis-speculation occurs, and the speculation termination instruction may be an instruction that causes the processor to begin retiring the additional instructions. | 05-28-2009 |
| 20090138627 | APPARATUS AND METHOD FOR HIGH PERFORMANCE VOLATILE DISK DRIVE MEMORY ACCESS USING AN INTEGRATED DMA ENGINE - A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a data access request to VDD memory implemented within volatile system memory. Once a data access request is detected, a VDD driver may issue a DMA data request to perform the data access request from the VDD. Accordingly, in one embodiment, the job of transferring data to/from a VDD memory implemented within an allocated portion of volatile system memory is offloaded to a DMA engine, such as, for example, an integrated DMA engine within a memory controller hub (MCH). Other embodiments are described and claimed. | 05-28-2009 |
| 20090135780 | PREEMPTIVE DYNAMIC FREQUENCY SELECTION - Briefly, in accordance with one embodiment of the invention, an access point may preemptively broadcast an alternate channel to switch to, along with an indication of the beacon timing for the alternate channel, prior to any catastrophic interference. The access point may switch to the alternate channel in the event of interference on the original channel without attempting to broadcast the alternate channel during the interference event. A mobile user may then know in advance of the interference event which alternate channel the access point switched to and may switch to the alternate channel. | 05-28-2009 |
| 20090135139 | INTEGRATED INPUT AND DISPLAY DEVICE FOR A MOBILE COMPUTER - A device and system are disclosed. In one embodiment the device comprises a primary display unit, a base unit coupled to the primary display unit, and a touch-sensitive secondary display unit, coupled to the base unit, operable to receive input from a user and display information for the user. | 05-28-2009 |
| 20090133008 | UNWIND INFORMATION FOR OPTIMIZED PROGRAMS - Analyzing a first binary version of a program and unwind information associated with the first binary version of the program, performing optimization on the first binary version of the program to produce a second binary version of the program based at least in part on the results of the analysis, and generating new unwind information for the second binary version of the program based at least in part on the results of the analysis and at least in part on the optimization performed. | 05-21-2009 |
| 20090132809 | Method and Apparatus for the Provision of Unified Systems and Network Management of Aggregates of Separate Systems - A method and apparatus for the provision of unified systems and network management of aggregates of separate systems is described herein. | 05-21-2009 |
| 20090129022 | Micro-chimney and thermosiphon die-level cooling - A method and arrangement for dissipating heat from a localized area within a semiconductor die is presented. A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area. As such, thermal stress on the die is reduced, and total heat from the die is more readily dissipated. | 05-21-2009 |
| 20090127541 | REDUCING DEFECTS IN SEMICONDUCTOR QUANTUM WELL HETEROSTRUCTURES - Reducing defects in semiconductor quantum well structures is generally described. In one example, an apparatus includes a semiconductor substrate including silicon, a buffer film epitaxially grown on the semiconductor substrate, the buffer film comprising silicon, germanium, and an impurity, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film and wherein the impurity disrupts lattice structure dislocation gliding in at least the first semiconductor film. | 05-21-2009 |
| 20090121943 | ANTENNA SYSTEM USING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TECHNIQUES - Apparatus, system, and method are described for a complementary metal oxide semiconductor (CMOS) integrated circuit device having a first metal layer that includes a radiating element and a second metal layer that includes a first conductor coupled to the radiating element. The first conductor and the radiating element are mutually coupled to form an antenna to wirelessly communicate a signal. | 05-14-2009 |
| 20090119671 | REGISTERS FOR DATA TRANSFERS - A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine. | 05-07-2009 |
| 20090119524 | Energy Efficient Ethernet Using Active/Idle Toggling - Generally, this disclosure describes an energy-efficient Ethernet communications approach. In at least one embodiment described herein, an Ethernet controller may be configured to operate in an active power state to transmit or receive data packets at a maximum available link speed. The maximum available link speed may be determined by a negotiation between the Ethernet controller and a link partner coupled to the Ethernet controller. Once the data packets are transmitted or received, the Ethernet controller may be configured to operate in an idle power state to reduce energy consumption. | 05-07-2009 |
| 20090119457 | MULTITHREADED CLUSTERED MICROARCHITECTURE WITH DYNAMIC BACK-END ASSIGNMENT - A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units. | 05-07-2009 |
| 20090119446 | DIVIDED BITLINE FLASH MEMORY ARRAY WITH LOCAL SENSE AND SIGNAL TRANSMISSION - A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A read operation of selected bitlines of a selected memory segment is performed by a segment data handler coupled to the selected memory segment locally and the read data is transmitted to the data cache. A segment data handler is configured to get read data from the selected bitlines by first pre-charging the bitlines and sensing the bitlines. Further, the read data is transmitted to the data cache through all of the segment data handlers in a sequential manner, if present between the selected memory segment and the data cache. | 05-07-2009 |
| 20090116586 | DIRECT CONVERSION RECEIVER AND METHOD FOR CORRECTING PHASE IMBALANCE THEREIN - A direct conversion receiver and a method for correcting phase imbalance therein is disclosed. An input signal is applied to an in-phase channel and a quadrature channel of the receiver. The input signal is processed by the direct conversion receiver to obtain an in-phase zero intermediate frequency (IF) signal in the in-phase channel and a quadrature zero-IF signal in the quadrature channel. The in-phase zero-IF signal and the quadrature zero-IF signal are filtered to obtain a fixed band signal. A phase imbalance correction value is obtained for the fixed-band quadrature zero-IF signal as a function of the frequency of the fixed-band in-phase zero-IF signal and the fixed-band quadrature zero-IF signal. The in-phase zero-IF signal and the quadrature zero-IF signal are sampled and the phase imbalance correction value is applied using an interpolation to the sampled quadrature zero-IF signal or to the sampled in-phase zero-IF signal to correct the phase imbalance in the direct conversion receiver. | 05-07-2009 |
| 20090115552 | PACKAGE FOR SUPPRESSING SPURIOUS RESONANCE IN AN FBAR - Disclosed is a package having a thin film bulk acoustic resonator (FBAR). The package may be utilized for suppressing spurious resonance occurred during operation of the FBAR. The package includes a negative impedance converter (NIC) operatively coupled to the FBAR through at least one interconnect. The at least one interconnect includes transmission lines and bonding wires. The package further includes a filter operatively coupled to the NIC. The filter exhibits a parallel resonance at a predefined frequency. The parallel resonance exhibited by the filter is converted to a series resonance by the NIC such that the series resonance of the NIC is responsible for suppressing the spurious resonance occurring during the operation of the FBAR. | 05-07-2009 |
| 20090113262 | SYSTEM AND METHOD FOR CONDITIONING AND IDENTIFYING BAD BLOCKS IN INTEGRATED CIRCUITS - An electronic system of an Integrated circuit (IC) for conditioning and identification of bad blocks in the IC is disclosed. The electronic system includes at least one cyclic scan chain and at least one multiplexer. A cyclic scan chain includes a plurality of flip-flops, which are connected in a cascaded manner. A multiplexer is connected between two adjacent flip-flops of the cyclic shift register. The multiplexer has a first input pin connected to output of a first flip-flop, a second input pin connected to a user pin and an output pin connected to an input of a second flip-flop. The multiplexer is configured to condition the plurality of flip-flops through the user pin by programming logic bits in the plurality of flip-flop. The output of the first flip-flop is configured to read the logic bits in the plurality of flip-flops to identify a bad block in the IC. | 04-30-2009 |
| 20090109931 | METHOD FOR CODING ADDITIONAL INFORMATION IN A MEDIA ACCESS PROTOCOL (MAP) MESSAGE - Disclosed is a method for reducing number of bits in a Media Access Protocol (MAP) message. The MAP message comprises a plurality of information elements grouped into one of a first set of information elements and a second set of information elements. The first set of information elements are arranged in a pre-defined order and each of the second set of information elements is inserted into one of a prefix position to the pre-defined order, a suffix position to the pre-defined order and an intermediate position in-between two information elements in the pre-defined order. Each information element of the second set of information elements is then coded based on position of the information element relative to the position of the first set of information elements in the pre-defined order, thereby reducing the number of bits in the MAP message. | 04-30-2009 |
| 20090108455 | INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF - A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material. | 04-30-2009 |
| 20090103769 | COGNITIVE CONTROL FRAMEWORK FOR AUTOMATIC CONTROL OF APPLICATION PROGRAMS EXPOSURE A GRAPHICAL USER INTERFACE - The present invention relates generally to automatic control of software application programs and image analysis and, more specifically, to analyzing graphical component, an execution scenario script, and a playback component. The recording component is adapted to capture user input data and images displayed by the graphical user interface during a recording phase of execution of the application program, and to analyze the captured user input data and displayed images to generate an execution scenario (script) during the recording phase. The execution scenario may be written in a selected high level language (e.g., XML). The playback component is adapted to generate simulated user input data based on the execution scenario during a playback phase of execution of the application program, to input the simulated user input data to the application program, to perform image analysis on images displayed by the graphical user interface as a result of processing the simulated user input data during the playback phase and captured displayed images from the recording phase; and to automatically control execution of the application program based at least in part on the image analysis. | 04-23-2009 |
| 20090102850 | Error Diffusion for Display Frame Buffer Power Saving - Methods and apparatuses for error diffusion for display frame buffer power saving are described herein. According to one embodiment, pixels of a color plane of image data are stored in a first segment and a second segment of a frame buffer during a normal power state. During a low power state, an error diffusion operation is performed on the pixels to reduce a color depth of the pixels. Thereafter, at least a portion of the pixels with reduced color depth is stored in the first segment of the frame buffer during the low power state without accessing the second segment of the frame buffer. Other methods and apparatuses are also described. | 04-23-2009 |
| 20090097602 | APPARATUS AND METHOD FOR NON-CONTACT SENSING USING TEMPORAL MEASURES - An embodiment of the invention relates to a sampling circuit comprising at least one clock, a reference trace, a sensor trace adapted to be connected to a sensing element, and a device to measure a length of delay between a reference signal transmission time of a reference signal transmitting through the reference trace and a sensed signal transmission time of a sensed signal transmitting through the sensor trace, wherein the length of delay is determined by counting the number of burst tones occurring during the length of delay. | 04-16-2009 |
| 20090097600 | DIVERSITY RECEIVER AND METHOD FOR CONTROLLING POWER THEREOF - The present disclosure provides a diversity receiver. The diversity receiver includes a plurality of tuners, a plurality of demodulators operatively coupled to the plurality of tuners and a controller operatively coupled to the plurality of demodulators and the plurality of tuners. Each tuner is capable of receiving a modulated signal from a path of a plurality of distinct paths. The controller determines information for each path and computes a ratio of signal strength to an additive noise for each path based on determined information. Further, the controller adjusts power of signal in each path based on comparison of computed ratio of signal strength to additive noise with a predetermined threshold. The diversity receiver also includes a MRC circuitry operatively coupled to the plurality of demodulators and configured to combine the signal of each path for obtaining a resultant combined signal having an improved ratio of signal strength to additive noise. | 04-16-2009 |
| 20090097456 | METHOD FOR ACHIEVING FAIRNESS IN A NETWORK - Disclosed are a method and a computer program product for achieving fairness in utilization of a channel in a network. The network includes plurality of stations such that at least one station of the plurality of stations includes at least one radio. The at least one radio may fail to access the channel even when the channel is available for performing transmission. The method includes determining a number of idle slots occurred at the channel during a disruption period when the at least one radio is unavailable for transmission. The number of idle slots occurred during the disruption period may be accumulated as a credit. Based on the accumulated credit, an initial value of a backoff counter of the at least one station may be reset. The reset initial value of the backoff counter enables the at least one radio to utilize the accumulated idle slots for next transmission. | 04-16-2009 |
| 20090097426 | METHOD FOR IMPROVING POWER EFFICIENCY OF SUBSCRIBER STATIONS - Disclosed is a method for improving power efficiency of subscriber stations in a communication network. A subscriber station is uniquely identified by a base station using a connection Identifier (CID). The method includes splitting CIDs of subscriber stations to form a plurality of first parts and a plurality of second parts. The method includes generating an index including a plurality of entries and transmitting the index to a plurality of subscriber stations by the base station. One or more subscriber stations switch to a power-saving mode on absence of a match between each entry of the plurality of entries with an equivalent part of CIDs associated with the one or more subscriber stations, thereby conserving power and improving power efficiency of the subscriber station. Further, at least one information element in a sub-MAP message may be compressed to reduce overhead. | 04-16-2009 |
| 20090097187 | MULTI-LAYER CERAMIC CAPACITOR WITH LOW SELF-INDUCTANCE - A Multi-layer Ceramic Capacitor (MLCC) device of a low self-inductance is disclosed. The MLCC device includes a plurality of ceramic sheets arranged in parallel to each other, a plurality of inner metal electrodes, and a plurality of outer electrodes including a pair of positive terminals and a pair of negative terminals. The plurality of inner metal electrodes and the plurality of ceramic sheets are stacked alternately to form a plurality of capacitors. The plurality of outer electrodes is disposed on corners of the plurality of ceramic sheets such that the pair of positive terminals is disposed on adjacent corners of the plurality of ceramic sheets and the pair of negative terminals is disposed on other set of adjacent corners of the plurality of ceramic sheets. An MLCC device having the plurality of outer electrodes disposed on middle portions of the edges of the plurality of ceramic sheets is also disclosed. | 04-16-2009 |
| 20090090976 | PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY - A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths. | 04-09-2009 |
| 20090089887 | Theft-deterrence method and apparatus for processor based devices - A manageability engine of a processor based device and a host theft-deterrence agent of the processor based device, jointly implement a theft-deterrence protocol with a theft-deterrence service, remotely disposed from the processor based device, to deter theft of the processor based device. The host theft-deterrence agent is configured to operate in a processor operated application execution environment of the processor based device, and the manageability engine is configured to operate outside the application execution environment. | 04-02-2009 |
| 20090089621 | Application crash resist method and apparatus - Embodiments of an application crash resist method and apparatus including an abnormal application termination service and an exception handler are disclosed herein. The service is configured to broadcast messages to cause the exception handler to be loaded by applications, and the exception handler is configured to stall abnormal termination of an application having loaded an instance of the exception handler. In various embodiments, the exception handler instances further report abnormal terminations to the service, and to receive instructions on how long to stall from the service. In various embodiments, the method and apparatus further includes a tray application through which the service obtains user inputs on how long to stall an abnormal termination from a user. | 04-02-2009 |
| 20090089546 | Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache - In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads. | 04-02-2009 |
| 20090089508 | METHOD FOR REDUCING NUMBER OF WRITES IN A CACHE MEMORY - Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a set of data of the plurality of the data in the cache memory to be flushed to a hard disk, wherein the hard disk is operatively coupled to the cache memory; flushing the set of data of the plurality of data to the hard disk from the cache memory; and writing a clean-marker to the cache memory specifying which of the plurality of the data has been flushed to the disk. | 04-02-2009 |
| 20090088015 | PICK-AND-PLACE CAP FOR SOCKET ASSEMBLY - Disclosed is a socket assembly for electrically engaging an Integrated Circuit (IC) package with a printed circuit board. The socket assembly includes a socket body and a Pick-and-Place (PnP) cap. The socket body is mounted on the printed circuit board. Further, the PnP cap is capable of detachably mounting on the socket body. An upper surface of the PnP cap includes a raised portion with multiple chamfered portions projecting out from the raised portion. The multiple chamfered portions enable easier detachment of the PnP cap from the socket body. | 04-02-2009 |
| 20090086547 | CIRCUIT FOR PERFORMING READ OPERATION IN NAND FLASH MEMORY AND METHOD THEREOF - A circuit for performing a read operation in a NAND flash memory is disclosed. The NAND flash memory includes an array of bit lines grouped into first group of bit lines and second group of bit lines. The circuit includes a plurality of pre-charging and reading circuitries connected at first end of the array of bit lines and a plurality of pre-charging circuitries connected at second end of the array of bit lines. The pre-charging and reading circuitries include a select circuit which selects one group from the first and the second group of bit lines; a first and a second circuit to pre-charge and read the selected group of bit lines from the first end. The plurality of pre-charging circuits include two select lines to select one group of bit lines, and a plurality of pre-charging transistors to pre-charge the selected group of bit lines from the second end. | 04-02-2009 |
| 20090086107 | RECIEVER SYSTEM FOR MULTIPLE BANDWIDTH TELEVISION CHANNELS - Disclosed is a receiver system, capable of receiving RF signals on television channels of multiple bandwidths. The receiver system includes a tuner, an analog IF filter, an ADC, a mixer module, one or more digital filters, an AGC module and a controller. The tuner converts an RF signal into an IF signal using a mixer frequency. The analog IF filter filters out a fixed band signal from the IF signal. The ADC module converts the fixed band signal into a digital signal, which is filtered by digital filters. The output of the digital filters is converted to a base band signal and the power level of the base band signal is controlled by the AGC module. The controller selects a mixer frequency from a group of mixer frequencies based on a function of power of the output of the AGC module by applying each mixer frequency to the tuner. | 04-02-2009 |
| 20090085660 | AGC MODULE AND METHOD FOR CONTROLLING NOISE FIGURE AND INTERMODULATION CHARACTERISTICS THEREIN - An Automatic Gain Control (AGC) module for controlling Noise Figure (NF) and IM characteristics therein is disclosed. The AGC module comprises a plurality of AGC stages. Each AGC stage comprises a differential amplifier circuit, an input signal transistor and a current-steering circuit. Differential amplifier circuits of the plurality of AGC stages receive control signals at their differential inputs and their output is connected to a common load. The input signal transistors of the plurality of AGC stages receive a common input signal and is further coupled to the differential amplifier circuit and the current-steering circuit. The current-steering circuits and the control signals at the differential amplifier circuits control gain of the each AGC stage of the plurality of AGC stage, which is used to control the NF and the IM characteristics. | 04-02-2009 |
| 20090085206 | METHOD OF FORMING SOLDER BUMPS ON SUBSTRATES - A method of forming solder bumps on a substrate is disclosed. The method includes forming a plurality of contact points on the substrate. The method further includes depositing a layer of surface finish material on the plurality of contact points. Furthermore, the method includes disposing a plurality of solder balls on the layer of surface finish material. Each solder ball of the plurality of solder balls has conductive material including a solder alloy and Phosphorus. Thereafter, the method includes applying a solder reflow process to the plurality of solder balls to configure a plurality of solder bumps on the substrate layer. The concentration of the Phosphorus in the solder material is based on target performance characteristic of the substrate having the plurality of solder bumps. | 04-02-2009 |
| 20090085027 | THREE DIMENSIONAL STRAINED QUANTUM WELLS AND THREE DIMENSIONAL STRAINED SURFACE CHANNELS BY GE CONFINEMENT METHOD - The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 04-02-2009 |
| 20090084755 | METHOD FOR FORMING MICRO-VIAS ON A SUBSTRATE - A method for forming at least one micro-via on a substrate is disclosed. The method comprises drilling at least one hole in a substrate by using a first laser beam. The first laser beam has an energy distribution, which is more at edges of the first laser beam than at the center of the first laser beam. The method further comprises forming at least one blank pattern on a top surface of the substrate and around an outer periphery of the at least one hole by removing at least a portion of the substrate by using a second laser beam. At least one blank pattern of the plurality of blank pattern corresponds to pad of the at least one micro-via. Thereafter, the method comprises filling the plurality of blank patterns and the at least one micro-via with a conductive material to form at least micro-via. | 04-02-2009 |
| 20090084598 | CORELESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - Disclosed are a coreless substrate and a method of manufacturing the same. The coreless substrate includes a solder resist layer capable of being formed on each of on a first side and a second side of a metal panel. The solder resist layer includes at least one opening. A copper layer may be plated in the at least one opening such that a height of the copper layer exceeds a height of the solder resist layer. Further, at least one dielectric layer is deposited above the copper layer, and at least one microvia drilled in the dielectric layer. The at least one microvia enables an electrical connection between at least one of the first side and the second side of the metal panel and a lower surface of the coreless substrate. | 04-02-2009 |
| 20090083554 | DYNAMIC CORE SWAPPING - An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level. | 03-26-2009 |
| 20090080408 | HEALTHCARE SEMANTIC INTEROPERABILITY PLATFORM - A system and method for efficiently linking local databases having different data formats or standards into a network, wherein a content based router is provided between each of the databases and a network “party line” bus and translates data from the respective database into a common canonical form or format so that all information within the network between the content based routers complies with the common canonical form and are validated according to single standard or mechanism, for example when information first enters the network. Also provided is a tracking or audit mechanism whereby each item of information provided with a unique network identifier when it first enters the network, and is also provided with or associated with a local identifier from each local database that originates or accesses the information item and router identifiers of the content based routers corresponding to those local databases. | 03-26-2009 |
| 20090075616 | METHOD AND APPARATUS FOR DETERMINING AN OPERATING CONDITION IN A COMMUNICATIONS SYSTEM - A communication system environment estimation apparatus and method. In one embodiment, an environment estimation apparatus according to the teachings of the present invention includes a plurality of antenna elements and a receiver coupled to receive uplink signals from the plurality of antenna elements. The apparatus also includes a signal processor coupled to receive the uplink signals to select an estimation of an environment responsive to the uplink signals received from the plurality of antenna elements. | 03-19-2009 |
| 20090075586 | SYSTEM AND METHOD FOR TRANSMITTING DATA IN A COMMUNICATION NETWORK - Disclosed is a system and method for transmitting data from a first base station to a first destination subscriber station (DSS). The first base station is capable of transmitting data directly to the first DSS through a direct route. Co-channel interference is present at neighboring cells during the transmission of the data through the direct route. The method includes selecting a relay station from a plurality of relay stations for transmitting data to the first DSS via a relay route. The relay route includes a route from the first base station to the relay station and further from the relay station to the first DSS. A height of the relay station is lower than a height of the first base station. Further, the method includes transmitting the data through the relay route when a throughput of the relay route is greater than a throughput of the direct route by a predetermined threshold. | 03-19-2009 |
| 20090073882 | DIRECTIONAL AND PRIORITY BASED FLOW CONTROL MECHANISM BETWEEN NODES - A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion. | 03-19-2009 |
| 20090070562 | METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR OR THE LIKE - In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor. | 03-12-2009 |
| 20090069970 | COMPONENT IDENTIFICATION SYSTEM AND METHOD THEREOF - Disclosed are a system and a method for identifying components in an assembly. The system comprises an assembly including one or more components and a power harvesting device, and a reader. The power harvesting device provides power to the one or more components and queries component identification information from the one or more components. The one or more components provide the power harvesting device with the component identification information which is relayed to the reader by the power harvesting device. The system allows determination of the components of the assembly while precluding the need for dismantling the assembly or powering on the assembly to run diagnostic software. | 03-12-2009 |
| 20090068830 | Microelectronic package interconnect and method of fabrication thereof - A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles. | 03-12-2009 |
| 20090065931 | PACKAGED INTEGRATED CIRCUIT AND METHOD OF FORMING THEREOF - Disclosed is a packaged integrated circuit and a method of forming thereof. The packaged integrated circuit includes a substrate, a plurality of solder bumps, a semiconductor die and a plurality of copper bumps. The plurality of solder bumps are configured on the substrate. Each of the plurality of solder bumps has a height of about 40 micrometers (μm) to about 65 μm. Further, the plurality of copper bumps are configured on the semiconductor die. Each of the plurality of copper bumps has a height of about 10 μm to about 25 μm. The semiconductor die is disposed above the substrate such that the plurality of copper bumps are coupled to the plurality of solder bumps, which in turn, couples the semiconductor die to the substrate. | 03-12-2009 |
| 20090065535 | FLUID DISPENSER SYSTEM - Disclosed is fluid dispenser valve for managing a streamlined flow of fluid. The fluid dispenser valve includes a valve chamber and a fluid inlet. The valve chamber is capable of circulating the fluid. Further, the fluid inlet is configured tangentially to the valve chamber. The fluid inlet is capable of enabling the flow of the fluid into the valve chamber. | 03-12-2009 |
| 20090065176 | THERMAL INTERFACE - Various embodiments include apparatus and method having a heat source, a thermal management device, and an interface disposed between the thermal management device and the heat source. The interface includes nanostructures to facilitate heat transfer and adhesion between the heat source and the thermal management device. | 03-12-2009 |
