Institute of Computing Technology of the Chinese Academy of Sciences Patent applications |
Patent application number | Title | Published |
20110035745 | RISC PROCESSOR APPARATUS AND METHOD FOR SUPPORTING X86 VIRTUAL MACHINE - A RISC processor apparatus and method for supporting an X86 virtual machine. The RISC processor includes: an instruction module for storing a virtual machine instruction set that supports the X86 virtual machine; a decoder for, during the decoding of an instruction of the virtual machine instruction set, distinguishing the virtual machine instruction set mode of the instruction, decoding the instruction according to the distinguished virtual machine instruction set mode, and outputting the decoded instruction to a fixed-point operation component or a floating-point operation component according to the distinguished virtual machine instruction set mode; the fixed-point operation component for processing the fixed-point instruction of the virtual machine instruction set according to the output of the decoder and outputting the execution result; the floating-point operation component for processing the floating-point instruction of the virtual machine instruction set according to the output of the decoder and outputting the execution result. | 02-10-2011 |
20100293545 | RISC PROCESSOR DEVICE AND ITS INSTRUCTION ADDRESS CONVERSION LOOKING-UP METHOD - An RISC processor and a method for converting and looking-up instruction address in the RISC processor. The device comprises a decoder, which includes a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table. The look-up table module includes: a looking-up sub-module for indexing the look-up table based on content, wherein if looking-up is hit, the corresponding content will be stored in a target register, and if not, an entry address of the not-hit service program will be stored in the target register; and an indexing sub-module for indexing the look-up table based on content and getting an index of the table entry in which the content resides. | 11-18-2010 |
20100274991 | RISC PROCESSOR DEVICE AND METHOD OF SIMULATING FLOATING-POINT STACK OPERATION THEREOF - An RISC processor device and a method of emulating a floating-point stack operation thereof The processor device comprises: a floating-point register file containing a plurality of floating-point registers; a decoding section for decoding operation instructions of the RISC processor; a floating-point operation section connected to the decoding section; a control register for controlling the status of the floating-point registers and controlling the decoding section and the floating-point operation section to emulate a floating-point register stack using the floating-point register file. The decoding section includes a pointer register for maintaining a stack operation pointer and storing the value of the stack operation pointer; the floating-point operation section includes a pointer operation module for operating the pointer register, emulating the stack operation of the stack pointer of the pointer register, modifying and monitoring the phase of the stack pointer during emulating a floating-point register stack operation. | 10-28-2010 |
20100268916 | RISC PROCESSOR AND ITS REGISTER FLAG BIT PROCESSING METHOD - The present invention discloses a RISC processor and a method of processing flag bits of a register in the RISC processor. Said RISC processor comprises a physical register stack, an operating component connected to the physical register stack and an decoder connected to the operating component; the physical register stack comprises an emulation flag register for emulating to realize flag bits of a flag register in a CISC processor; the operating component comprises a flag read-write module for reading and writing the values of the flag bits of the emulation flag register. The operating component further comprises an operating controller for performing an operation control according to the values of the flag bits of the emulation flag register when the RISC processor is in the working mode of X86 virtual machine during an operation process. | 10-21-2010 |
20100235672 | MULTI-CORE PROCESSOR, ITS FREQUENCY CONVERSION DEVICE AND A METHOD OF DATA COMMUNICATION BETWEEN THE CORES - A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a frequency conversion device, which includes a multi-bit state changing means, a multiple selector, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit. A common original clock is sent to the frequency conversion device of each processor core at work. The frequency conversion device real-timely reads the value of the frequency conversion coefficient register of a corresponding processor core and receives data transmission valid signals from other processor cores. By gating the common original clock, a frequency conversion function of the processor core is completed. In the invention, the dynamic frequency conversion function of a multi-core processor is achieved, the frequency conversion coefficient control may be performed by each processor core independently, and a highly effective synchronous communication may be maintained between the processor cores, so as to reduce the overall running consumption of the processor and save power on different processor cores of the multi-core processor or on different IP modules in SOC. | 09-16-2010 |