# INSTITUT TELECOM-TELECOM PARIS TECH

### PARIS, FR

INSTITUT TELECOM-TELECOM PARIS TECH Patent applications | ||

Patent application number | Title | Published |
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20130202107 | Integrated Silicon Circuit Comprising a Physicallly Non-Reproducible Function, and Method and System for Testing Such a Circuit - A silicon integrated circuit comprises a physically non-copyable function LPUF allowing the generation of a signature specific to said circuit. Said function comprises a ring oscillator composed of a loop traversed by a signal, being formed of N topologically identical chains of lags, connected in series and of an inversion gate, a chain of lags being composed of M delay elements connected in series. The function also comprises a control module generating N control words being used to configure the value of the delays introduced by the chains of lags on the signal traversing them. A measurement module measures the frequency of the signal at the output of the last chain of lags after the updating of the control words, and means can deduce from the frequency measurements the bits making up the signature of the circuit. A method and a system for testing such circuits are also provided. | 08-08-2013 |

20120220856 | METHOD FOR QUANTIFYING THE DEVELOPMENT OF PATHOLOGIES INVOLVING CHANGES IN THE VOLUMES OF BODIES, NOTABLY TUMORS" - A method for quantifying the development of pathologies involving changes in volume of a body represented via an imaging technique, including normalizing gray levels by a midway technique for two images I | 08-30-2012 |

20120124680 | METHOD FOR DETECTING ABNORMALITIES IN A CRYPTOGRAPHIC CIRCUIT PROTECTED BY DIFFERENTIAL LOGIC, AND CIRCUIT FOR IMPLEMENTING SAID METHOD - In a method for detecting anomalies in a circuit protected by differential logic and which processes logic variables represented by a pair of components, a first network of cells carrying out logic functions on the first component of said pairs, a second network of dual cells operating in complementary logic on the second component, the logic functions being carried out by each pair of cells in a pre-charge phase placing the variables in a known state on input to the cells and followed by an evaluation phase where a calculation is performed by the cells, the method includes detecting an anomaly by at least one non-consistent state. | 05-17-2012 |

20110307691 | METHOD OF TRACING AND OF RESURGENCE OF PSEUDONYMIZED STREAMS ON COMMUNICATION NETWORKS, AND METHOD OF SENDING INFORMATIVE STREAMS ABLE TO SECURE THE DATA TRAFFIC AND ITS ADDRESSEES - A network includes communication media transmitting streams to addressees, and a method includes: step of allocation of a cryptonymic identity to communication media by a first instance, the streams transmitted by a medium bearing a mark, as a function of its cryptonym, the cryptonymic identity of a medium being distinct from its real identity; step of reading and of analyzing the streams by a second instance, the analysis including a phase of identifying streams to their communication media by searching for similarity between the mark of the streams and the cryptonymic identity of the media, with the aid of a table listing the cryptonyms, and a phase of logging observable characteristics of the streams through the network. A behavior defined by a set of characteristics is declared typical or atypical by comparison with a given set of criteria, the table of cryptonymic identities having no link with the real identities. The invention is applied notably for combating illegal downloads, the sending of material that is unsolicited or likely to cover up identifiable malicious intentions. | 12-15-2011 |

20110261953 | METHOD FOR TESTING CRYPTOGRAPHIC CIRCUITS, SECURED CRYPTOGRAPHIC CIRCUIT CAPABLE OF BEING TESTED, AND METHOD FOR WIRING SUCH CIRCUIT - The present invention relates to a method for testing cryptography circuits. It also relates to a secure cryptography circuit capable of being tested. The cryptography circuit includes registers and logic gates, and a test thereof performs a differential power analysis on the registers of the circuit. A cryptography circuit being secure and including a first half-circuit associated with a second half-circuit operating in complementary logic, the electric power supply of the first half-circuit is separated from the electric power supply of the second half-circuit, the differential power analysis being carried out in parallel on each half-circuit, the two power supplies being combined into one and the same electric power supply after the test. | 10-27-2011 |

20110167279 | METHOD FOR PROTECTING A PROGRAMMABLE CRYPTOGRAPHY CIRCUIT, AND CIRCUIT PROTECTED BY SAID METHOD - A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal. | 07-07-2011 |