| INPAQ TECHNOLOGY CO., LTD. Patent applications |
| Patent application number | Title | Published |
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| 20120119863 | COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - A common mode filter includes at least two inductance unit sets. Each inductance unit set includes a coil leading layer, an insulating substrate, at least two electrically conductive columns, and a coil main body layer. The coil leading layer is disposed on a first surface of the substrate, and includes at least two leading wires, at least four leading terminals, and at least two contacts. Each leading wire respectively connects one leading terminal and one contact. The coil main body layer is disposed on a second surface of the substrate, and includes a coil lead and two end portions thereof. Each electrically conductive column extends through the substrate, connecting one contact and one end portion. The two substrates and two coil main body layers of the at least two inductance unit sets are bonded by an electrically insulating layer. The two coil main body layers are electrically isolated from each other by the electrically insulating layer. | 05-17-2012 |
| 20120100711 | SINGLE CHIP SEMICONDUCTOR COATING STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a single chip semiconductor coating structure includes following steps. Step | 04-26-2012 |
| 20110316658 | THIN TYPE COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - A thin type common mode filter includes an insulating flexible substrate, a first magnetic material layer, a first coil leading layer, a coil main body multi-layer, a second coil leading layer, and a second magnetic material layer. The first coil leading layer is formed on a first surface of the flexible substrate, and the first coil leading layer is formed on a second surface of the flexible substrate opposite to the first surface. The coil main body multi-layer, the second coil leading layer, and the second magnetic material layer are sequentially stacked on the first coil leading layer. | 12-29-2011 |
| 20110204521 | CHIP-SCALE SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A chip-scale semiconductor device package includes a die, an insulating substrate having a through hole, a first metal layer, a second metal layer, and an insulating layer. The first metal layer is on a first surface of the insulating substrate and a first side of the through hole. The insulating layer is overlaid on a second surface of the insulating substrate and surrounds a second side of the through hole. The second metal is on the insulating layer and the second side of the through hole. The die is in the through hole and includes a first electrode and a second electrode. The first electrode is electrically connected to the first metal layer, and the second electrode is electrically connected to the second metal layer. | 08-25-2011 |
| 20110025442 | COMMON MODE FILTER AND METHOD FOR MANUFACTURING THE SAME - A common mode filter comprises an insulating substrate, a lower coil leading layer, a coil main body multilayer, and an upper coil leading layer. The upper coil leading layer comprises at least one upper lead, at least one upper terminal, and at least one upper contact, and the lower coil leading layer comprises at least one lower lead, at least one lower terminal, and at least one lower contact. The two ends of the upper lead are respectively connected to the upper terminal and the upper contact, and the upper lead surrounds the upper contact. The two ends of the lower lead are respectively connected to the lower terminal and the lower contact, and the lower lead surrounds the lower contact. The upper coil leading layer and the lower coil leading layer sandwich the coil main body multi-layer, and the lower coil leading layer is disposed on the insulating substrate. | 02-03-2011 |
| 20100309087 | Chip antenna device - A chip antenna device includes a single or multi-layer dielectric substrate, a radiator body, one or a plurality of first coupling electrodes formed on the radiator body, and a ground radiator formed on the upper or lower surface or inter-layer in another end of the substrate. It is designed by using loops and coupling concepts. The chip antenna device does not require large areas and clear space but has high radiation efficiency. It adjusts the impedance matching and operation frequency by changing the signal feed position, so that low frequency operation can be achieved without increasing the area of said antenna meeting the requirements of compact size for electronic products. | 12-09-2010 |
| 20100182121 | OVER-CURRENT PROTECTION DEVICE AND MANUFACTURING METHOD THEREOF - An over-current protection device comprises a PTC material layer, a first electrode layer, a second electrode layer, a first side electrode and a second side electrode. The PTC material layer is sandwiched between the first electrode layer and the second electrode layer. The first side electrode and the second side electrode are respectively disposed on two opposite side surfaces of the PTC material layer, and are respectively connected to the first electrode layer and the second electrode layer. Furthermore, the first side electrode and the second side electrode are respectively extended to four surfaces adjacent and perpendicular to the two side surfaces. | 07-22-2010 |
| 20100164809 | CIRCULAR POLARIZATION ANTENNA STRUCTURE WITH A DUAL-LAYER CERAMIC AND METHOD FOR MANUFACTURING THE SAME - A circular polarization antenna structure with a dual-layer ceramic includes a first hard dielectric body, a first metal layer, a grounding layer, an antenna feed pin, a second hard dielectric body, a second metal layer and an adhesive element. The first metal layer and the grounding layer dispose on a top surface and a bottom surface of the first hard dielectric body. The antenna feed pin passes through the through hole of the first hard dielectric body, the top side of the antenna feed pin is fixed on the top surface of the first hard dielectric body, and the bottom side of the antenna feed pin extends outwards from the bottom surface of the first hard dielectric body. The second hard dielectric body disposes above the top side of the first hard dielectric body. The second metal layer disposes on the top surface of the second hard dielectric body. | 07-01-2010 |
| 20100078798 | INSULATION COVERING STRUCTURE FOR A SEMICONDUCTOR ELEMENT WITH A SINGLE DIE DIMENSION AND A MANUFACTURING METHOD THEREOF - An insulation covering structure for a semiconductor element with a single die dimension includes: a semiconductor element with a single die dimension and an insulation covering layer. The semiconductor element has a front side surface, a rear side surface, a left side surface, a right side surface, a bottom surface, and a top surface. The top surface of the semiconductor element has two metal pads. The insulation covering layer covers the front side surface, the rear side surface, the left side surface, the right side surface, and the bottom surface of the semiconductor element. A manufacturing process for covering the semiconductor element with a single die dimension is also disclosed. | 04-01-2010 |
| 20090296294 | ELECTRO-STATIC DISCHARGE PROTECTION DEVICE WITH LOW TEMPERATURE CO-FIRE CERAMIC AND MANUFACTURING METHOD THEREOF - The present invention relates to an electro-static discharge (ESD) protection device with a low temperature co-fire ceramic (LTCC) and a manufacturing method thereof. The ESD protection device comprises a low temperature co-fire ceramic film having a first patterned conductive electrode material layer and a second patterned conductive electrode material layer therein. The low temperature co-fire ceramic film has at least one via exposing a portion of the first patterned conductive electrode material layer and a portion of the second patterned conductive electrode material layer simultaneously. | 12-03-2009 |
| 20090128281 | COMPOSITE CHIP VARISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A composite chip varistor device includes a body; at least one inner varistor, disposed in the body; and a plurality of end electrodes, disposed at two sides of the inner varistor. The body is a highly insulative and imporous mono-material. The body of the present invention provides protection for the inner varistor to avoid being damaged by external factors and the manufacturing cost of the varistor device is effectively reduced. | 05-21-2009 |
| 20090002911 | OVER VOLTAGE PROTECTION DEVICE WITH AN AIR-GAP - The present invention relates to an over voltage protection device with an air gap and a manufacturing method thereof. The over voltage protection device provides over voltage protection by using an air gap extending into a first substrate and a second substrate. The air gap is formed by a first trench of the first substrate and a second trench of the second substrate. | 01-01-2009 |
| 20090002910 | OVER VOLTAGE PROTECTION DEVICE WITH AN AIR-GAP - The present invention relates to an over voltage protection device with an air gap and a manufacturing method thereof. The over voltage protection device provides over voltage protection by using an air gap extending into a first substrate and a second substrate. The air gap is formed by a first trench of the first substrate and a second trench of the second substrate. | 01-01-2009 |
| 20090002906 | OVER VOLTAGE PROTECTION DEVICE WITH AN AIR-GAP - The present invention relates to an over voltage protection device with an air gap and a manufacturing method thereof. The over voltage protection device provides over voltage protection by using an air gap extending into a first substrate and a second substrate. The air gap is formed by a first trench of the first substrate and a second trench of the second substrate. | 01-01-2009 |
| 20080239600 | LOW TRIGGER VOLTAGE ESD PROTECTION DEVICE - The present invention is an electrostatic discharge protection device having a low trigger voltage. The device can utilize a process of manufacturing a PCB to minimize costs and manufacturing time. The device comprises: a discharge area, which is essentially a space within the device and can be filled by a material having a desired breakdown voltage, and at least two electrode areas, wherein the two electrode areas are substantially electrically isolated from each other and simultaneously adjacent to or within the discharge area. When an electric potential difference between the electrode areas exceeds a predetermined value, a conductive path between the electrode areas will be created by discharging through the discharge area. The device is characterized in that each of the two electrodes is a part of a conductive plate, and the two conductive plates become a part of the device by pressing or adhering so that a gap for electric isolation exists between the two electrode areas. | 10-02-2008 |
