INNOVASIC, INC. Patent applications |
Patent application number | Title | Published |
20160087917 | ETHERNET INTERFACE MODULE - An Ethernet interface module comprises a first full duplex port, a second duplex port, a first path coupling the first duplex port and the second full duplex port, a second path coupling the second full duplex port and the first full duplex port, a first queue disposed in the first path, a second queue disposed in the second path, a third path comprising at least a portion of the first queue coupling the receive and transmit portions of the first port, a fourth path comprising at least a portion of the second queue coupling the receive and transmit portions of the second port, execution apparatus operable responsive to a command to alter the state of said Ethernet interface module, or the contents of said received frame to produce a return frame comprising fields of a received frame that are modified, or both. | 03-24-2016 |
20160087675 | ETHERNET INTERFACE MODULE - An Ethernet interface module comprises a duplex port operable to transfer frames between said Ethernet network and a device and a path coupling a receive portion of the duplex port to a transmit portion of said first full duplex port. A queue is disposed in said first path. Evaluation apparatus is coupled to the queue and determines whether a received frame is addressed to said Ethernet interface module and whether a frame type field contains a frame type. The Ethernet interface module is operable in a first mode such that every said received frame is echoed back out the full duplex port; and is operable in a second mode such that each received frame that meets predetermined evaluation criteria is echoed back out the duplex port and those received frames that do not meet the predetermined evaluation criteria are discarded. | 03-24-2016 |
20160072929 | PROCESSING APPARATUS FOR BUS DATA - A communication controller apparatus couples a device comprising a device processor to a data bus. The communication controller comprises an input/output controller coupled to the bus to receive a plurality of types of data packets. The types of data packets comprise at least one type of data packets having a high priority determined by timing criticality. The input/output controller is operable to process data packets received via the bus before providing any of the received data packets to the device processor. The communication controller comprises a high priority data path comprising a high priority data packet queue a low priority data path to the device comprising a low priority data packet queue. | 03-10-2016 |
20160028655 | ETHERNET INTERFACE MODULE - An Ethernet interface comprises a first full duplex port and a second duplex port each operable to transfer frames between a network and a device. The Ethernet interface module further comprises a first path coupling the first duplex port and the second full duplex port; a second path coupling the second full duplex port and the first full duplex port; a first queue disposed in the first path; a second queue disposed in the second path; and evaluation apparatus coupled to the first queue and to the second queue. | 01-28-2016 |
20150089080 | METHOD OF PROCESSING BUS DATA - A method is provided for operating a communication controller coupling a device comprising a processor with a bus. The method comprises: receiving a plurality of types of data packets via the bus and processing received data packets before making available said received data packets to the device processor. The processing of received data packets comprises: evaluating each received data packet in accordance with predetermined criteria; rejecting any of the received data packets that fails to meet the predetermined criteria; identifying non-rejected data packets having high priority; identifying said non-rejected other data packets having lower priority; providing a high priority data path to the processor for the high priority data packets; providing at least one additional data path to the processor for the other data packets; and providing a high priority alert to the device processor to the presence of high priority data packets at the high priority channel. | 03-26-2015 |