INFINEON TECHNOLOGIES DRESDEN GMBH Patent applications |
Patent application number | Title | Published |
20150357446 | BIPOLAR TRANSISTOR STRUCTURE AND A METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR STRUCTURE - According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon. | 12-10-2015 |
20150323381 | ARRANGEMENT AND METHOD FOR DETERMINING THE SPATIAL DIRECTION OF RADIATION INCIDENCE - The present disclosure relates to an optical receiver. The optical receiver has a first photosensor and a second photosensor disposed within a substrate. The first photosensor has a first angled surface located on a first side of a depression within the substrate, and the second photosensor has a second angled surface located on a second side of the depression, opposite the first side of the depression. A plurality of blocking structures are disposed over the substrate. The plurality of blocking structures block radiation that is not incident on the first and second angled surfaces. By receiving incident radiation on the first and second angled surfaces, the first and second photosensors are able to generate directional-dependent photocurrents that vary depending upon an angle of incident radiation. Based upon the directional-dependent photocurrents, an angle of incident radiation can be determined. | 11-12-2015 |
20150318166 | WAFER, A METHOD FOR PROCESSING A WAFER, AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a method for processing a wafer may include: forming at least one hollow chamber and a support structure within the wafer, the at least one hollow chamber defining a cap region of the carrier located above the at least one hollow chamber and a bottom region of the carrier located below the at least one hollow chamber and an edge region surrounding the cap region of the carrier, wherein a surface area of the cap region is greater than a surface area of the edge region, and wherein the cap region is connected to the bottom region by the support structure; removing the cap region in one piece from the bottom region and the edge region. | 11-05-2015 |
20150225230 | SUPPORT FOR MEMS COVER - Embodiments related to a MEMS device in which a support structure for supporting a cover is formed in a cavity are described and depicted. | 08-13-2015 |
20150163915 | ELECTRONIC DEVICE, A METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE, AND A METHOD FOR OPERATING AN ELECTRONIC DEVICE - According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to each other; an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure; a first electronic component arranged in the first region of the carrier over the electrically insulating structure; a second electronic component arranged in the second region of the carrier; wherein the electrically insulating structure includes one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material. | 06-11-2015 |
20150162385 | OPTOELECTRONIC COMPONENT AND A METHOD FOR MANUFACTURING AN OPTOELECTRONIC COMPONENT - Various embodiments relate to an optoelectronic component including: an electronic circuit structure including an electronic circuit and a metallization structure disposed over the electronic circuit, the metallization structure including one or more contact pads electrically connected to the electronic circuit; and an optoelectronic structure disposed over the metallization structure, the optoelectronic structure including at least one electrode structure being in direct contact with the one or more contact pads, wherein the electrode structure includes an electroless plated electrically conductive material. | 06-11-2015 |
20150162254 | CARRIER AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a carrier may include: a hollow chamber spaced apart from a surface of the carrier; and at least one support structure within the hollow chamber connecting a first region of the carrier disposed over the hollow chamber with a second region of the carrier disposed below the hollow chamber, wherein at least a part of a surface of the at least one support structure is spaced apart from an inner surface of the hollow chamber, and wherein the at least one support structure includes an electrically insulating material. | 06-11-2015 |
20150162253 | CARRIER AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure including one or more trenches extending from the surface of the carrier to the hollow chamber, and one or more support structures intersecting the one or more trenches and connecting the first region of the carrier with a second region of the carrier outside the trench structure, wherein the one or more support structures including an electrically insulating material. | 06-11-2015 |
20150147839 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device may include: forming a metal layer structure over a semiconductor workpiece; forming a first layer over the metal layer structure, the first layer including a first material; forming at least one opening in the first layer and the metal layer structure; depositing a second layer to fill the at least one opening and at least partially cover a surface of the first layer facing away from the metal layer structure, the second layer including a second material that is different from the first material; removing the second layer from at least the surface of the first layer facing away from the metal layer structure; and removing the first layer. | 05-28-2015 |
20150115444 | WAFER ARRANGEMENT, A METHOD FOR TESTING A WAFER, AND A METHOD FOR PROCESSING A WAFER - According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component. | 04-30-2015 |
20150115226 | OPTOELECTRONIC COMPONENT, A METHOD FOR MANUFACTURING AN OPTOELECTRONIC COMPONENT, AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, an optoelectronic component may be provided, the optoelectronic component including: an electrode structure disposed at least one of over and in a carrier; and a grating structure disposed over the electrode structure, the grating structure including at least a first region and a second region, wherein the first region of the grating structure includes amorphous silicon; and wherein the second region of the grating structure includes a material having a refractive index different from the refractive index of the amorphous silicon. | 04-30-2015 |
20150079787 | METHOD AND STRUCTURE FOR CREATING CAVITIES WITH EXTREME ASPECT RATIOS - Embodiments relate to structures, systems and methods for more efficiently and effectively etching sacrificial and other layers in substrates and other structures. In embodiments, a substrate in which a sacrificial layer is to be removed to, e.g., form a cavity comprises an etch dispersion system comprising a trench, channel or other structure in which etch gas or another suitable gas, fluid or substance can flow to penetrate the substrate and remove the sacrificial layer. The trench, channel or other structure can be implemented along with openings or other apertures formed in the substrate, such as proximate one or more edges of the substrate, to even more quickly disperse etch gas or some other substance within the substrate. | 03-19-2015 |
20140353852 | METHOD FOR PROCESSING A CARRIER AND A CARRIER - A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure. | 12-04-2014 |
20140332759 | ELECTRODE, AN ELECTRONIC DEVICE, AND A METHOD FOR MANUFACTURING AN OPTOELECTRONIC DEVICE - According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium. | 11-13-2014 |
20140273445 | METHOD FOR PROCESSING A CARRIER - A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed. | 09-18-2014 |
20140266484 | MICROELECTROMECHANICAL RESONATORS - Embodiments relate to MEMS resonator structures and methods that enable application of a maximum available on-chip voltage. In an embodiment, a MEMS resonator comprises a connection between a ground potential and the gap electrode of the resonator. Embodiments also relate to manufacturing systems and methods that are less complex and enable production of MEMS resonators of reduced dimensions. | 09-18-2014 |
20140213049 | METHOD FOR PROCESSING A CARRIER, METHOD FOR FABRICATING A CHARGE STORAGE MEMORY CELL, METHOD FOR PROCESSING A CHIP, AND METHOD FOR ELECTRICALLY CONTACTING A SPACER STRUCTURE - A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material. | 07-31-2014 |
20140175571 | METHOD FOR MANUFACTURING A MICROMECHANICAL SYSTEM COMPRISING A REMOVAL OF SACRIFICIAL MATERIAL THROUGH A HOLE IN A MARGIN REGION - A method for manufacturing a micromechanical system includes creating a sacrificial layer at a substrate surface. A structural material is deposited at a sacrificial layer surface and at a support structure for later supporting the structural material. At least one hole is created in the structural material extending from an exposed surface of the structural material to the surface of the sacrificial layer. The at least one hole leads to a margin region of the sacrificial layer. The sacrificial layer is removed using a removal process through the at least one hole, to obtain a cavity between the surface of the substrate and the structural material. The method also includes filling the at least one hole and a portion of the cavity beneath the at least one hole close to the cavity. A corresponding micromechanical system and a microelectromechanical transducer are also described. | 06-26-2014 |
20140145319 | Semicondutor Packages and Methods of Fabrication Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad. | 05-29-2014 |
20140134844 | METHOD FOR PROCESSING A DIE - In various embodiments, a method for processing a die is provided. The method may include forming a periodic structure at least one of over and in a carrier, the periodic structure including a plurality of structure elements; depositing masking material over the periodic structure; partially removing masking material to expose at least one structure element but not all of the structure elements; and removing the exposed at least one structure element. | 05-15-2014 |
20140112067 | Apparatus, Storage Device, Switch and Methods, Which Include Microstructures Extending from a Support - An apparatus has a support and a plurality of bendable and conductive microstructures extending from the support. Two adjacent microstructures of the plurality of microstructures define a detectable first state if they are not bent such that end portions thereof, which are distal with respect to the support, do not touch each other, and the two adjacent microstructures of the plurality of microstructures define a detectable second state if they are bent such that the end portions thereof, which are distal with respect to the support, touch each other and are fixed to each other. | 04-24-2014 |
20140110805 | SILICON LIGHT TRAP DEVICES, SYSTEMS AND METHODS - Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art. | 04-24-2014 |
20140097521 | Silicon on Nothing Devices and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate. | 04-10-2014 |
20140062585 | Circuit Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices. | 03-06-2014 |
20140027848 | Lateral Semiconductor Device and Manufacturing Method Therefor - A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension. | 01-30-2014 |
20140016386 | Circuit Arrangement with a Rectifier Circuit - A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. | 01-16-2014 |
20140015592 | INTEGRATED CIRCUIT WITH AT LEAST TWO SWITCHES - A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. | 01-16-2014 |
20130264654 | Integrated Switching Device with Parallel Rectifier Element - An integrated circuit includes a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body. The integrated circuit further includes a switching device with a control terminal and a load path between a first load terminal and a second load terminal, and a rectifier element connected in parallel with at least one section of the load path. The switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer. | 10-10-2013 |
20130193512 | Semiconductor Arrangement with Active Drift Zone - A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure. | 08-01-2013 |