| INFINEON TECHNOLOGIES AG Patent applications |
| Patent application number | Title | Published |
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| 20120126805 | Current Sensor - Embodiments of the invention provide a current sensor including a conductive element and at least two magnetic field sensors. The conductive element includes at least three terminal areas and a common conductive area, wherein each of the at least three terminal areas is connected to the common conductive area to guide a current applied to the respective terminal area into the common conductive area. The at least two magnetic field sensors are arranged at different geometric positions adjacent to the common conductive area, wherein each of the at least two magnetic field sensors is configured to sense a magnetic field component of each current flowing into the common conductive area to provide a sensor signal based on the sensed magnetic field component. | 05-24-2012 |
| 20120126783 | SELF TIMED CURRENT INTEGRATING SCHEME EMPLOYING LEVEL AND SLOPE DETECTION - Some embodiments of the invention relate to a sense amplifier configured to determine the slope of a bitline charging voltage and to utilize the determined slope in combination with a voltage level sensing scheme to aid in reading data from a memory cell associated with the bitline. In particular, a sense amplifier circuit is configured to determine a slope of a bit line charging voltage and based upon the determined slope to adjust the slope of the bitline voltage (e.g., by adding a dynamic slope dependent current to a memory cell current configured to charge the bitline) provided to a sense amplifier. By adjusting the slope of the bitline voltage, the charging speed of memory cells in a low resistive state (e.g., having a high cell current and therefore a good SNR) can be increased. | 05-24-2012 |
| 20120126344 | SENSOR DEVICE AND METHOD - A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element. | 05-24-2012 |
| 20120126343 | Self Aligned Silicided Contacts - Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material. | 05-24-2012 |
| 20120126318 | Integrated Circuit Including Field Effect Transistor - An integrated circuit includes a semiconductor carrier including a first side and a second side opposite the first side. An FET is in a first area of the semiconductor carrier, and has a drain electrically coupled to a drain contact area at the first side and a source electrically coupled to a source contact area at the second side. First circuit elements are in a second area of the semiconductor carrier. The second area is electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending through the semiconductor carrier from the first side to the second side. An interconnection level electrically interconnects the first circuit elements at the second side, and is electrically insulated from the source contact area in the entire second area via an insulating layer at the second side. A conductive pathway extends through the semiconductor carrier from the first side to the second side, and is electrically insulated from the semiconductor carrier surrounding the conductive pathway. At least one of the first circuit elements is electrically coupled to a contact area at the first side via the conductive pathway. | 05-24-2012 |
| 20120126305 | Strained Semiconductor Device and Method of Making Same - In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress. | 05-24-2012 |
| 20120122448 | METHOD AND DEVICE FOR CONFIGURATION OF A MOBILE COMMUNICATION SYSTEM - A method for configuration of a mobile communication system with a mobile communication network and a mobile terminal, which comprises determining a communication service quality required by a software application running on the mobile terminal for the transmission of data to be transmitted via a communication connection between the mobile communication network and the mobile terminal; and determining at least one of a base station of the mobile communication network to provide the communication connection and a radio frequency region to be used to provide the communication connection based on the required communication service quality. | 05-17-2012 |
| 20120119721 | CIRCUIT ARRANGEMENT INCLUDING VOLTAGE SUPPLY CIRCUIT - A circuit arrangement comprising a first semiconductor switching element, which has a load path and a drive terminal. A voltage supply circuit, is provided including an inductance connected in series with the load path of the first semiconductor switching element, and a capacitive charge storage arrangement, which is connected in parallel with the inductance and which has a first and a second output terminal for providing a supply voltage. | 05-17-2012 |
| 20120119297 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin. | 05-17-2012 |
| 20120117448 | Apparatus and Method for Correcting at least one Bit Error within a Coded Bit Sequence - An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence. | 05-10-2012 |
| 20120117283 | ARRANGEMENT COMPRISING A FIRST SEMICONDUCTOR CHIP AND A SECOND SEMICONDUCTOR CHIP CONNECTED THERETO - A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip. | 05-10-2012 |
| 20120114016 | Method for Processing Data - A method includes encoding data according to a space time transmit diversity scheme and spatial-multiplexing the encoded data. | 05-10-2012 |
| 20120112775 | Detection of the Conduction State of an RC-IGBT - A circuit arrangement includes: a reverse conducting IGBT configured to allow for conducting a load current in a forward direction and in a reverse direction, the IGBT having a load current path and a gate electrode; a gate control unit connected to the gate electrode and configured to activate or deactivate the IGBT by charging or, respectively, discharging the gate electrode in accordance with a gate control signal; a gate driver unit configured to detect whether the IGBT conducts current in the forward direction or the reverse direction by sensing a gate current caused by a change of a voltage drop across the load path due to a changing of the reverse conducting IGBT into its reverse conducting state, the gate control unit further configured to deactivate the IGBT or to prevent an activation of the IGBT via its gate electrode when the gate driver unit detects that the IGBT is in its reverse conducting state. | 05-10-2012 |
| 20120112365 | Semiconductor Packages and Methods For Producing The Same - In one embodiment, a semiconductor package includes an isolating container having a recess, which forms an inner membrane portion and an outer rim portion. The rim portion is thicker than the membrane portion. The package includes a semiconductor chip disposed in the recess and a backplane disposed under the membrane portion of the isolating container. | 05-10-2012 |
| 20120110374 | Methods and Systems for Measuring I/O Signals - Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal. | 05-03-2012 |
| 20120106086 | SEMICONDUCTOR MODULE HAVING AN INSERT AND METHOD FOR PRODUCING A SEMICONDUCTOR MODULE HAVING AN INSERT - A power semiconductor module includes a module housing with a sealing ring on its top side. The sealing ring, in co-operation with the module housing and a printed circuit board attached to the power semiconductor module, hermetically seals feed-through locations at the top side of the module housing for feeding through electric terminals of the power semiconductor module. On the bottom side of the module housing a sealing ring hermetically seals the bottom side of the module housing. | 05-03-2012 |
| 20120105173 | MEMS Device - System and method for a microelectromechanical system (MEMS) is disclosed. A preferred embodiment comprises a first anchor region, a vibrating MEMS structure fixed to the first anchor region, a first electrode adjacent the vibrating MEMS structure, a second electrode adjacent the vibrating MEMS structure wherein the vibrating MEMS structure is arranged between the first and the second electrode. | 05-03-2012 |
| 20120104592 | SEMICONDUCTOR MODULE HAVING A SEMICONDUCTOR CHIP STACK AND METHOD - A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film. | 05-03-2012 |
| 20120104582 | High Power Ceramic on Copper Package - According to an embodiment of a high power package, the package includes a heat sink containing enough copper to have a thermal conductivity of at least 350 W/mK, an electrically insulating attached to the heat sink with an epoxy and a semiconductor chip attached to the heat sink on the same side as the lead frame with an electrically conductive material having a melting point of 280° C. or greater. | 05-03-2012 |
| 20120104574 | INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE - A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package. | 05-03-2012 |
| 20120104537 | Semiconductor Device and a Method for Manufacturing a Semiconductor Device - A semiconductor device and a method for forming a semiconductor device are provided. The semiconductor device includes a semiconductor body with a first semiconductor region and a second semiconductor region spaced apart from each other. A first metallization is in contact with the first semiconductor region. A second metallization is in contact with the second semiconductor region. An insulating region extends between the first semiconductor region and the second semiconductor region. A semi-insulating region having a resistivity of about 10 | 05-03-2012 |
| 20120100689 | MIM CAPACITOR AND ASSOCIATED PRODUCTION METHOD - An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top. | 04-26-2012 |
| 20120099359 | Nonvolatile Memory Architecture - Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array. | 04-26-2012 |
| 20120099243 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via. | 04-26-2012 |
| 20120093312 | Data Transmitter with a Secure and Efficient Signature - An encryption device encrypts a first block of user data to obtain a first encryption result and encrypts a second block of user data, which follows the first block of user data, to obtain a second encryption result. The encryption device uses the first encryption result for encrypting the second block of user data. An extractor extracts a first portion of the first encryption result, the first portion being smaller than the first encryption result, and a second portion of the second encryption result, the second portion being smaller than the second encryption result. A message formatter combines the first block of user data and the first portion as a signature for the first block to produce a first transmission packet, and combines the second block of user data and the second portion as a signature for the second block to produce a second transmission packet. | 04-19-2012 |
| 20120091568 | MIXED WIRE SEMICONDUCTOR LEAD FRAME PACKAGE - One embodiment includes an encapsulated semiconductor package having a lead frame with die pad surrounded by a plurality of first and second leadfingers. A semiconductor chip including chip contact pads on its upper active surface is attached to the die pad. A plurality of first bond wires, incoluding a first electrically conductive material, extend between the chip contact pads and the plurality of first leadfingers. A plurality of second bond wires, including a second electrically conductive material, extend between a chip contact pad and a second leadfinger. The semiconductor package further includes a plurality of electrically conducting means attached to the second leadfingers. | 04-19-2012 |
| 20120089810 | Apparatus and Method for Formatting and Preselecting Trace Data - The invention relates to a method and apparatus for formatting and preselecting trace data, and includes a trace message generator, an address checker, and a memory connected to the trace message generator and address checker. The trace message generator is configured to receive an address and associated data and generate a trace message with the associated data for the received address. The address checker is configured to receive the address, check the received address with the aid of the memory, and generate an output signal that indicates whether or not the trace message generated for the address is intended to be stored. The memory is configured to receive the trace message generated by the trace message generator, receive the output signal generated by the address checker, and store the received trace message if the output signal indicates that the trace message is intended to be stored. | 04-12-2012 |
| 20120087361 | DATA FLOW CONTROL IN WLAN RADIO CONNECTIONS FOR THE IMPAIRMENT OF INTERNET TELEPHONY - In a method for controlling the data flow on a radio link between a WLAN base station and a WLAN mobile station, the data rate on the radio link is reduced for in each case one time period ( | 04-12-2012 |
| 20120087191 | Symmetric, Differential Nonvolatile Memory Cell - Some embodiments relate to a differential memory cell. The memory cell includes a first transistor having a source, a drain, a gate, and a body. A first capacitor has a first plate and a second plate, wherein the first plate is coupled to the gate of the first transistor and extends over the body region. The memory cell also includes a second transistor having a source, a drain, a gate, and a body, wherein the source and body of the second transistor is coupled to the second plate of the first capacitor. A second capacitor has a third plate and a fourth plate, wherein the third plate is coupled to the gate of the second transistor and the fourth plate is coupled to the source and the body of the first transistor. | 04-12-2012 |
| 20120084512 | FAST UNALIGNED CACHE ACCESS SYSTEM AND METHOD - A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations. | 04-05-2012 |
| 20120083236 | Multimode Receiver with Active Blocker Suppression - Various embodiments of a wireless multimode receiver having an off-chip duplex filter associated with a multimode band, and a blocker cancellation circuit disposed on a semiconductor chip are described in the present disclosure. | 04-05-2012 |
| 20120083108 | Transistor Level Routing - A system and a method for transistor level routing are disclosed. The method comprises forming a high-k dielectric layer over a substrate, forming a metal layer directly over the high-k dielectric layer, and selectively disposing a semiconductive layer over the metal layer. The method further comprises forming a first transistor in a first region and a second transistor in a second region spaced from the first region, the first and second transistor having gate stacks comprising a high-k dielectric layer, a metal layer and a semiconductive layer, and forming an electrical connection between the first transistor and the second transistor comprising the high-k dielectric layer and the metal layer but not the semiconductive layer. | 04-05-2012 |
| 20120083098 | Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core - According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate. | 04-05-2012 |
| 20120082099 | RADIO BASE STATIONS, MOBILE RADIO TERMINALS, METHODS FOR CONTROLLING A RADIO BASE STATION, AND METHODS FOR CONTROLLING A MOBILE RADIO TERMINAL - In an embodiment, a radio base station is provided. The radio base station may include: a receiver configured to receive, via a pre-determined radio resource, a Random Access Preamble from a mobile radio terminal; a load determiner configured to determine whether a load situation which fulfills a pre-determined criterion is present for at least one communication resource of the radio base station; a Random Access Response message generator configured to generate, based on the determination of the load determiner, a Random Access Response message including controlling information for controlling access to the pre-determined radio resource and recipient information indicating whether a recipient of the Random Access Response message is to apply the controlling information; and a sender configured to send the Random Access Response message in response to the received Random Access Preamble to the mobile radio terminal. | 04-05-2012 |
| 20120081166 | Level Shifter Circuits and Methods - Some embodiments of the present disclosure relate to a level shifter that provides improved response time and/or low static power dissipation compared to conventional level shifters. In some embodiments, a level shifter circuit includes an input terminal coupled to a first semiconductor device, and an output terminal coupled to a second semiconductor device. The first semiconductor device is designed to operate over a first voltage range associated with an input signal, and the second semiconductor device is designed to operate over a second, different voltage range associated with an latched output signal. To transform the input voltage range to the output voltage range, the level shifter circuit includes a signal analyzer and an output latch, wherein the signal analyzer includes at least one state change element for setting a voltage level of the latched output signal. | 04-05-2012 |
| 20120081109 | Hall sensor arrangement for the redundant measurement of a magnetic field - In various embodiments, a Hall sensor arrangement for the redundant measurement of a magnetic field may include a first Hall sensor on a top side of a first semiconductor substrate; a second Hall sensor on a top side of a second semiconductor substrate; a carrier having a top side and an underside; wherein the first Hall sensor is arranged on the top side of the carrier and the second Hall sensor is arranged on the underside of the carrier; and wherein the measuring area of the first Hall sensor projected perpendicularly onto the carrier at least partly overlaps the measuring area of the second Hall sensor projected perpendicularly onto the carrier. | 04-05-2012 |
| 20120080799 | Semiconductor Module Comprising an Insert and Method for Producing a Semiconductor Module Comprising an Insert - A power semiconductor module is fabricated by providing a base with a metal surface and an insulating substrate comprising an insulation carrier having a bottom side provided with a bottom metallization layer. An insert exhibiting a wavy structure is provided. The insert is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom side metallization layer and insert by means of a solder packing all interstices between the metal surface and bottom side metallization layer with the solder. | 04-05-2012 |
| 20120079343 | APPARATUS AND METHOD FOR DETERMINATION OF A POSITION OF A 1 BIT ERROR IN A CODED BIT SEQUENCE, APPARATUS AND METHOD FOR CORRECTION OF A 1-BIT ERROR IN A CODED BIT SEQUENCE AND DECODER AND METHOD FOR DECODING AN INCORRECT, CODED BIT SEQUENCE - An apparatus for determination of a position of a 1-bit error includes an error position determiner of the inner code, an error syndrome determiner of the outer code, a derivative determiner and an overall error position determiner. The error position determiner of the inner code determines at least one possible error position of a bit error in the coded bit sequence on the basis of the inner code. The error syndrome determiner of the outer code determines a value of a non-linear syndrome bit of the outer code on the basis of a non-linear function of bits in the coded bit sequence. Furthermore, the derivative determiner determines a value of a derivative bit for at least one determined, possible error position of the bit error on the basis of derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence. | 03-29-2012 |
| 20120077452 | IP2 CALIBRATION METHODS AND TECHNIQUES - Some embodiments of the present disclosure relate to improved techniques for performing IP2 calibration in receivers having two complementary data paths (e.g., i-data path and q-data path). In these techniques, one of the two data paths (e.g., the i-data path) is used to generate a reference signal for the other data path (e.g., the q-data path), and/or vice versa. The other data path then performs calibration using the reference signal. Compared to previous techniques (which required separate, dedicated circuitry for generating a reference signal), the inventive techniques reduce the amount of circuitry and correspondingly reduce the manufacturing costs and power consumption. This is because the inventive techniques use the existing circuitry in complementary fashion during calibration (e.g., during calibration an i-data path generates a reference signal for a q-data path, and vice versa). | 03-29-2012 |
| 20120075812 | MULTI-CHIP PACKAGE - In various embodiments, a chip module may include a substrate; electronic components, the electronic components being arranged on a first side of the substrate; and an insulating layer, which is applied to the first side of the substrate and to the electronic components, contact openings being arranged in the insulating layer which permit electrical contacting of the electronic components; and an electrically conducting layer being arranged on the insulating layer and in the contact openings, which connects the electronic components electrically to one another. | 03-29-2012 |
| 20120074947 | Failure Detection for Series of Electrical Loads - A device can be used for detecting failures in an illumination device having a plurality of light emitting diodes connected in series. A first circuit node, a second circuit node, and a third circuit node interface the illumination device such that a voltage supplying the plurality of light emitting diodes is applied between the first and the second circuit node and a first fraction of the supply voltage drop is provided between the third and the second circuit node. An evaluation unit is coupled to the first circuit node, the second circuit node, and the third circuit node and configured to assess whether a voltage present at the third circuit node is within a pre-defined range of tolerance about a nominal value that is defined as a second fraction of the supply voltage present between the first and the second circuit node. | 03-29-2012 |
| 20120074598 | CHIP, METHOD FOR PRODUCING A CHIP AND DEVICE FOR LASER ABLATION - In various embodiments, a chip may include a substrate; a coating, the coating covering the substrate at least partially and the coating being designed for being stripped at least partially by means of laser ablation; wherein between the substrate and the coating, a laser detector layer is arranged at least partially, the laser detector layer being designed for generating a detector signal for ending the laser ablation. | 03-29-2012 |
| 20120074570 | Method for Forming a Through Via in a Semiconductor Element and Semiconductor Element Comprising the Same - A method for forming a through via in a semiconductor element includes providing a semiconductor element having electronic circuitry integrated on the main side thereof. The semiconductor element further includes an etch stop layer and a conductive region, wherein the conductive region is arranged between the etch stop layer and the main side of the semiconductor element. The method also includes selectively etching a through via from a backside of the semiconductor element, opposite to the main side of the semiconductor element, to the etch stop layer and removing at least partly the etch stop layer, so that the conductive region is exposed to the backside and filling at least partly the through via with a conductive material, wherein the conductive material is electrically isolated from the semiconductor element. | 03-29-2012 |
| 20120074536 | Methods of Manufacturing Semiconductor Devices and Structures Thereof - Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern. | 03-29-2012 |
| 20120074499 | Integrated Circuits and Methods of Design and Manufacture Thereof - Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives. | 03-29-2012 |
| 20120074405 | Process for the Simultaneous Deposition of Crystalline and Amorphous Layers with Doping - One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics. | 03-29-2012 |
| 20120074228 | TRANSPONDER INLAY FOR A DOCUMENT FOR PERSONAL IDENTIFICATION, AND A METHOD FOR PRODUCING A TRANSPONDER INLAY - In various embodiments, a transponder inlay for a document for personal identification may include a cover; an adhesive layer arranged on the cover; a chip arranged on the adhesive layer; an antenna connected to the chip; and a top layer on the adhesive layer, wherein the top layer has a top and a bottom and wherein the bottom of the top layer is connected to the cover by means of the adhesive layer and wherein the antenna is arranged on the top of the top layer such that the antenna is at least to some extent physically separated from the adhesive layer by the top layer. | 03-29-2012 |
| 20120073372 | MICROELECTROMECHANICAL SYSTEM - In various embodiments, a microelectromechanical system may include a chip, a substrate, a signal generator, and a fixing structure configured to fix the chip to the substrate. The chip may be fixed in such a way that, upon an acceleration of the microelectromechanical system, the chip is moved relative to the substrate. Furthermore, a signal may be generated by the movement of the chip by means of the signal generator. | 03-29-2012 |
| 20120073371 | MICROELECTROMECHANICAL SENSOR - In various embodiments, a microelectromechanical system may include a mass element; a substrate; a signal generator; and a fixing structure configured to fix the mass element to the substrate; wherein the mass element is fixed in such a way that, upon an acceleration of the microelectromechanical system, the mass element can be moved relative to the substrate in at least two spatial directions, and wherein a signal is generated by the movement of the mass element by means of the signal generator. | 03-29-2012 |
| 20120072504 | DEVICES AND METHODS FOR MANAGING COLLABORATIVE COMMUNICATIONS SESSIONS - In an embodiment, a method for providing information for managing a collaborative communications session may be provided. The method may include generating a first message according to a call control protocol; generating a second message according to the call control protocol, the second message including information for managing the collaborative communications session; and sending the first message to a call managing server. The first message may be generated to include the second message. | 03-22-2012 |
| 20120072503 | METHODS AND DEVICES FOR AUTHORIZATION IN COLLABORATIVE COMMUNICATIONS SESSIONS - In an embodiment, a method for changing a collaborative communications session may be provided. The method may include: sending a request message requesting for authorizing a change of a collaborative communications session to an end device of the collaborative communications session; determining whether an authorization message is received from the end device in response to the request message sent; and changing the collaborative communications session, in case it is determined that an authorization message is received from the end device in response to the request message sent. | 03-22-2012 |
| 20120071200 | METHOD AND DEVICE FOR SELECTING A SERVING BASE STATION, MOBILE COMMUNICATION NETWORK, BASE STATION, AND METHOD FOR DETERMINING TRANSMISSION CHARACTERISTICS - According to one embodiment, a device for selecting a serving base station of a plurality of base stations of a mobile communication system is described which comprises a receiving circuit configured to receive, for each base station of the plurality of base stations, a message including information related to a possible communication between the base station and a mobile terminal and a selecting circuit configured to select, based on the determined information, a base station of the plurality of base stations that is to provide a communication connection for the mobile terminal. | 03-22-2012 |
| 20120071190 | BASE STATIONS AND RADIO DEVICES - According to an embodiment, a base station operates a first radio cell of a mobile communication network and signals, for a mobile terminal in the first radio cell having a communication connection via the base station, to a first radio device of a plurality of radio devices located in the first radio cell, wherein each radio device operates a second radio cell, that the first radio device is to provide a communication connection for the mobile terminal. Further, the base station signals, for the mobile terminal, to at least one second radio device of the plurality of radio devices, that the at least one second radio device is to take into account the allocation of radio resources by the first radio device for the communication connection to be provided for the mobile terminal when allocating radio resources for communication within the second radio cell operated by the at least one second radio device. | 03-22-2012 |
| 20120071120 | Adaptive Adjustment of Active Area for Power Amplifier - One embodiment of the present invention relates to a transmission circuit configured to dynamically adjust a number of active transistor cells within a power amplifier based upon a signal quality measurement determined from a feedback. The transmission circuit comprises a transmission chain having a power amplifier configured to provide an output signal. A feedback loop extends from the output of the power, amplifier to a control circuit and is configured to provide measured information about output signal (e.g., phase, amplitude, etc.) to the control circuit. The control circuit utilizes the measured signal information to evaluate a measured signal quality of the output signal. The control circuit dynamically adjusts a number of active transistor cells within a power amplifier based upon a signal quality measurement until the power amplifier is optimized to operate at an operating point for low current and good transmission quality. | 03-22-2012 |
| 20120070977 | Methods For Forming Contacts in Semiconductor Devices - Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance. | 03-22-2012 |
| 20120070941 | MODULE WITH SILICON-BASED LAYER - The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound. | 03-22-2012 |
| 20120069673 | METHOD AND DEVICE FOR PROGRAMMING DATA INTO NON-VOLATILE MEMORIES - A device includes a non-volatile memory and a control unit, wherein the control unit is configured to change over programming of data of the non-volatile memory from a first programming mode to a second, different programming mode based on the occurrence of a control signal. | 03-22-2012 |
| 20120069311 | Passivation of Multi-Layer Mirror for Extreme Ultraviolet Lithography - A reflector structure suitable for extreme ultraviolet lithography (EUVL) is provided. The structure comprises a substrate having a multi-layer reflector. A capping layer is formed over the multi-layer reflector to prevent oxidation. In an embodiment, the capping layer is formed of an inert oxide, such as Al | 03-22-2012 |
| 20120068345 | LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS - In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process. | 03-22-2012 |
| 20120068323 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE PACKAGE - A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively etching a second surface of the lead frame material sheet, the second surface being opposite to the first surface. | 03-22-2012 |
| 20120064849 | PA Bias Optimization for Modulation Schemes with Variable Bandwidth - One embodiment of the present invention relates to a method for improving the power consumption of a transmission chain by varying the operating point of a power amplifier to optimize (e.g., reduce) the current that is consumed by the amplifier. The operating point is varied by changing the bias voltage(s) (e.g., supply voltage, quiescent voltage) of the amplifier to a predetermined value that is chosen based upon the effect that a given transmitted signal modulation scheme characteristic (e.g., channel bandwidth and/or number of subcarriers) has on the operating point of a power amplifier. For example, if the characteristics indicate a good power amplifier performance the linear output power capability of a power amplifier can be lowered, by changing the bias voltage(s) supplied to the power amplifier, to reduce the output power capability and current consumption of the power amplifier. | 03-15-2012 |
| 20120062306 | Chip Comprising a Radio Frequency Switch Arrangement, Circuit Arrangement and Method for Producing a Radio Frequency Circuit Arrangement - A chip includes an RF switch arrangement that has a plurality of RF switches arranged jointly on the chip. Each of the RF switches has at least one first RF connection accessible from outside the chip and one second RF connection accessible from outside the chip. Furthermore, each of the RF switches is designed to activate, in response to a driving, at least one RF path between two of its RF connections. The RF connections of different switches from among the RF switches are separated from one another in terms of radio frequency. | 03-15-2012 |
| 20120062204 | Digital Voltage Converter Using A Tracking ADC - The disclosed DC-to-DC converter circuit comprises a tracking ADC configured to drive a DC-to-DC converter. In particular, the tracking ADC is configured to receive an analog feedback voltage from the output of the DC-to-DC converter. The analog feedback voltage is compared to an analog reference voltage and based upon the comparison a digital ADC output signal, comprising a digital code, is generated to drive the DC-to-DC converter. The digital ADC output signal is received by the DC-to-DC converter, which is configured to compare the digital code to a target code value. Based upon this comparison, the digital signal drives operation of the DC-to-DC converter by indicating whether the output of the DC-to-DC converter will be adjusted (e.g., by telling the DC-to-DC converter to increase its output voltage, to decrease its output voltage, or to keep its output voltage the same). Other systems and methods are also disclosed. | 03-15-2012 |
| 20120062137 | Method for Detection of Non-Zero-Voltage Switching Operation of a Ballast of Fluorescent Lamps, and Ballast - A method for use in a lamp ballast includes obtaining a measurement signal representative of a voltage at an output of a half-bridge circuit. The half-bridge circuit includes first and second semiconductor switching elements, a resonant circuit connected to the half-bridge circuit, and a snubber capacitance connected in parallel with one of the semiconductor switching elements. The method also includes providing a comparison sinal by comparing heeasurem ment signal with a reference value. The method further includes detecting one of a first type of non-zero-voltage switching operation and a second type of non-zero-voltage switching operation based on evaluations of the comparison signal, wherein the evaluations of the comparison signal occurs in each case before the first semiconductor element is switched on and in each case before the second semiconductor element is switched on. | 03-15-2012 |
| 20120061845 | Methods for filling a contact hole in a chip package arrangement and chip package arrangements - In various embodiments, a method for filling a contact hole in a chip package arrangement is provided. The method may include introducing electrically conductive discrete particles into a contact hole of a chip package; and forming an electrical contact between the electrically conductive particles and a contact terminal of the front side and/or the back side of the chip. | 03-15-2012 |
| 20120061835 | DIE STRUCTURE, DIE ARRANGEMENT AND METHOD OF PROCESSING A DIE - A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded. | 03-15-2012 |
| 20120061811 | APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES - An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a heat sink plate and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the heat sink plate. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. | 03-15-2012 |
| 20120061734 | Micro-Electromechanical System Devices - Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer. | 03-15-2012 |
| 20120058606 | Method of Fabricating A Semiconductor Device Having A Resin With Warpage Compensated Structures - A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion. | 03-08-2012 |
| 20120058362 | METHOD FOR DEPOSITING METAL ON A SUBSTRATE; METAL STRUCTURE AND METHOD FOR PLATING A METAL ON A SUBSTRATE - Various embodiments provide a method for depositing metal on a substrate. The method may include carrying out a first immersion plating process, thereby forming a first metal portion on the substrate; providing an immersion plating activating substance on the first metal portion; and carrying out a second immersion plating process using the immersion plating activating substance, thereby forming a second metal portion on the first metal portion. | 03-08-2012 |
| 20120057655 | Polar Transmitter Suitable for Monolithic Integration in SoCs - The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed. | 03-08-2012 |
| 20120056718 | TRANSPONDER AND METHOD FOR OPERATING A TRANSPONDER - An RFID transponder having an adjustable response field strength including a determination circuit formed to determine a quantity which is derivable from a field strength of an electromagnetic field prevailing at the location of the RFID transponder, a comparator formed to compare the determined quantity derived from the field strength with a threshold value, wherein the threshold value is based on the adjustable response field strength, which is higher than the minimum field strength required for the operation of the RFID transponder, and a deactivator formed to deactivate a functionality of the RFID transponder if the derived quantity falls below the threshold value. | 03-08-2012 |
| 20120056615 | Method and Apparatus for Defined Magnetizing of Permanently Magnetizable Elements and Magnetoresistive Sensor Structures - An apparatus includes a sensor arrangement with a sensor chip. A magnetic field generator is configured to generate a secondary magnetic field opposing an external primary magnetic field at the sensor chip. The magnetic field generator protects the sensor arrangement against the external primary magnetic field. | 03-08-2012 |
| 20120056240 | SEMICONDUCTOR DEVICE - A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate. | 03-08-2012 |
| 20120044102 | TIME-TO-DIGITAL CONVERTER WITH BUILT-IN SELF TEST - Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices. | 02-23-2012 |
| 20120043650 | Packaging Integrated Circuits - An integrated circuit | 02-23-2012 |
| 20120042296 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 02-16-2012 |
| 20120040628 | Transceiver with Interferer Control - Some embodiments of the present disclosure relate to a transceiver that includes multiple communication subunits associated with multiple communication protocols, respectively. The transceiver includes a conflict detection and control unit that determines whether interference is present or anticipated to occur between two or more of the communication subunits. If interference is present or anticipated, a local oscillator (LO) tuning unit changes an LO frequency provided to at least one of the two or more communication units. For example, in some embodiments, the LO tuning unit changes the LO frequency from high-side injection to low-side injection, or vice versa, or changes the intermediate frequency (IF) associated with a given communication subunit. In these ways, the techniques disclosed herein limit signal degradation due to interference from communication subunits residing within the transceiver. | 02-16-2012 |
| 20120038063 | REPAIRABLE SEMICONDUCTOR DEVICE AND METHOD - Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer. | 02-16-2012 |
| 20120036483 | DEVICE, METHOD FOR DISPLAYING A CHANGE FROM A FIRST PICTURE TO A SECOND PICTURE ON A DISPLAY, AND COMPUTER PROGRAM PRODUCT - A device is described having a memory storing data specifying a change animation between pictures to be displayed successively on the display, a setting circuit configured to store a setting specifying that a change animation between pictures to be displayed successively on the display is to be carried out in accordance with the specification of the change animation given by the data, a display controller configured to control a display to display a first picture, a detector configured to detect an event which triggers that a second picture is to be displayed on the display, a determination circuit configured to read the setting and to determine, based on the setting, a change animation between the first picture and the second picture, wherein the display controller is configured to control the display to display the change animation, and, after the change animation, to display the second picture. | 02-09-2012 |
| 20120033621 | COMMUNICATION DEVICES, METHOD FOR DATA COMMUNICATION, AND COMPUTER PROGRAM PRODUCT - A communication device is described comprising a transceiver, a determining circuit configured to determine whether the communication device may use radio resources, which are allocated to be used by a wireless bidirectional communication system in the geographical region in which the communication device is located, for radio data communication without participation by the wireless bidirectional communication system, and a controller configured to control the transceiver to carry out radio data communication using the radio resources if the communication device may use the radio resources. | 02-09-2012 |
| 20120033453 | Controller for a Resonant Switched-Mode Power Converter - In accordance with an embodiment, a switch controller for a switched-mode power supply includes an oscillator, an advance timing generator, and a dead zone generator. The advance timing generator generates an advance timing output pulse having a first pulse width that is asserted when the oscillator reaches a first phase. The dead zone generator produces a dead zone output having a second pulse width when the advance timing output pulse is de-asserted. This dead zone output pulse is coupled to a freeze input of the oscillator that freezes the phase accumulation of the oscillator when asserted. The controller also has a primary switch logic circuit that produces primary switch drive signals having a dead zone coincident with the dead zone output, and a secondary switch logic circuit that generates a secondary switch drive signal that is de-asserted when the advance timing output pulse becomes asserted. | 02-09-2012 |
| 20120032295 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SUCH A DEVICE - A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature. | 02-09-2012 |
| 20120032255 | INTEGRATED CIRCUIT HAVING COMPENSATION COMPONENT - An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed. | 02-09-2012 |
| 20120030531 | Safe Memory Storage By Internal Operation Verification - The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous. | 02-02-2012 |
| 20120028638 | RADIO COMMUNICATION DEVICES, INFORMATION PROVIDERS, METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE AND METHODS FOR CONTROLLING AN INFORMATION PROVIDER - In an embodiment, a radio communication device may be provided. The radio communication device may include a first receiver configured to receive from a first cell first data representing a content encoded using a first codec; a second receiver configured to receive from a second cell second data representing the content encoded using a second codec; and a combiner configured to combine the first data and the second data. | 02-02-2012 |
| 20120028382 | SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP, AND METHOD FOR THE PRODUCTION THEREOF - A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer. | 02-02-2012 |
| 20120027928 | ELECTRONIC DEVICE - An electronic device is disclosed. One embodiment provides a metallic body. A first electrically insulating layer is applied over the metallic body and having a thickness of less than 100 μm. A first thermally conductive layer is applied over the first electrically insulating layer and having a thermal conductivity of more than 50 W/(m·K). A second electrically insulating layer is applied over the first thermally conductive layer and having a thickness of less than 100 μm. | 02-02-2012 |
| 20120026793 | Nonvolatile Memory Cell With Extended Well - One embodiment relates to a memory device. The memory device includes a capacitor having a first capacitor plate and a second capacitor plate, wherein the first and second capacitor plates are separated by an insulating layer and are formed over a first portion of a semiconductor substrate. The memory device also includes a transistor having a source region, a drain region, and a gate region, where the gate region is coupled to the second capacitor plate. The transistor is formed over a second portion of the semiconductor substrate. A well region is disposed in the first and second portions of the semiconductor substrate and has a doping-type that is opposite a doping-type of the semiconductor substrate. Other embodiments are also disclosed. | 02-02-2012 |
| 20120026781 | RESISTIVE MEMORY AND METHOD - A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. | 02-02-2012 |
| 20120025808 | OFF-CENTER ANGLE MEASUREMENT SYSTEM - A method for measuring an angular position of a rotating shaft, the method including providing a magnetic field which rotates with the shaft about an axis of rotation, positioning an integrated circuit having first and second magnetic sensing bridges within the magnetic field at a radially off-center position from the axis of rotation, the first and second magnetic sensing bridges respectively providing first and second signals representative of first and second magnetic field directions, the integrated circuit having a set of adjustment parameters for modifying attributes of the first and second signals, modifying values of the set of adjustment parameters until errors in the first and second signals are substantially minimized, and determining an angular position of the shaft based on the first and second signals. | 02-02-2012 |
| 20120025393 | Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module - A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug. | 02-02-2012 |
| 20120025384 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 02-02-2012 |
| 20120025382 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 02-02-2012 |
| 20120025325 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 02-02-2012 |
| 20120020145 | Identification Circuit and Method for Generating an Identification Bit - A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another. | 01-26-2012 |
| 20120013884 | Metrology Systems and Methods for Lithography Processes - Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask. | 01-19-2012 |
| 20120012924 | Vertical Transistor Component - A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface. | 01-19-2012 |
| 20120008715 | Digital Phase Feedback for Determining Phase Distortion - A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information. | 01-12-2012 |
| 20120007176 | High-Voltage Bipolar Transistor with Trench Field Plate - A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate. | 01-12-2012 |
| 20120002333 | ESD Clamp Adjustment - Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses. | 01-05-2012 |
| 20110318883 | POWER SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF - A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided. | 12-29-2011 |
| 20110316160 | Semiconductor Arrangement, Semiconductor Module, and Method for Connecting a Semiconductor Chip to a Ceramic Substrate - A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least | 12-29-2011 |
| 20110312328 | COMMUNICATION TERMINAL, COMMUNICATION DEVICE, METHOD FOR DATA COMMUNICATION, AND METHOD FOR FREQUENCY ALLOCATION - A communication terminal is described comprising a determiner configured to determine, for a frequency region, a plurality of first communication devices from which the communication terminal receives a signal via the frequency region; a selector configured to select at least one of the first communication devices based on a predetermined interference criterion; a signal generator configured to generate a signal with an identification of the at least one selected first communication device; and a transceiver configured to transmit the signal to a second communication device, to receive an indication from the second communication device specifying whether the communication terminal should use the frequency region for data communication with the second communication device, and to carry out data communication with the second communication device using the frequency region depending on the indication. | 12-22-2011 |
| 20110312274 | RADIO COMMUNICATION DEVICE, RECEIVER CONTROLLER OF A RADIO COMMUNICATION DEVICE, METHODS FOR SEARCHING FOR A RADIO CELL - Embodiments relate generally to a radio communication device, to a receiver controller of a radio communication device, and to a method for searching for a radio cell. In an embodiment, a method for searching for a radio cell is provided. The method may include scanning at least one frequency band of a first radio access technology, scanning at least one frequency band of a second radio access technology, wherein the at least one frequency band of the second radio access technology at least partially overlaps with the at least one frequency band of the first radio access technology, wherein at least one frequency sub-band of the first radio access technology is not scanned in the at least one frequency band of the second radio access technology. | 12-22-2011 |
| 20110310988 | Communication Methods and Apparatuses - Communication methods and apparatuses are provided. | 12-22-2011 |
| 20110310674 | System and Method for Bit-Line Control - In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor. | 12-22-2011 |
| 20110310568 | Circuit Arrangement with Shunt Resistor - A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction. | 12-22-2011 |
| 20110309814 | USE OF AUXILIARY CURRENTS FOR VOLTAGE REGULATION - One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator. | 12-22-2011 |
| 20110309810 | Electronic Circuit and Semiconductor Arrangement With a Load, a Sense and a Start-Up Transistor - Disclosed is an electronic circuit with a first load terminal, a second load terminal, a supply terminal configured for having a charge storage arrangement connected thereto, and a load transistor, a current sense circuit with a sense transistor, and a start-up circuit with a start-up transistor. | 12-22-2011 |
| 20110309441 | INTEGRATED SEMICONDUCTOR DEVICE HAVING AN INSULATING STRUCTURE AND A MANUFACTURING METHOD - An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided. | 12-22-2011 |
| 20110309423 | SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING - A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension. | 12-22-2011 |
| 20110308866 | Sensor Measurement System Using Pulsed Current Signals - The disclosed invention provides a structure and method for easily measuring capacitive and/or resistive components of a sensor system. In one embodiment, the structure comprises a signal generator configured to output a load current to a measurement element containing measurement sensor elements and a parasitic capacitance. A controllable excitation voltage is generated, via integration of the load current on the parasitic capacitance, and output to the measurement sensor elements having capacitive and resistive components. The controlled voltage through the measurement device may be manipulated to cause the capacitive and resistive components to exhibit a transient effect. The resulting output current, provided from the measurement device therefore has transient response characteristics (e.g., the settling time, amplitude) that can be selectively measured by a measurement circuit to easily determine values of the capacitive and resistive measurement elements. Furthermore, dedicated demodulation techniques may be used to measure the capacitive and resistive components. | 12-22-2011 |
| 20110305284 | Method for Transmitting a Data Signal in a MIMO System - A method for transmitting a data signal by a transmission unit of a wireless multiple-input/multiple-output (MIMO) communication system. The communication system includes the transmission unit and a reception unit, the transmission unit having a plurality of transmission antennas and the reception unit having a plurality of reception antennas. The method includes performing a first transmission of a data signal, the first transmission including transmitting the data signal by each one of the plurality of transmission antennas, and performing a second transmission of the data signal at a time later than the first transmission, the second transmission including transmitting at least one spectrally modified signal variant of the data signal by at least one antenna of the plurality of transmission antennas. | 12-15-2011 |
| 20110304940 | Protection Circuit - A protection circuit includes a controllable discharge element having a load path coupled between a first second circuit nodes. The discharge element provides a discharge path between the first and the second circuit nodes when in an on state. A trigger circuit has a first connection coupled to the first circuit node and a second connections coupled to the second circuit node. The trigger circuit is configured to produce a drive signal that switches the discharge element to its on state when the voltage between the first and the second circuit nodes reaches a trigger value. A setting circuit coupled to the trigger circuit is configured to change the trigger value from a first trigger value to a second trigger value depending on a voltage between the first and the second circuit nodes and/or on the drive signal. | 12-15-2011 |
| 20110304487 | FLOATING POINT TIMER TECHNIQUES - Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications. | 12-15-2011 |
| 20110304047 | Method for Producing a Composite Material, Associated Composite Material and Associated Semiconductor Circuit Arrangements - A method for producing a composite material, associated composite material and associated semiconductor circuit arrangements is disclosed. A plurality of first electrically conducting material particles are applied to a carrier substrate and a second electrically conducting material is galvanically deposited on a surface of the first material particles in such a way that the second material mechanically and electrically bonds the plurality of first material particles to one another. | 12-15-2011 |
| 20110303948 | ESD and EMC optimized HV-MOS Transistor - Devices and circuits related to Electrostatic discharge (ESD) and Electromagnetic compatibility (EMC) are herein described. An ESD protection device is incorporated into a transistor in order to protect the gate of the transistor from excessive current loads related to ESD or EMC events. In an implementation, a device includes a first diode and a second diode that are electrically connected via their respective cathodes. The breakdown voltage of the first diode is lower than the breakdown voltage of the second diode in order to divert excessive current through the second diode. | 12-15-2011 |
| 20110300864 | MOBILE RADIO COMMUNICATION SYSTEM - A mobile radio communication system having a mobile radio communication network and a mobile radio subscriber appliance, wherein a unit in the network layer of the core network of the mobile radio communication network is configured to transmit to the mobile radio subscriber appliance a first message, based on an occurrence of a predetermined event, with a request for a statement which describes at least one radio characteristic of the mobile radio subscriber appliance. | 12-08-2011 |
| 20110298454 | Current Sensor - A current sensor includes a conductive element, at least two magnetic field sensors arranged on the conductive element and adapted to sense a magnetic field generated by a current through the conductor element. The at least two magnetic field sensors are arranged on opposite sides of a line perpendicular to a current flow direction in the conductive element, an insulating layer is arranged between the conductive element and the magnetic field sensors, and a conductor trace is connected to the magnetic field sensors. | 12-08-2011 |
| 20110298085 | SHALLOW TRENCH ISOLATION AREA HAVING BURIED CAPACITOR - A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area. | 12-08-2011 |
| 20110294451 | RECEIVER - A receiver includes an input to receive data of a pilot channel having a carrier frequency associated therewith, and a first unit to obtain a quantity, wherein the quantity depends on a frequency broadening of the received data and a frequency shift of the received data with respect to the carrier frequency. The receiver also includes a second unit to adjust the bandwidth of a channel estimation unit, wherein the adjustment depends on the quantity. | 12-01-2011 |
| 20110294238 | SEMICONDUCTOR WAFER WITH ELECTRICALLY CONNECTED CONTACT AND TEST AREAS - The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit. | 12-01-2011 |
| 20110291274 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips. | 12-01-2011 |
| 20110289377 | SYSTEMS AND METHODS FOR SECURE INTERRUPT HANDLING - The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. | 11-24-2011 |
| 20110285033 | Chip Carrier - Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location. | 11-24-2011 |
| 20110285030 | METHOD FOR PRODUCING CHIP PACKAGES, AND CHIP PACKAGE PRODUCED IN THIS WAY - A method for producing chip packages is disclosed. In one embodiment, a plurality of chips is provided. The chips each have first pads. Second connection pads are applied on the wafer, wherein each second pad is electrically connected to a first pad. | 11-24-2011 |
| 20110284970 | Transistor Device and Methods of Manufacture Thereof - Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor. | 11-24-2011 |
| 20110281405 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip. | 11-17-2011 |
| 20110278730 | Semiconductor Devices and Structures Thereof - A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region. | 11-17-2011 |
| 20110278680 | Strained Semiconductor Device and Method of Making the Same - In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess. | 11-17-2011 |
| 20110270553 | Apparatus, Sensor Circuit, and Method for Operating an Apparatus or a Sensor Circuit - An apparatus is described, including: a signal processing circuit adapted to process an input signal to obtain an output signal; a sensor element for sensing a predetermined physical quantity, wherein the sensor element is adapted to generate a sensor signal in response to the predetermined physical quantity; wherein the signal processing unit is adapted to process the input signal to obtain the output signal depending on the sensor signal; and wherein the apparatus further comprises an evaluation circuit adapted to evaluate the sensor signal and to generate an indication signal indicating an abnormal operating condition in case the sensor signal does not fulfill a predetermined normal operation criterion. | 11-03-2011 |
| 20110269447 | MOBILE RADIO COMMUNICATION NETWORK DEVICE, MOBILE TERMINAL, AND METHOD FOR TRANSMISSION/RECEPTION OF CONTROL INFORMATION - A mobile radio communication network device is descried including a receiver configured to receive control information from a mobile terminal, wherein the receiver is configured to receive the control information in a first mode or in a second mode, wherein in the second mode, less of the control information is received in time from the mobile terminal than in the first mode, and a controller configured to control the receiver to receive the control information in the first mode if the mobile terminal is associated with a first mobile terminal mobility class and to control the receiver to receive the information in the second mode if the mobile terminal is associated with a second mobile terminal mobility class. | 11-03-2011 |
| 20110269073 | METHOD FOR APPLYING A RESIST LAYER, USES OF ADHESIVE MATERIALS, AND ADHESIVE MATERIALS AND RESIST LAYER - A method in which a resist layer is applied to a base layer is disclosed. The resist layer includes an adhesive material, and the adhesive force of the adhesive material decreases or increases during an irradiation process. Residues of the resist layer may be stripped using the disclosed method. | 11-03-2011 |
| 20110268046 | COMMUNICATION NETWORK DEVICE, COMMUNICATION TERMINAL, AND COMMUNICATION RESOURCE ALLOCATION METHODS - A communication network device of a communication system is described comprising a transmitter configured to transmit data in a plurality of frames, wherein in each frame, a plurality of communication resource elements is provided to be allocated for data transmission of downlink control data, wherein a data communication resource element is defined by a frequency range and a communication time interval within the frame and a communication resource allocator configured to allocate a first set of the communication resource elements of the plurality of communication resource elements provided to be allocated for data reception of downlink control data in a frame for the transmission of the downlink control data and to allocate a second set of the communication resource elements of the plurality of communication resource elements provided to be allocated for data reception of downlink control data in the frame that have not been allocated for the transmission of downlink control data for the transmission of data of another type than the downlink control data. | 11-03-2011 |
| 20110261542 | DIE PACKAGE - In an embodiment, a die package may be provided. The die package may include at least one first height adjusting structure, the at least one first height adjusting structure may include a first adjusting height relative to a common plane; at least one second height adjusting structure may be positioned adjacent to the at least one first height adjusting structure, the at least one second height adjusting structure may include a second adjusting height relative to the common plane; wherein the second adjusting height may be different from the first adjusting height relative to the common plane; a first die may be positioned on the at least one first height adjusting structure; and a mold housing substantially surrounding the at least one first height adjusting structure, the at least one second height adjusting structure and the first die. | 10-27-2011 |
| 20110260307 | INTEGRATED CIRCUIT INCLUDING BOND WIRE DIRECTLY BONDED TO PAD - An integrated circuit includes a chip including a copper bond pad metallization, and a copper bond wire including a copper ball. The copper ball is bonded directly to the copper bond pad. | 10-27-2011 |
| 20110260302 | SHIELDING DEVICE - One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit. | 10-27-2011 |
| 20110258844 | METHOD OF MANUFACTURING A POWER TRANSISTOR MODULE AND PACKAGE WITH INTEGRATED BUS BAR - According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections. | 10-27-2011 |
| 20110256749 | Press-Fit Connections for Electronic Modules - A press-fit connecting element for being pressed into a first contact opening in a first connection element and into a second contact opening in a second connection element is provided. The press-fit connecting element includes an elongated base body configured to be guided through the second contact opening in the second connection element to the first contact opening in the first connection element. The press-fit connecting element further includes a first press-fit zone configured to contact-connect the first contact opening in a force-fitting manner and a second press-fit zone which is at a distance from the first press-fit zone in a longitudinal direction and configured to contact-connect the second contact opening in a force-fitting manner. | 10-20-2011 |
| 20110256688 | SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench. | 10-20-2011 |
| 20110254589 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements. | 10-20-2011 |
| 20110254018 | Semiconductor Switching Arrangement Having a Normally on and a Normally off Transistor - A semiconductor switching arrangement includes a normally on semiconductor component of a first conduction type and a normally off semiconductor component of a second conduction type which is the complement of the first conduction type. A load path of the normally off semiconductor component is connected in series with the load path of the normally on semiconductor component. A first actuation circuit connected between the control connection of the normally on semiconductor component and a load path connection of the normally on semiconductor component. The load path connection of the normally on semiconductor component is arranged between the normally on and normally off semiconductor components. A second actuation circuit is connected between the control connection of the normally off semiconductor component and a load path connection of the normally off semiconductor component. The load path connection of the normally off semiconductor component is arranged between the normally on and normally off semiconductor components. | 10-20-2011 |
| 20110250856 | Direct FM/PM Modulation - Representative implementations of direct FM/PM modulation and systems are disclosed describing frequency modulation or phase modulation of information onto a carrier signal using a divider that is remote from the carrier signal generation path. | 10-13-2011 |
| 20110250740 | METHOD AND DEVICE FOR THE TREATMENT OF A SEMICONDUCTOR SUBSTRATE - Method for the treatment of a semiconductor substrate ( | 10-13-2011 |
| 20110250530 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced. | 10-13-2011 |
| 20110248792 | CIRCUIT ARRANGEMENT WITH IMPROVED DECOUPLING - A circuit arrangement includes a component having a closed signal path, that closed signal path connected to a first port, a second port and at least a third port. The component has a directed signal flow of a signal applied to one of that ports. Such a coupling device can be connected to a transmitter and to a receiver path, respectively. | 10-13-2011 |
| 20110248753 | Suppression of Low-Frequency Noise from Phase Detector in Phase Control Loop - The disclosed invention provides a structure and method for improving performance of a phase locked loop by suppressing low-frequency noise produced by a phase detector. This is achieved by up-conversion of the in-band frequency components in the phase difference between reference signal and feedback signal to a higher frequency range where noise performance of a phase detector is improved. The up-converted phase difference is provided to a phase detector that is configured to determine an error signal based upon this phase difference. The error signal is output to a down-converter configured to down-convert the error signal (e.g., back to the original frequency range), thereby intrinsically up-converting the error signal's low-frequency noise (produced by the phase detector), prior to being provided to a filter configured to filter the up-converted noise, thereby resulting in an improved PLL noise performance. | 10-13-2011 |
| 20110248711 | MAGNETIC FIELD CURRENT SENSORS - Current sensors, conductors and methods are disclosed. A magnetic current sensor includes a conductor including a first sheet metal layer having a first thickness and including at least one notch extending inwardly from a first edge of the first sheet metal layer, and a second sheet metal layer having a second thickness less than the first thickness and including at least one notch, the second sheet metal layer being coupled to the first sheet metal layer such that the at least one notch of the first sheet metal layer is generally aligned with the at least one notch of the second sheet metal layer; and an integrated circuit (IC) die including at least one magnetic sensor element and being coupled to the conductor such that the at least one magnetic sensor element is generally aligned with a tip of the at least one notch of the second sheet metal layer. | 10-13-2011 |
| 20110248234 | VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer. | 10-13-2011 |
| 20110244811 | Demodulator and Method for Demodulating a Modulated Carrier Signal - A demodulator includes a sampler configured to sample a plurality of first amplitude values of a modulated carrier signal using a constant sampling frequency and a plurality of second amplitude values of the modulated carrier signal at different times using the same constant sampling frequency. The constant sampling frequency is equal to a carrier frequency of the modulated carrier signal with a tolerance of +/−1% of the carrier frequency. | 10-06-2011 |
| 20110243261 | COMMUNICATION DEVICE - According to one embodiment, a communication device is described comprising a communication circuit configured to communicate in a first communication mode using a first frequency range and a receiver configured to receive a switching delay information message indicating a time interval by which start of communication in a second communication mode using a second frequency range should be delayed after a switch from the first communication mode to the second communication mode. The communication circuit is configured to communicate in the second communication mode when the time interval has elapsed since the start of the switching from the first communication mode to the second communication mode. | 10-06-2011 |
| 20110243200 | Demodulator and Method for Demodulating a Carrier Signal - A demodulator includes a sampler and a trigger unit. The sampler is configured to sample a carrier signal based on a trigger signal to obtain a demodulated signal. The trigger unit is configured to detect a zero crossing of the carrier signal or an extreme value of an amplitude of the carrier signal. Further, the trigger unit is configured to provide the trigger signal based on the detected zero crossing or the detected extreme value, so that the carrier signal is sampled by the sampler with a predefined phase shift to the detected zero crossing or the detected extreme value. The predefined phase shift is larger than 30° plus an integer multiple of 90° and lower than 60° plus the same integer multiple of 90° in reference to the carrier signal. | 10-06-2011 |
| 20110234472 | Integrated Circuit Package Assembly Including Wave Guide - Some embodiments herein relate to a transmitter. The transmitter includes an integrated circuit (IC) package including a first antenna configured to radiate a first electromagnetic signal therefrom. A printed circuit board (PCB) substrate includes a waveguide configured to receive the first electromagnetic signal and to generate a waveguide signal based thereon. A second antenna can be electrically coupled to the waveguide and can radiate a second electromagnetic signal that corresponds to the waveguide signal. Other devices and methods are also disclosed. | 09-29-2011 |
| 20110234215 | Sensor Package and Method for Producing a Sensor Package - Some embodiments herein relate to a sensor package. The sensor package includes a printed circuit board with a laminar current conductor arranged on a first main surface of the printed circuit board. The sensor package also includes a sensor chip adapted to measure a current flowing through the laminar current conductor, wherein the sensor chip comprises a magnetic field sensor. The sensor chip is electrically insulated from the current conductor by the printed circuit board, and is arranged on a second main surface of the printed circuit board opposite to the first main surface. The sensor chip is hermetically sealed between the mold material and the printed circuit board, or is arranged in the printed circuit board and hermetically sealed by the printed circuit board. | 09-29-2011 |
| 20110233721 | SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench. | 09-29-2011 |
| 20110233630 | INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR SUBSTRATE WITH BARRIER LAYER - An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element. | 09-29-2011 |
| 20110231718 | MEMORY REPAIR - A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime. | 09-22-2011 |
| 20110227204 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. An encapsulating body encapsulates the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. At least one of the second conducting element, third conducting element, and fourth conducting element extend over the semiconductor chip and the encapsulating body. | 09-22-2011 |
| 20110216561 | Low-Inductance Power Semiconductor Assembly - A power semiconductor assembly includes at least two bridge branches each including at least two circuit breakers connected to a phase output. Each of the circuit breakers has at least two parallel-connected switching elements integrated into a semiconductor chip. Each of the circuit breakers is arranged in a power semiconductor module and the individual power semiconductor modules are arranged adjacent to one another in a first direction. The semiconductor chips of a particular circuit breaker are arranged adjacent to one another in the corresponding power semiconductor module in a second direction extending perpendicular to the first direction. | 09-08-2011 |
| 20110215955 | SYSTEM INCLUDING FEEDBACK CIRCUIT WITH DIGITAL CHOPPING CIRCUIT - A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The chopping circuit is configured to receive the digital output signals and provide error signals that represent ripple error in the digital output signals. The integrator circuit is configured to accumulate the error signals and provide an accumulated error signal. The digital to analog converter circuit is configured to convert the accumulated error signal into an analog signal that is received by the second circuit to reduce the ripple error. | 09-08-2011 |
| 20110215460 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane. | 09-08-2011 |
| 20110215158 | Passive RFID Transponder and RFID Reader - A passive RFID transponder includes a coder and a modulator. The coder generates a digital coded data stream based on a digital data stream to be transmitted. The digital coded data stream includes an initialization bit sequence having a maximum data frequency of the digital coded data stream. Furthermore, the digital coded data stream changes its value at the latest after a predefined number of bits. The modulator modulates an amplitude of a carrier signal with the digital coded data stream to provide an amplitude-modulated coded signal. | 09-08-2011 |
| 20110211552 | COMPUTED-AIDED MAPPING OF SYSTEM INFORMATION MEDIUM ACCESS CONTROL PROTOCOL MESSAGES - A method for computer-aided mapping of system information medium access control protocol messages onto a plurality of transport channels for transmission using an orthogonal frequency division multiple access method, wherein a scheduling of system information data packets information in the context of the mapping on a transport channel of the plurality of transport channels is carried out dependent on the type of the system information. | 09-01-2011 |
| 20110210840 | POSITION IDENTIFICATION SYSTEM AND METHOD - A position identification system and method include a receiver configured to receive an initiation signal and attenuate the initiation signal until the initiation signal is within a first predetermined range of a reference signal. A controller identifies the position of the receiver in response to the attenuation. | 09-01-2011 |
| 20110210798 | Ring Oscillator for Providing Constant Oscillation Frequency - Some embodiments disclosed herein relate to techniques for providing a relatively constant oscillation frequency. In some instances, these techniques can make use of a ring oscillator that is powered by an adaptive voltage supply. The adaptive voltage supply provides a temperature-dependent supply voltage to respective delay elements in the ring oscillator, such that the oscillation frequency of the ring oscillator is approximately constant over a predetermined temperature range. For example, if temperature increases, the supply voltage can be increased proportionally, thereby tending to limit variation in the oscillation frequency delivered by the ring oscillator. | 09-01-2011 |
| 20110210782 | Integrated Circuit with a Radiation-Sensitive Thyristor Structure - An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data. | 09-01-2011 |
| 20110209556 | STRESS SENSING DEVICES AND METHODS - Embodiments relate to stress sensing devices and methods. In an embodiment, a sensor device includes an active layer; and at least three contacts spaced apart from one another in the active layer, the at least three contacts being coupleable in a first configuration for a first operating mode of the sensor device in which a current in the active layer has a first ratio of horizontal to vertical components with respect to a die surface and in a second configuration different from the first for a second operating mode of the sensor device in which a current in the active layer has a second ratio of horizontal to vertical components, wherein a ratio of a resistance between at least two of the contacts in the first operating mode and a resistance between at least two of the contacts in the second operating mode is related to mechanical stress in the sensor device. | 09-01-2011 |
| 20110208948 | READING TO AND WRITING FROM PERIPHERALS WITH TEMPORALLY SEPARATED REDUNDANT PROCESSOR EXECUTION - Embodiments relate to systems and methods for reading from and writing to interface peripherals or other shared resources during robust computation utilizing temporally separated redundant execution. Embodiments can be utilized in safety-relevant applications related to automotive, banking and finance, aerospace, defense, Internet payment, and others. | 08-25-2011 |
| 20110206171 | Interference Suppression Processing Unit and a Method of Suppressing Interference in Wireless Data Communication - An interference suppression processing unit includes at least one receive path, wherein each of the at least one receive path is configured to transmit one of at least one received data sequence received from at least one antenna port, a signal generation unit configured to generate at least one signal data sequence from the at least one received data sequence, at least one signal path, wherein each of the at least one signal path is configured to transmit one of the at least one signal data sequence, at least one prefilter unit, wherein each of the at least one prefilter unit is coupled to one of the at least one signal path and a combiner including at least one input terminal, wherein each of the at least one input terminal is connected to an output terminal of one of the at least one prefilter unit, wherein the signal generation unit is configured to generate K1 first signal data sequences, wherein each first signal data sequence is identical to one of the at least one received data sequence, respectively, and K2 second signal data sequences, wherein each second signal data sequence is not identical to one of the at least one received data sequence, respectively, and wherein the number of the first signal data sequences and the second signal data sequences (K1+K2) equals the number of the at least one signal data sequence. | 08-25-2011 |
| 20110204887 | CURRENT SENSORS AND METHODS - Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a conductor portion having a first portion and a second portion; at least three slots formed in the conductor portion between the first and second portions, each of the at least three slots having a length and at least one tip portion; at least two bridge portions each having a width separating two of the at least three slots and a length coupling the first and second portions; a first contact region disposed relative to the first portion and a second contact region disposed relative to the second portion; and at least one pair of magnetic sensor elements, a first pair of magnetic sensor elements arranged relative to and spaced apart from a first of the at least two bridge portions. | 08-25-2011 |
| 20110201186 | METHOD AND APPARATUS FOR REDUCING FLICKER NOISE IN A SEMICONDUCTOR DEVICE - Some embodiments discussed relate to an integrated circuit and methods for making it. In an example, a method can include providing a semiconductor wafer including a fin, and introducing a noise-reducing dopant into a sidewall of the fin. | 08-18-2011 |
| 20110200075 | Device and Method for Selecting a Path from an Estimated Delay Profile of a Radio Signal - A device includes a delay profile estimator to estimate a delay profile of multiple paths of a radio signal, wherein the delay profile indicates signal powers of the multiple paths as a function of time delay. The device further includes a path selector to select a path from the delay profile if the path has a signal power higher than a threshold. The threshold has a first threshold value in a first section of the delay profile which is higher than a second threshold value in a second section of the delay profile. | 08-18-2011 |
| 20110199132 | SYSTEM PROVIDING A SWITCHED OUTPUT SIGNAL AND A HIGH RESOLUTION OUTPUT SIGNAL - A system including a sensing system, a first chopped circuit, a second chopped circuit, and a clock generator. The sensing system is configured to provide sensed input signals. The first chopped circuit is configured to provide a switched output signal that switches in response to values of the sensed input signals crossing a limit. The second chopped circuit is configured to provide a high resolution output signal that corresponds to the sensed input signals and has a higher resolution than the switched output signal. The clock generator is configured to provide clock signals that synchronize chopping of the first chopped circuit and the second chopped circuit. | 08-18-2011 |
| 20110195682 | DIVERSITY RECEIVER - A diversity receiver includes a plurality of receiver circuits that are configured to receive and process the received radio frequency signals. A channel estimator is coupled to at least one of the plurality of receiver circuits and is configured to determine at least one channel estimation value for the received radio frequency signals. A controller is coupled to the channel estimator and to at least one of the plurality of receiver circuits and is configured to selectively activate or deactivate the at least one of the plurality of receiver circuits based on the determined at least one channel estimation value. | 08-11-2011 |
| 20110194364 | NVM OVERLAPPING WRITE METHOD - The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). Specifically, the write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit. This interleaving of data bit write windows allows a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) reducing overall memory write time. | 08-11-2011 |
| 20110193557 | CURRENT SENSOR INCLUDING A SINTERED METAL LAYER - An integrated circuit includes a semiconductor die including a first magnetic field sensor. The integrated circuit includes an isolation material layer over the first magnetic field sensor and a sintered metal layer over the isolation material layer. The first magnetic field sensor is configured to sense a magnetic field generated by a current passing through the sintered metal layer. | 08-11-2011 |
| 20110191658 | Method and Apparatus for Storing Data - When coding user data, it may be desirable to mark user data as invalid. This may arise, by way of example, in applications in which a stored data item needs to be updated by virtue of an updated data item additionally being stored and the old stored data item being marked as invalid. In order to mark the invalidity of a stored data item by means of the value of the data item and to be able to apply an error-recognizing or error-correcting coding dependably, the user data are extended by supplementary data and the coding is applied to the extended user data. | 08-04-2011 |
| 20110190011 | RADIO BASE STATIONS, RADIO COMMUNICATION DEVICES, METHODS FOR CONTROLLING A RADIO BASE STATION, AND METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE - In various embodiments, a radio base station may be provided. The radio base station may include a transceiver configured to communicate with a radio communication device using a plurality of component carriers; and a message generator configured to generate an idle mode message including an information item related to at least one of the component carriers of the plurality of component carriers of the radio base station. The transceiver may further be configured to transmit the generated idle mode message to the radio communication device. | 08-04-2011 |
| 20110189999 | METHOD AND APPARATUSES FOR TWO OR MORE NEIGHBORING WIRELESS NETWORK DEVICES ACCESSING A PLURALITY OF RADIO RESOURCES - Methods and apparatuses for two or more neighboring base stations to access a plurality of radio resources are described. The method includes defining a channel quality requirement by one or more access conditions and assigning the plurality of radio resources to the channel quality requirement, wherein a neighboring base station has access to the plurality of radio resources and the neighboring base station neighbors a target base station. The method also includes allowing the target base station access to the plurality of radio resources if the target base station satisfies the channel quality requirement. | 08-04-2011 |
| 20110189969 | Receiver Arrangement with AC Coupling - A receiver arrangement with AC coupling is specified in which a filter arrangement ( | 08-04-2011 |
| 20110189821 | SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer. | 08-04-2011 |
| 20110188604 | Digital Modulator and Digital-to-Analog Conversion Techniques Associated Therewith - Some embodiments disclosed herein relate to a transmitter. The transmitter includes a digital modulator adapted to provide a digital modulated RF signal based on a multi-bit representation of data and a multi-bit representation of a carrier wave. A digital-to-analog converter (DAC) is adapted to generate an analog modulated RF signal based on the digital modulated RF signal. A resonant circuit coupled to an output of the DAC and adapted to filter undesired frequency components from the analog modulated RF signal. | 08-04-2011 |
| 20110188446 | ENABLING IMS SERVICES FOR NON-IMS UEs VIA A HOME BASE STATION SUBSYSTEM - Apparatuses and methods for enabling IMS services for non-IMS UEs via a home base station subsystem are described. In various embodiments, a home base station subsystem includes a message generator configured to generate an Internet Protocol multimedia subscription request message comprising a unique user identifier and an information request message, the information request message requesting an Internet Protocol multimedia subscription for the user identified by the unique user identifier. The home base station subsystem also includes a transmitter configured to transmit the generated Internet Protocol multimedia subscription request message to a user database. | 08-04-2011 |
| 20110187587 | RECEIVER TEST CIRCUITS, SYSTEMS AND METHODS - Embodiments relate to apparatuses, systems and methods for testing high-frequency receivers. In an embodiment, a method includes integrating a pulse train generator and a receiver in an integrated circuit; generating a pulse train by the pulse train generator and applying the pulse train to an input of the receiver; measuring at least one property of the pulse train; and determining at least one characteristic of the receiver using the at least one property of the pulse train. In an embodiment, an integrated circuit includes a receiver, and a pulse train generator configured to generate a pulse train and apply the pulse train to an input of the receiver, wherein at least one characteristic of the receiver can be determined using at least one measured property of the pulse train. | 08-04-2011 |
| 20110187433 | On-Chip Self Calibrating Delay Monitoring Circuitry - The present disclosure relates to on-chip self calibrating delay monitoring circuitry. | 08-04-2011 |
| 20110187350 | Magnetic-Field Sensor and Method of Calibrating a Magnetic-Field Sensor - An embodiment of a magnetic-field sensor has a plurality of sensor elements connected to form measurement arrangements, each measurement arrangement having a measurement tap, and a control circuit formed to perform an embodiment of a method of calibrating the magnetic-field sensor. | 08-04-2011 |
| 20110181459 | SYSTEMS AND METHODS FOR INCIDENT ANGLE MEASUREMENT OF WAVES IMPINGING ON A RECEIVER - Embodiments relate to radar systems and methods. In an embodiment, a system includes a radio frequency (RF) sensor array comprising a plurality of spaced apart sensors; and a reflector element positioned proximate the RF sensor array to reflect waves toward the RF sensor array. In an embodiment, a system includes an antenna array comprising a transceive antenna and a plurality of receive antennas; a mirror arranged proximate the antenna array; a voltage controlled oscillator (VCO) configured to generate a signal to be transmitted by the transceive antenna; and a controller configured to resolve signals received by the plurality of receive antennas to determine an angular position of a target, wherein the signals received include a first portion of the signal reflected by the target and a second portion of the signal reflected by the target and the mirror. | 07-28-2011 |
| 20110176589 | METHODS AND SYSTEMS FOR MEASURING DATA PULSES - Some embodiments disclosed herein relate to a method. In the method, a duration of a first synchronization pulse is measured. A fixed, predetermined number of ticks are equally spaced at a first time interval over the first sync pulse, regardless of the duration of the first synchronization pulse. A duration of a first data pulse is then measured by periodically incrementing a tick count value at the first time interval during the entire duration of the first data pulse. The tick count value at an end of the first data pulse is then correlated to a first digital value encoded on the first data pulse. | 07-21-2011 |
| 20110176561 | TIME-BASED MAINTENANCE VIA A PACKET-ORIENTED DIGITAL INTERFACE IN RADIO-FREQUENCY TRANSMITTING AND RECEIVING ASSEMBLIES - Disclosed herein are techniques, systems, and methods relating maintaining a time base between receiving and transmitting assemblies during interruption of data streams communicated therebetween. | 07-21-2011 |
| 20110175214 | Power Semiconductor Module With Interconnected Package Portions - A power semiconductor module includes a package having a first package portion and a second package portion. The side of the first package portion facing the second package portion has an anchoring element with a first recess. The second package portion includes a second recess with an indentation which receives the anchoring element. To produce a mechanically firm connection between the first package portion and the second package portion, a plug-in element is inserted in the first recess and the second recess. The plug-in element displaces the anchoring element transversely with respect to the plug-in direction, causing the anchoring element to engage the indentation so that a form-fit connection is produced between the first package portion and the second package portion. The plug-in element prevents the anchoring element from disengaging the indentation. | 07-21-2011 |
| 20110175174 | Methods of Manufacturing Resistors and Structures Thereof - A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material. | 07-21-2011 |
| 20110173804 | Method for Producing a Housing Part for a Power Semiconductor Module and Method for Producing a Power Semiconductor Module - A method for producing a housing part for a power semiconductor module includes providing a connecting lug having a lower end with a foot region, providing a housing having a side wall with a lead-in bevel, and inserting the connecting lug into the lead-in bevel so that the foot region projects inward into an interior of the housing. The method further includes encapsulating at least a portion of the foot region of the connecting lug inserted into the lead-in bevel with a first plastic to produce a positively locking first connection between the connecting lug and the side wall. | 07-21-2011 |
| 20110173508 | RADIO RECEIVER AND METHOD FOR CHANNEL ESTIMATION - A radio receiver includes an input terminal to receive a first radio signal, an equalizer, coupled to the input terminal, to equalize the first radio signal and to output an equalized signal and a first channel estimator, coupled to the input terminal and the equalizer, to estimate first channel parameters by using the first radio signal and a signal derived from the equalized signal. The radio receiver may contain a controller implementing a HARQ protocol and a HARQ buffer to store likelihood information based on the equalized signal. The radio receiver may contain a reconstruction unit to provide the signal derived from the equalized signal based on a content of the HARQ buffer. | 07-14-2011 |
| 20110169564 | Integrated Circuit - An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down. | 07-14-2011 |
| 20110169555 | Mitigating Side Effects Of Impedance Transformation Circuits - The present disclosure relates to mitigating side effects of impedance transformation circuits. | 07-14-2011 |
| 20110165755 | Semiconductor Component Arrangement Comprising a Trench Transistor - Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps. | 07-07-2011 |
| 20110163737 | Tire Pressure Measurement System with Reduced Current Consumption - A tire pressure measurement system (TPMS) includes a capacitor and an integrated circuit configured to receive a supply voltage. The integrated circuit includes a voltage regulator and a measurement unit. The voltage regulator is configured to be turned on and off for predetermined periods of time such that the capacitor is charged and discharged, respectively. The voltage regulator and the capacitor are connected to the measurement unit in order to selectively provide electric charge at a voltage between predetermined upper and lower limits. | 07-07-2011 |
| 20110163598 | Method and Apparatus for Controlling a Supply Current for a Circuit or a Plurality of Circuit Blocks - A method for controlling a supply current for a circuit includes setting a target value of a quantity related to a supply current, said target value being different from a presently established value of the quantity, and adjusting the quantity until a value of the quantity corresponds to the target value. A method for controlling a supply current to a plurality of circuit blocks includes providing a plurality of partial supply currents to the plurality of circuit blocks, setting at least one target value of a quantity related to at least one of the partial supply currents, checking whether a predetermined condition which depends on the at least one set target value is achieved, and if the predetermined condition is not achieved, changing at least one among the at least one target values and the at least one partial supply currents to achieve the predetermined condition. | 07-07-2011 |
| 20110163440 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a carrier and attaching a plurality of semiconductor chips to the carrier. The semiconductor chips have a first electrode pad on a first main face and at least a second electrode pad on a second main face opposite to the first main face, whereby the first electrode pad is electrically connected to the carrier. A plurality of first bumps are formed on the carrier, the first bumps being made of a conductive material. The carrier is then singulated into a plurality of semiconductor devices, wherein each semiconductor device includes at least one semiconductor chip and one first bump. | 07-07-2011 |
