| INFINEON TECHNOLOGIES AG Patent applications |
| Patent application number | Title | Published |
|---|
| 20120036483 | DEVICE, METHOD FOR DISPLAYING A CHANGE FROM A FIRST PICTURE TO A SECOND PICTURE ON A DISPLAY, AND COMPUTER PROGRAM PRODUCT - A device is described having a memory storing data specifying a change animation between pictures to be displayed successively on the display, a setting circuit configured to store a setting specifying that a change animation between pictures to be displayed successively on the display is to be carried out in accordance with the specification of the change animation given by the data, a display controller configured to control a display to display a first picture, a detector configured to detect an event which triggers that a second picture is to be displayed on the display, a determination circuit configured to read the setting and to determine, based on the setting, a change animation between the first picture and the second picture, wherein the display controller is configured to control the display to display the change animation, and, after the change animation, to display the second picture. | 02-09-2012 |
| 20120033621 | COMMUNICATION DEVICES, METHOD FOR DATA COMMUNICATION, AND COMPUTER PROGRAM PRODUCT - A communication device is described comprising a transceiver, a determining circuit configured to determine whether the communication device may use radio resources, which are allocated to be used by a wireless bidirectional communication system in the geographical region in which the communication device is located, for radio data communication without participation by the wireless bidirectional communication system, and a controller configured to control the transceiver to carry out radio data communication using the radio resources if the communication device may use the radio resources. | 02-09-2012 |
| 20120033453 | Controller for a Resonant Switched-Mode Power Converter - In accordance with an embodiment, a switch controller for a switched-mode power supply includes an oscillator, an advance timing generator, and a dead zone generator. The advance timing generator generates an advance timing output pulse having a first pulse width that is asserted when the oscillator reaches a first phase. The dead zone generator produces a dead zone output having a second pulse width when the advance timing output pulse is de-asserted. This dead zone output pulse is coupled to a freeze input of the oscillator that freezes the phase accumulation of the oscillator when asserted. The controller also has a primary switch logic circuit that produces primary switch drive signals having a dead zone coincident with the dead zone output, and a secondary switch logic circuit that generates a secondary switch drive signal that is de-asserted when the advance timing output pulse becomes asserted. | 02-09-2012 |
| 20120032295 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SUCH A DEVICE - A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature. | 02-09-2012 |
| 20120032255 | INTEGRATED CIRCUIT HAVING COMPENSATION COMPONENT - An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed. | 02-09-2012 |
| 20120030531 | Safe Memory Storage By Internal Operation Verification - The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous. | 02-02-2012 |
| 20120028638 | RADIO COMMUNICATION DEVICES, INFORMATION PROVIDERS, METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE AND METHODS FOR CONTROLLING AN INFORMATION PROVIDER - In an embodiment, a radio communication device may be provided. The radio communication device may include a first receiver configured to receive from a first cell first data representing a content encoded using a first codec; a second receiver configured to receive from a second cell second data representing the content encoded using a second codec; and a combiner configured to combine the first data and the second data. | 02-02-2012 |
| 20120028382 | SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP, AND METHOD FOR THE PRODUCTION THEREOF - A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer. | 02-02-2012 |
| 20120027928 | ELECTRONIC DEVICE - An electronic device is disclosed. One embodiment provides a metallic body. A first electrically insulating layer is applied over the metallic body and having a thickness of less than 100 μm. A first thermally conductive layer is applied over the first electrically insulating layer and having a thermal conductivity of more than 50 W/(m·K). A second electrically insulating layer is applied over the first thermally conductive layer and having a thickness of less than 100 μm. | 02-02-2012 |
| 20120026793 | Nonvolatile Memory Cell With Extended Well - One embodiment relates to a memory device. The memory device includes a capacitor having a first capacitor plate and a second capacitor plate, wherein the first and second capacitor plates are separated by an insulating layer and are formed over a first portion of a semiconductor substrate. The memory device also includes a transistor having a source region, a drain region, and a gate region, where the gate region is coupled to the second capacitor plate. The transistor is formed over a second portion of the semiconductor substrate. A well region is disposed in the first and second portions of the semiconductor substrate and has a doping-type that is opposite a doping-type of the semiconductor substrate. Other embodiments are also disclosed. | 02-02-2012 |
| 20120026781 | RESISTIVE MEMORY AND METHOD - A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. | 02-02-2012 |
| 20120025808 | OFF-CENTER ANGLE MEASUREMENT SYSTEM - A method for measuring an angular position of a rotating shaft, the method including providing a magnetic field which rotates with the shaft about an axis of rotation, positioning an integrated circuit having first and second magnetic sensing bridges within the magnetic field at a radially off-center position from the axis of rotation, the first and second magnetic sensing bridges respectively providing first and second signals representative of first and second magnetic field directions, the integrated circuit having a set of adjustment parameters for modifying attributes of the first and second signals, modifying values of the set of adjustment parameters until errors in the first and second signals are substantially minimized, and determining an angular position of the shaft based on the first and second signals. | 02-02-2012 |
| 20120025393 | Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module - A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug. | 02-02-2012 |
| 20120025384 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 02-02-2012 |
| 20120025382 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 02-02-2012 |
| 20120025325 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 02-02-2012 |
| 20120020145 | Identification Circuit and Method for Generating an Identification Bit - A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another. | 01-26-2012 |
| 20120013884 | Metrology Systems and Methods for Lithography Processes - Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask. | 01-19-2012 |
| 20120012924 | Vertical Transistor Component - A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface. | 01-19-2012 |
| 20120008715 | Digital Phase Feedback for Determining Phase Distortion - A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information. | 01-12-2012 |
| 20120007176 | High-Voltage Bipolar Transistor with Trench Field Plate - A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate. | 01-12-2012 |
| 20120002333 | ESD Clamp Adjustment - Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses. | 01-05-2012 |
| 20110318883 | POWER SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF - A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided. | 12-29-2011 |
| 20110316160 | Semiconductor Arrangement, Semiconductor Module, and Method for Connecting a Semiconductor Chip to a Ceramic Substrate - A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least | 12-29-2011 |
| 20110312328 | COMMUNICATION TERMINAL, COMMUNICATION DEVICE, METHOD FOR DATA COMMUNICATION, AND METHOD FOR FREQUENCY ALLOCATION - A communication terminal is described comprising a determiner configured to determine, for a frequency region, a plurality of first communication devices from which the communication terminal receives a signal via the frequency region; a selector configured to select at least one of the first communication devices based on a predetermined interference criterion; a signal generator configured to generate a signal with an identification of the at least one selected first communication device; and a transceiver configured to transmit the signal to a second communication device, to receive an indication from the second communication device specifying whether the communication terminal should use the frequency region for data communication with the second communication device, and to carry out data communication with the second communication device using the frequency region depending on the indication. | 12-22-2011 |
| 20110312274 | RADIO COMMUNICATION DEVICE, RECEIVER CONTROLLER OF A RADIO COMMUNICATION DEVICE, METHODS FOR SEARCHING FOR A RADIO CELL - Embodiments relate generally to a radio communication device, to a receiver controller of a radio communication device, and to a method for searching for a radio cell. In an embodiment, a method for searching for a radio cell is provided. The method may include scanning at least one frequency band of a first radio access technology, scanning at least one frequency band of a second radio access technology, wherein the at least one frequency band of the second radio access technology at least partially overlaps with the at least one frequency band of the first radio access technology, wherein at least one frequency sub-band of the first radio access technology is not scanned in the at least one frequency band of the second radio access technology. | 12-22-2011 |
| 20110310988 | Communication Methods and Apparatuses - Communication methods and apparatuses are provided. | 12-22-2011 |
| 20110310674 | System and Method for Bit-Line Control - In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor. | 12-22-2011 |
| 20110310568 | Circuit Arrangement with Shunt Resistor - A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction. | 12-22-2011 |
| 20110309814 | USE OF AUXILIARY CURRENTS FOR VOLTAGE REGULATION - One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator. | 12-22-2011 |
| 20110309810 | Electronic Circuit and Semiconductor Arrangement With a Load, a Sense and a Start-Up Transistor - Disclosed is an electronic circuit with a first load terminal, a second load terminal, a supply terminal configured for having a charge storage arrangement connected thereto, and a load transistor, a current sense circuit with a sense transistor, and a start-up circuit with a start-up transistor. | 12-22-2011 |
| 20110309441 | INTEGRATED SEMICONDUCTOR DEVICE HAVING AN INSULATING STRUCTURE AND A MANUFACTURING METHOD - An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided. | 12-22-2011 |
| 20110309423 | SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING - A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension. | 12-22-2011 |
| 20110308866 | Sensor Measurement System Using Pulsed Current Signals - The disclosed invention provides a structure and method for easily measuring capacitive and/or resistive components of a sensor system. In one embodiment, the structure comprises a signal generator configured to output a load current to a measurement element containing measurement sensor elements and a parasitic capacitance. A controllable excitation voltage is generated, via integration of the load current on the parasitic capacitance, and output to the measurement sensor elements having capacitive and resistive components. The controlled voltage through the measurement device may be manipulated to cause the capacitive and resistive components to exhibit a transient effect. The resulting output current, provided from the measurement device therefore has transient response characteristics (e.g., the settling time, amplitude) that can be selectively measured by a measurement circuit to easily determine values of the capacitive and resistive measurement elements. Furthermore, dedicated demodulation techniques may be used to measure the capacitive and resistive components. | 12-22-2011 |
| 20110305284 | Method for Transmitting a Data Signal in a MIMO System - A method for transmitting a data signal by a transmission unit of a wireless multiple-input/multiple-output (MIMO) communication system. The communication system includes the transmission unit and a reception unit, the transmission unit having a plurality of transmission antennas and the reception unit having a plurality of reception antennas. The method includes performing a first transmission of a data signal, the first transmission including transmitting the data signal by each one of the plurality of transmission antennas, and performing a second transmission of the data signal at a time later than the first transmission, the second transmission including transmitting at least one spectrally modified signal variant of the data signal by at least one antenna of the plurality of transmission antennas. | 12-15-2011 |
| 20110304940 | Protection Circuit - A protection circuit includes a controllable discharge element having a load path coupled between a first second circuit nodes. The discharge element provides a discharge path between the first and the second circuit nodes when in an on state. A trigger circuit has a first connection coupled to the first circuit node and a second connections coupled to the second circuit node. The trigger circuit is configured to produce a drive signal that switches the discharge element to its on state when the voltage between the first and the second circuit nodes reaches a trigger value. A setting circuit coupled to the trigger circuit is configured to change the trigger value from a first trigger value to a second trigger value depending on a voltage between the first and the second circuit nodes and/or on the drive signal. | 12-15-2011 |
| 20110304487 | FLOATING POINT TIMER TECHNIQUES - Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications. | 12-15-2011 |
| 20110304047 | Method for Producing a Composite Material, Associated Composite Material and Associated Semiconductor Circuit Arrangements - A method for producing a composite material, associated composite material and associated semiconductor circuit arrangements is disclosed. A plurality of first electrically conducting material particles are applied to a carrier substrate and a second electrically conducting material is galvanically deposited on a surface of the first material particles in such a way that the second material mechanically and electrically bonds the plurality of first material particles to one another. | 12-15-2011 |
| 20110303948 | ESD and EMC optimized HV-MOS Transistor - Devices and circuits related to Electrostatic discharge (ESD) and Electromagnetic compatibility (EMC) are herein described. An ESD protection device is incorporated into a transistor in order to protect the gate of the transistor from excessive current loads related to ESD or EMC events. In an implementation, a device includes a first diode and a second diode that are electrically connected via their respective cathodes. The breakdown voltage of the first diode is lower than the breakdown voltage of the second diode in order to divert excessive current through the second diode. | 12-15-2011 |
| 20110300864 | MOBILE RADIO COMMUNICATION SYSTEM - A mobile radio communication system having a mobile radio communication network and a mobile radio subscriber appliance, wherein a unit in the network layer of the core network of the mobile radio communication network is configured to transmit to the mobile radio subscriber appliance a first message, based on an occurrence of a predetermined event, with a request for a statement which describes at least one radio characteristic of the mobile radio subscriber appliance. | 12-08-2011 |
| 20110298454 | Current Sensor - A current sensor includes a conductive element, at least two magnetic field sensors arranged on the conductive element and adapted to sense a magnetic field generated by a current through the conductor element. The at least two magnetic field sensors are arranged on opposite sides of a line perpendicular to a current flow direction in the conductive element, an insulating layer is arranged between the conductive element and the magnetic field sensors, and a conductor trace is connected to the magnetic field sensors. | 12-08-2011 |
| 20110298085 | SHALLOW TRENCH ISOLATION AREA HAVING BURIED CAPACITOR - A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area. | 12-08-2011 |
| 20110294451 | RECEIVER - A receiver includes an input to receive data of a pilot channel having a carrier frequency associated therewith, and a first unit to obtain a quantity, wherein the quantity depends on a frequency broadening of the received data and a frequency shift of the received data with respect to the carrier frequency. The receiver also includes a second unit to adjust the bandwidth of a channel estimation unit, wherein the adjustment depends on the quantity. | 12-01-2011 |
| 20110294238 | SEMICONDUCTOR WAFER WITH ELECTRICALLY CONNECTED CONTACT AND TEST AREAS - The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit. | 12-01-2011 |
| 20110291274 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips. | 12-01-2011 |
| 20110289377 | SYSTEMS AND METHODS FOR SECURE INTERRUPT HANDLING - The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. | 11-24-2011 |
| 20110285033 | Chip Carrier - Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location. | 11-24-2011 |
| 20110285030 | METHOD FOR PRODUCING CHIP PACKAGES, AND CHIP PACKAGE PRODUCED IN THIS WAY - A method for producing chip packages is disclosed. In one embodiment, a plurality of chips is provided. The chips each have first pads. Second connection pads are applied on the wafer, wherein each second pad is electrically connected to a first pad. | 11-24-2011 |
| 20110284970 | Transistor Device and Methods of Manufacture Thereof - Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor. | 11-24-2011 |
| 20110281405 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip. | 11-17-2011 |
| 20110278730 | Semiconductor Devices and Structures Thereof - A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region. | 11-17-2011 |
| 20110278680 | Strained Semiconductor Device and Method of Making the Same - In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess. | 11-17-2011 |
| 20110270553 | Apparatus, Sensor Circuit, and Method for Operating an Apparatus or a Sensor Circuit - An apparatus is described, including: a signal processing circuit adapted to process an input signal to obtain an output signal; a sensor element for sensing a predetermined physical quantity, wherein the sensor element is adapted to generate a sensor signal in response to the predetermined physical quantity; wherein the signal processing unit is adapted to process the input signal to obtain the output signal depending on the sensor signal; and wherein the apparatus further comprises an evaluation circuit adapted to evaluate the sensor signal and to generate an indication signal indicating an abnormal operating condition in case the sensor signal does not fulfill a predetermined normal operation criterion. | 11-03-2011 |
| 20110269447 | MOBILE RADIO COMMUNICATION NETWORK DEVICE, MOBILE TERMINAL, AND METHOD FOR TRANSMISSION/RECEPTION OF CONTROL INFORMATION - A mobile radio communication network device is descried including a receiver configured to receive control information from a mobile terminal, wherein the receiver is configured to receive the control information in a first mode or in a second mode, wherein in the second mode, less of the control information is received in time from the mobile terminal than in the first mode, and a controller configured to control the receiver to receive the control information in the first mode if the mobile terminal is associated with a first mobile terminal mobility class and to control the receiver to receive the information in the second mode if the mobile terminal is associated with a second mobile terminal mobility class. | 11-03-2011 |
| 20110269073 | METHOD FOR APPLYING A RESIST LAYER, USES OF ADHESIVE MATERIALS, AND ADHESIVE MATERIALS AND RESIST LAYER - A method in which a resist layer is applied to a base layer is disclosed. The resist layer includes an adhesive material, and the adhesive force of the adhesive material decreases or increases during an irradiation process. Residues of the resist layer may be stripped using the disclosed method. | 11-03-2011 |
| 20110268046 | COMMUNICATION NETWORK DEVICE, COMMUNICATION TERMINAL, AND COMMUNICATION RESOURCE ALLOCATION METHODS - A communication network device of a communication system is described comprising a transmitter configured to transmit data in a plurality of frames, wherein in each frame, a plurality of communication resource elements is provided to be allocated for data transmission of downlink control data, wherein a data communication resource element is defined by a frequency range and a communication time interval within the frame and a communication resource allocator configured to allocate a first set of the communication resource elements of the plurality of communication resource elements provided to be allocated for data reception of downlink control data in a frame for the transmission of the downlink control data and to allocate a second set of the communication resource elements of the plurality of communication resource elements provided to be allocated for data reception of downlink control data in the frame that have not been allocated for the transmission of downlink control data for the transmission of data of another type than the downlink control data. | 11-03-2011 |
| 20110261542 | DIE PACKAGE - In an embodiment, a die package may be provided. The die package may include at least one first height adjusting structure, the at least one first height adjusting structure may include a first adjusting height relative to a common plane; at least one second height adjusting structure may be positioned adjacent to the at least one first height adjusting structure, the at least one second height adjusting structure may include a second adjusting height relative to the common plane; wherein the second adjusting height may be different from the first adjusting height relative to the common plane; a first die may be positioned on the at least one first height adjusting structure; and a mold housing substantially surrounding the at least one first height adjusting structure, the at least one second height adjusting structure and the first die. | 10-27-2011 |
| 20110260307 | INTEGRATED CIRCUIT INCLUDING BOND WIRE DIRECTLY BONDED TO PAD - An integrated circuit includes a chip including a copper bond pad metallization, and a copper bond wire including a copper ball. The copper ball is bonded directly to the copper bond pad. | 10-27-2011 |
| 20110260302 | SHIELDING DEVICE - One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit. | 10-27-2011 |
| 20110258844 | METHOD OF MANUFACTURING A POWER TRANSISTOR MODULE AND PACKAGE WITH INTEGRATED BUS BAR - According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections. | 10-27-2011 |
| 20110256749 | Press-Fit Connections for Electronic Modules - A press-fit connecting element for being pressed into a first contact opening in a first connection element and into a second contact opening in a second connection element is provided. The press-fit connecting element includes an elongated base body configured to be guided through the second contact opening in the second connection element to the first contact opening in the first connection element. The press-fit connecting element further includes a first press-fit zone configured to contact-connect the first contact opening in a force-fitting manner and a second press-fit zone which is at a distance from the first press-fit zone in a longitudinal direction and configured to contact-connect the second contact opening in a force-fitting manner. | 10-20-2011 |
| 20110256688 | SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench. | 10-20-2011 |
| 20110254589 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements. | 10-20-2011 |
| 20110254018 | Semiconductor Switching Arrangement Having a Normally on and a Normally off Transistor - A semiconductor switching arrangement includes a normally on semiconductor component of a first conduction type and a normally off semiconductor component of a second conduction type which is the complement of the first conduction type. A load path of the normally off semiconductor component is connected in series with the load path of the normally on semiconductor component. A first actuation circuit connected between the control connection of the normally on semiconductor component and a load path connection of the normally on semiconductor component. The load path connection of the normally on semiconductor component is arranged between the normally on and normally off semiconductor components. A second actuation circuit is connected between the control connection of the normally off semiconductor component and a load path connection of the normally off semiconductor component. The load path connection of the normally off semiconductor component is arranged between the normally on and normally off semiconductor components. | 10-20-2011 |
| 20110250856 | Direct FM/PM Modulation - Representative implementations of direct FM/PM modulation and systems are disclosed describing frequency modulation or phase modulation of information onto a carrier signal using a divider that is remote from the carrier signal generation path. | 10-13-2011 |
| 20110250740 | METHOD AND DEVICE FOR THE TREATMENT OF A SEMICONDUCTOR SUBSTRATE - Method for the treatment of a semiconductor substrate ( | 10-13-2011 |
| 20110250530 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced. | 10-13-2011 |
| 20110248792 | CIRCUIT ARRANGEMENT WITH IMPROVED DECOUPLING - A circuit arrangement includes a component having a closed signal path, that closed signal path connected to a first port, a second port and at least a third port. The component has a directed signal flow of a signal applied to one of that ports. Such a coupling device can be connected to a transmitter and to a receiver path, respectively. | 10-13-2011 |
| 20110248753 | Suppression of Low-Frequency Noise from Phase Detector in Phase Control Loop - The disclosed invention provides a structure and method for improving performance of a phase locked loop by suppressing low-frequency noise produced by a phase detector. This is achieved by up-conversion of the in-band frequency components in the phase difference between reference signal and feedback signal to a higher frequency range where noise performance of a phase detector is improved. The up-converted phase difference is provided to a phase detector that is configured to determine an error signal based upon this phase difference. The error signal is output to a down-converter configured to down-convert the error signal (e.g., back to the original frequency range), thereby intrinsically up-converting the error signal's low-frequency noise (produced by the phase detector), prior to being provided to a filter configured to filter the up-converted noise, thereby resulting in an improved PLL noise performance. | 10-13-2011 |
| 20110248711 | MAGNETIC FIELD CURRENT SENSORS - Current sensors, conductors and methods are disclosed. A magnetic current sensor includes a conductor including a first sheet metal layer having a first thickness and including at least one notch extending inwardly from a first edge of the first sheet metal layer, and a second sheet metal layer having a second thickness less than the first thickness and including at least one notch, the second sheet metal layer being coupled to the first sheet metal layer such that the at least one notch of the first sheet metal layer is generally aligned with the at least one notch of the second sheet metal layer; and an integrated circuit (IC) die including at least one magnetic sensor element and being coupled to the conductor such that the at least one magnetic sensor element is generally aligned with a tip of the at least one notch of the second sheet metal layer. | 10-13-2011 |
| 20110248234 | VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer. | 10-13-2011 |
| 20110244811 | Demodulator and Method for Demodulating a Modulated Carrier Signal - A demodulator includes a sampler configured to sample a plurality of first amplitude values of a modulated carrier signal using a constant sampling frequency and a plurality of second amplitude values of the modulated carrier signal at different times using the same constant sampling frequency. The constant sampling frequency is equal to a carrier frequency of the modulated carrier signal with a tolerance of +/−1% of the carrier frequency. | 10-06-2011 |
| 20110243261 | COMMUNICATION DEVICE - According to one embodiment, a communication device is described comprising a communication circuit configured to communicate in a first communication mode using a first frequency range and a receiver configured to receive a switching delay information message indicating a time interval by which start of communication in a second communication mode using a second frequency range should be delayed after a switch from the first communication mode to the second communication mode. The communication circuit is configured to communicate in the second communication mode when the time interval has elapsed since the start of the switching from the first communication mode to the second communication mode. | 10-06-2011 |
| 20110243200 | Demodulator and Method for Demodulating a Carrier Signal - A demodulator includes a sampler and a trigger unit. The sampler is configured to sample a carrier signal based on a trigger signal to obtain a demodulated signal. The trigger unit is configured to detect a zero crossing of the carrier signal or an extreme value of an amplitude of the carrier signal. Further, the trigger unit is configured to provide the trigger signal based on the detected zero crossing or the detected extreme value, so that the carrier signal is sampled by the sampler with a predefined phase shift to the detected zero crossing or the detected extreme value. The predefined phase shift is larger than 30° plus an integer multiple of 90° and lower than 60° plus the same integer multiple of 90° in reference to the carrier signal. | 10-06-2011 |
| 20110234472 | Integrated Circuit Package Assembly Including Wave Guide - Some embodiments herein relate to a transmitter. The transmitter includes an integrated circuit (IC) package including a first antenna configured to radiate a first electromagnetic signal therefrom. A printed circuit board (PCB) substrate includes a waveguide configured to receive the first electromagnetic signal and to generate a waveguide signal based thereon. A second antenna can be electrically coupled to the waveguide and can radiate a second electromagnetic signal that corresponds to the waveguide signal. Other devices and methods are also disclosed. | 09-29-2011 |
| 20110234215 | Sensor Package and Method for Producing a Sensor Package - Some embodiments herein relate to a sensor package. The sensor package includes a printed circuit board with a laminar current conductor arranged on a first main surface of the printed circuit board. The sensor package also includes a sensor chip adapted to measure a current flowing through the laminar current conductor, wherein the sensor chip comprises a magnetic field sensor. The sensor chip is electrically insulated from the current conductor by the printed circuit board, and is arranged on a second main surface of the printed circuit board opposite to the first main surface. The sensor chip is hermetically sealed between the mold material and the printed circuit board, or is arranged in the printed circuit board and hermetically sealed by the printed circuit board. | 09-29-2011 |
| 20110233721 | SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench. | 09-29-2011 |
| 20110233630 | INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR SUBSTRATE WITH BARRIER LAYER - An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element. | 09-29-2011 |
| 20110231718 | MEMORY REPAIR - A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime. | 09-22-2011 |
| 20110227204 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. An encapsulating body encapsulates the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. At least one of the second conducting element, third conducting element, and fourth conducting element extend over the semiconductor chip and the encapsulating body. | 09-22-2011 |
| 20110216561 | Low-Inductance Power Semiconductor Assembly - A power semiconductor assembly includes at least two bridge branches each including at least two circuit breakers connected to a phase output. Each of the circuit breakers has at least two parallel-connected switching elements integrated into a semiconductor chip. Each of the circuit breakers is arranged in a power semiconductor module and the individual power semiconductor modules are arranged adjacent to one another in a first direction. The semiconductor chips of a particular circuit breaker are arranged adjacent to one another in the corresponding power semiconductor module in a second direction extending perpendicular to the first direction. | 09-08-2011 |
| 20110215955 | SYSTEM INCLUDING FEEDBACK CIRCUIT WITH DIGITAL CHOPPING CIRCUIT - A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The chopping circuit is configured to receive the digital output signals and provide error signals that represent ripple error in the digital output signals. The integrator circuit is configured to accumulate the error signals and provide an accumulated error signal. The digital to analog converter circuit is configured to convert the accumulated error signal into an analog signal that is received by the second circuit to reduce the ripple error. | 09-08-2011 |
| 20110215460 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane. | 09-08-2011 |
| 20110215158 | Passive RFID Transponder and RFID Reader - A passive RFID transponder includes a coder and a modulator. The coder generates a digital coded data stream based on a digital data stream to be transmitted. The digital coded data stream includes an initialization bit sequence having a maximum data frequency of the digital coded data stream. Furthermore, the digital coded data stream changes its value at the latest after a predefined number of bits. The modulator modulates an amplitude of a carrier signal with the digital coded data stream to provide an amplitude-modulated coded signal. | 09-08-2011 |
| 20110211552 | COMPUTED-AIDED MAPPING OF SYSTEM INFORMATION MEDIUM ACCESS CONTROL PROTOCOL MESSAGES - A method for computer-aided mapping of system information medium access control protocol messages onto a plurality of transport channels for transmission using an orthogonal frequency division multiple access method, wherein a scheduling of system information data packets information in the context of the mapping on a transport channel of the plurality of transport channels is carried out dependent on the type of the system information. | 09-01-2011 |
| 20110210840 | POSITION IDENTIFICATION SYSTEM AND METHOD - A position identification system and method include a receiver configured to receive an initiation signal and attenuate the initiation signal until the initiation signal is within a first predetermined range of a reference signal. A controller identifies the position of the receiver in response to the attenuation. | 09-01-2011 |
| 20110210798 | Ring Oscillator for Providing Constant Oscillation Frequency - Some embodiments disclosed herein relate to techniques for providing a relatively constant oscillation frequency. In some instances, these techniques can make use of a ring oscillator that is powered by an adaptive voltage supply. The adaptive voltage supply provides a temperature-dependent supply voltage to respective delay elements in the ring oscillator, such that the oscillation frequency of the ring oscillator is approximately constant over a predetermined temperature range. For example, if temperature increases, the supply voltage can be increased proportionally, thereby tending to limit variation in the oscillation frequency delivered by the ring oscillator. | 09-01-2011 |
| 20110210782 | Integrated Circuit with a Radiation-Sensitive Thyristor Structure - An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data. | 09-01-2011 |
| 20110209556 | STRESS SENSING DEVICES AND METHODS - Embodiments relate to stress sensing devices and methods. In an embodiment, a sensor device includes an active layer; and at least three contacts spaced apart from one another in the active layer, the at least three contacts being coupleable in a first configuration for a first operating mode of the sensor device in which a current in the active layer has a first ratio of horizontal to vertical components with respect to a die surface and in a second configuration different from the first for a second operating mode of the sensor device in which a current in the active layer has a second ratio of horizontal to vertical components, wherein a ratio of a resistance between at least two of the contacts in the first operating mode and a resistance between at least two of the contacts in the second operating mode is related to mechanical stress in the sensor device. | 09-01-2011 |
| 20110208948 | READING TO AND WRITING FROM PERIPHERALS WITH TEMPORALLY SEPARATED REDUNDANT PROCESSOR EXECUTION - Embodiments relate to systems and methods for reading from and writing to interface peripherals or other shared resources during robust computation utilizing temporally separated redundant execution. Embodiments can be utilized in safety-relevant applications related to automotive, banking and finance, aerospace, defense, Internet payment, and others. | 08-25-2011 |
| 20110206171 | Interference Suppression Processing Unit and a Method of Suppressing Interference in Wireless Data Communication - An interference suppression processing unit includes at least one receive path, wherein each of the at least one receive path is configured to transmit one of at least one received data sequence received from at least one antenna port, a signal generation unit configured to generate at least one signal data sequence from the at least one received data sequence, at least one signal path, wherein each of the at least one signal path is configured to transmit one of the at least one signal data sequence, at least one prefilter unit, wherein each of the at least one prefilter unit is coupled to one of the at least one signal path and a combiner including at least one input terminal, wherein each of the at least one input terminal is connected to an output terminal of one of the at least one prefilter unit, wherein the signal generation unit is configured to generate K1 first signal data sequences, wherein each first signal data sequence is identical to one of the at least one received data sequence, respectively, and K2 second signal data sequences, wherein each second signal data sequence is not identical to one of the at least one received data sequence, respectively, and wherein the number of the first signal data sequences and the second signal data sequences (K1+K2) equals the number of the at least one signal data sequence. | 08-25-2011 |
| 20110204887 | CURRENT SENSORS AND METHODS - Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a conductor portion having a first portion and a second portion; at least three slots formed in the conductor portion between the first and second portions, each of the at least three slots having a length and at least one tip portion; at least two bridge portions each having a width separating two of the at least three slots and a length coupling the first and second portions; a first contact region disposed relative to the first portion and a second contact region disposed relative to the second portion; and at least one pair of magnetic sensor elements, a first pair of magnetic sensor elements arranged relative to and spaced apart from a first of the at least two bridge portions. | 08-25-2011 |
| 20110201186 | METHOD AND APPARATUS FOR REDUCING FLICKER NOISE IN A SEMICONDUCTOR DEVICE - Some embodiments discussed relate to an integrated circuit and methods for making it. In an example, a method can include providing a semiconductor wafer including a fin, and introducing a noise-reducing dopant into a sidewall of the fin. | 08-18-2011 |
| 20110200075 | Device and Method for Selecting a Path from an Estimated Delay Profile of a Radio Signal - A device includes a delay profile estimator to estimate a delay profile of multiple paths of a radio signal, wherein the delay profile indicates signal powers of the multiple paths as a function of time delay. The device further includes a path selector to select a path from the delay profile if the path has a signal power higher than a threshold. The threshold has a first threshold value in a first section of the delay profile which is higher than a second threshold value in a second section of the delay profile. | 08-18-2011 |
| 20110199132 | SYSTEM PROVIDING A SWITCHED OUTPUT SIGNAL AND A HIGH RESOLUTION OUTPUT SIGNAL - A system including a sensing system, a first chopped circuit, a second chopped circuit, and a clock generator. The sensing system is configured to provide sensed input signals. The first chopped circuit is configured to provide a switched output signal that switches in response to values of the sensed input signals crossing a limit. The second chopped circuit is configured to provide a high resolution output signal that corresponds to the sensed input signals and has a higher resolution than the switched output signal. The clock generator is configured to provide clock signals that synchronize chopping of the first chopped circuit and the second chopped circuit. | 08-18-2011 |
| 20110195682 | DIVERSITY RECEIVER - A diversity receiver includes a plurality of receiver circuits that are configured to receive and process the received radio frequency signals. A channel estimator is coupled to at least one of the plurality of receiver circuits and is configured to determine at least one channel estimation value for the received radio frequency signals. A controller is coupled to the channel estimator and to at least one of the plurality of receiver circuits and is configured to selectively activate or deactivate the at least one of the plurality of receiver circuits based on the determined at least one channel estimation value. | 08-11-2011 |
| 20110194364 | NVM OVERLAPPING WRITE METHOD - The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). Specifically, the write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit. This interleaving of data bit write windows allows a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) reducing overall memory write time. | 08-11-2011 |
| 20110193557 | CURRENT SENSOR INCLUDING A SINTERED METAL LAYER - An integrated circuit includes a semiconductor die including a first magnetic field sensor. The integrated circuit includes an isolation material layer over the first magnetic field sensor and a sintered metal layer over the isolation material layer. The first magnetic field sensor is configured to sense a magnetic field generated by a current passing through the sintered metal layer. | 08-11-2011 |
| 20110191658 | Method and Apparatus for Storing Data - When coding user data, it may be desirable to mark user data as invalid. This may arise, by way of example, in applications in which a stored data item needs to be updated by virtue of an updated data item additionally being stored and the old stored data item being marked as invalid. In order to mark the invalidity of a stored data item by means of the value of the data item and to be able to apply an error-recognizing or error-correcting coding dependably, the user data are extended by supplementary data and the coding is applied to the extended user data. | 08-04-2011 |
| 20110190011 | RADIO BASE STATIONS, RADIO COMMUNICATION DEVICES, METHODS FOR CONTROLLING A RADIO BASE STATION, AND METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE - In various embodiments, a radio base station may be provided. The radio base station may include a transceiver configured to communicate with a radio communication device using a plurality of component carriers; and a message generator configured to generate an idle mode message including an information item related to at least one of the component carriers of the plurality of component carriers of the radio base station. The transceiver may further be configured to transmit the generated idle mode message to the radio communication device. | 08-04-2011 |
| 20110189999 | METHOD AND APPARATUSES FOR TWO OR MORE NEIGHBORING WIRELESS NETWORK DEVICES ACCESSING A PLURALITY OF RADIO RESOURCES - Methods and apparatuses for two or more neighboring base stations to access a plurality of radio resources are described. The method includes defining a channel quality requirement by one or more access conditions and assigning the plurality of radio resources to the channel quality requirement, wherein a neighboring base station has access to the plurality of radio resources and the neighboring base station neighbors a target base station. The method also includes allowing the target base station access to the plurality of radio resources if the target base station satisfies the channel quality requirement. | 08-04-2011 |
| 20110189969 | Receiver Arrangement with AC Coupling - A receiver arrangement with AC coupling is specified in which a filter arrangement ( | 08-04-2011 |
| 20110189821 | SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer. | 08-04-2011 |
| 20110188604 | Digital Modulator and Digital-to-Analog Conversion Techniques Associated Therewith - Some embodiments disclosed herein relate to a transmitter. The transmitter includes a digital modulator adapted to provide a digital modulated RF signal based on a multi-bit representation of data and a multi-bit representation of a carrier wave. A digital-to-analog converter (DAC) is adapted to generate an analog modulated RF signal based on the digital modulated RF signal. A resonant circuit coupled to an output of the DAC and adapted to filter undesired frequency components from the analog modulated RF signal. | 08-04-2011 |
| 20110188446 | ENABLING IMS SERVICES FOR NON-IMS UEs VIA A HOME BASE STATION SUBSYSTEM - Apparatuses and methods for enabling IMS services for non-IMS UEs via a home base station subsystem are described. In various embodiments, a home base station subsystem includes a message generator configured to generate an Internet Protocol multimedia subscription request message comprising a unique user identifier and an information request message, the information request message requesting an Internet Protocol multimedia subscription for the user identified by the unique user identifier. The home base station subsystem also includes a transmitter configured to transmit the generated Internet Protocol multimedia subscription request message to a user database. | 08-04-2011 |
| 20110187587 | RECEIVER TEST CIRCUITS, SYSTEMS AND METHODS - Embodiments relate to apparatuses, systems and methods for testing high-frequency receivers. In an embodiment, a method includes integrating a pulse train generator and a receiver in an integrated circuit; generating a pulse train by the pulse train generator and applying the pulse train to an input of the receiver; measuring at least one property of the pulse train; and determining at least one characteristic of the receiver using the at least one property of the pulse train. In an embodiment, an integrated circuit includes a receiver, and a pulse train generator configured to generate a pulse train and apply the pulse train to an input of the receiver, wherein at least one characteristic of the receiver can be determined using at least one measured property of the pulse train. | 08-04-2011 |
| 20110187433 | On-Chip Self Calibrating Delay Monitoring Circuitry - The present disclosure relates to on-chip self calibrating delay monitoring circuitry. | 08-04-2011 |
| 20110187350 | Magnetic-Field Sensor and Method of Calibrating a Magnetic-Field Sensor - An embodiment of a magnetic-field sensor has a plurality of sensor elements connected to form measurement arrangements, each measurement arrangement having a measurement tap, and a control circuit formed to perform an embodiment of a method of calibrating the magnetic-field sensor. | 08-04-2011 |
| 20110181459 | SYSTEMS AND METHODS FOR INCIDENT ANGLE MEASUREMENT OF WAVES IMPINGING ON A RECEIVER - Embodiments relate to radar systems and methods. In an embodiment, a system includes a radio frequency (RF) sensor array comprising a plurality of spaced apart sensors; and a reflector element positioned proximate the RF sensor array to reflect waves toward the RF sensor array. In an embodiment, a system includes an antenna array comprising a transceive antenna and a plurality of receive antennas; a mirror arranged proximate the antenna array; a voltage controlled oscillator (VCO) configured to generate a signal to be transmitted by the transceive antenna; and a controller configured to resolve signals received by the plurality of receive antennas to determine an angular position of a target, wherein the signals received include a first portion of the signal reflected by the target and a second portion of the signal reflected by the target and the mirror. | 07-28-2011 |
| 20110176589 | METHODS AND SYSTEMS FOR MEASURING DATA PULSES - Some embodiments disclosed herein relate to a method. In the method, a duration of a first synchronization pulse is measured. A fixed, predetermined number of ticks are equally spaced at a first time interval over the first sync pulse, regardless of the duration of the first synchronization pulse. A duration of a first data pulse is then measured by periodically incrementing a tick count value at the first time interval during the entire duration of the first data pulse. The tick count value at an end of the first data pulse is then correlated to a first digital value encoded on the first data pulse. | 07-21-2011 |
| 20110176561 | TIME-BASED MAINTENANCE VIA A PACKET-ORIENTED DIGITAL INTERFACE IN RADIO-FREQUENCY TRANSMITTING AND RECEIVING ASSEMBLIES - Disclosed herein are techniques, systems, and methods relating maintaining a time base between receiving and transmitting assemblies during interruption of data streams communicated therebetween. | 07-21-2011 |
| 20110175214 | Power Semiconductor Module With Interconnected Package Portions - A power semiconductor module includes a package having a first package portion and a second package portion. The side of the first package portion facing the second package portion has an anchoring element with a first recess. The second package portion includes a second recess with an indentation which receives the anchoring element. To produce a mechanically firm connection between the first package portion and the second package portion, a plug-in element is inserted in the first recess and the second recess. The plug-in element displaces the anchoring element transversely with respect to the plug-in direction, causing the anchoring element to engage the indentation so that a form-fit connection is produced between the first package portion and the second package portion. The plug-in element prevents the anchoring element from disengaging the indentation. | 07-21-2011 |
| 20110175174 | Methods of Manufacturing Resistors and Structures Thereof - A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material. | 07-21-2011 |
| 20110173804 | Method for Producing a Housing Part for a Power Semiconductor Module and Method for Producing a Power Semiconductor Module - A method for producing a housing part for a power semiconductor module includes providing a connecting lug having a lower end with a foot region, providing a housing having a side wall with a lead-in bevel, and inserting the connecting lug into the lead-in bevel so that the foot region projects inward into an interior of the housing. The method further includes encapsulating at least a portion of the foot region of the connecting lug inserted into the lead-in bevel with a first plastic to produce a positively locking first connection between the connecting lug and the side wall. | 07-21-2011 |
| 20110173508 | RADIO RECEIVER AND METHOD FOR CHANNEL ESTIMATION - A radio receiver includes an input terminal to receive a first radio signal, an equalizer, coupled to the input terminal, to equalize the first radio signal and to output an equalized signal and a first channel estimator, coupled to the input terminal and the equalizer, to estimate first channel parameters by using the first radio signal and a signal derived from the equalized signal. The radio receiver may contain a controller implementing a HARQ protocol and a HARQ buffer to store likelihood information based on the equalized signal. The radio receiver may contain a reconstruction unit to provide the signal derived from the equalized signal based on a content of the HARQ buffer. | 07-14-2011 |
| 20110169564 | Integrated Circuit - An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down. | 07-14-2011 |
| 20110169555 | Mitigating Side Effects Of Impedance Transformation Circuits - The present disclosure relates to mitigating side effects of impedance transformation circuits. | 07-14-2011 |
| 20110165755 | Semiconductor Component Arrangement Comprising a Trench Transistor - Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps. | 07-07-2011 |
| 20110163737 | Tire Pressure Measurement System with Reduced Current Consumption - A tire pressure measurement system (TPMS) includes a capacitor and an integrated circuit configured to receive a supply voltage. The integrated circuit includes a voltage regulator and a measurement unit. The voltage regulator is configured to be turned on and off for predetermined periods of time such that the capacitor is charged and discharged, respectively. The voltage regulator and the capacitor are connected to the measurement unit in order to selectively provide electric charge at a voltage between predetermined upper and lower limits. | 07-07-2011 |
| 20110163598 | Method and Apparatus for Controlling a Supply Current for a Circuit or a Plurality of Circuit Blocks - A method for controlling a supply current for a circuit includes setting a target value of a quantity related to a supply current, said target value being different from a presently established value of the quantity, and adjusting the quantity until a value of the quantity corresponds to the target value. A method for controlling a supply current to a plurality of circuit blocks includes providing a plurality of partial supply currents to the plurality of circuit blocks, setting at least one target value of a quantity related to at least one of the partial supply currents, checking whether a predetermined condition which depends on the at least one set target value is achieved, and if the predetermined condition is not achieved, changing at least one among the at least one target values and the at least one partial supply currents to achieve the predetermined condition. | 07-07-2011 |
| 20110163440 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a carrier and attaching a plurality of semiconductor chips to the carrier. The semiconductor chips have a first electrode pad on a first main face and at least a second electrode pad on a second main face opposite to the first main face, whereby the first electrode pad is electrically connected to the carrier. A plurality of first bumps are formed on the carrier, the first bumps being made of a conductive material. The carrier is then singulated into a plurality of semiconductor devices, wherein each semiconductor device includes at least one semiconductor chip and one first bump. | 07-07-2011 |
| 20110163395 | Pressure Sensor and Method - A method for providing a pressure sensor substrate comprises creating a first cavity that extends inside the substrate in a first direction perpendicular to a main surface of the substrate, and that extends inside the substrate, in a second direction perpendicular to the first direction, into a first venting area of the substrate; creating a second cavity that extends in the first direction inside the substrate, that extends in parallel to the first cavity in the second direction, and that does not extend into the first venting area; and opening the first cavity in the first venting area. | 07-07-2011 |
| 20110163366 | Semiconductor Component Arrangement Comprising a Trench Transistor - Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps. | 07-07-2011 |
| 20110161534 | Control Architectures for RF Transceivers - Described herein are devices and methods for implementing a transceiver with independently controlled components. The components may include a programmable digital portion, a dedicated digital portion, and an analog portion. Each independently controlled component includes a programmable controller that resides in the programmable digital portion of the component that controls components in the dedicated digital or analog portions using state transition information. The programmable controller is configured to accommodate a broad spectrum of state transition information and is capable of emulating a plurality of hardwired finite state machines | 06-30-2011 |
| 20110156095 | Semiconductor Component with an Emitter Control Electrode - A semiconductor component includes a first emitter zone of a first conductivity type, a second emitter zone of a second conductivity type, a first base zone arranged between the first and second emitter zones and a first control structure. The first control structure includes a control electrode arranged adjacent the first emitter zone, the control electrode being insulated from the first emitter zone by a first dielectric layer and extending in a current flow direction of the semiconductor component. The first control structure includes a first control connection and at least one first connection zone arranged between the first control connection and the control electrode and comprising a semiconductor material. | 06-30-2011 |
| 20110154043 | SYSTEMS AND METHODS FOR CRYPTOGRAPHICALLY ENHANCED AUTOMATIC BLACKLIST MANAGEMENT AND ENFORCEMENT - Embodiments relate to systems and methods for the management and enforcement of blacklists of counterfeited, cloned or otherwise unauthenticated devices. In an embodiment, a system comprises an accessory comprising an authentication chip including data signed by a private verification key, the data including a unique identifier related to the accessory, and a device comprising a public verification key forming a verification key pair with the private verification key and an identifier list, the device configured to read the data from the authentication chip, compare the unique identifier with the identifier list, and reject the accessory if the unique identifier is found in the identifier list. | 06-23-2011 |
| 20110153889 | COUPLING DEVICES, SYSTEM COMPRISING A COUPLING DEVICE AND METHOD FOR USE IN A SYSTEM COMPRISING A COUPLING DEVICE - The invention relates to coupling devices, a system comprising a coupling device and a method for use in a system comprising a coupling device. | 06-23-2011 |
| 20110147930 | Semiconductor Component of Semiconductor Chip Size with Flip-Chip-Like External Contacts - A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the semiconductor component that are arranged in the manner of a flip-chip on its active upper side. The semiconductor chip can be encapsulated by a plastic compound at least on its rear side and its side edges. The outer contacts, which can be arranged on external contact connecting areas, can project from the active upper side. | 06-23-2011 |
| 20110147843 | Semiconductor Component and Method for Producing a Semiconductor Component - A semiconductor component includes at least one field effect transistor disposed along a trench in a semiconductor region and has at least one locally delimited dopant region in the semiconductor region. The at least one locally delimited dopant region extends from or over a pn junction between the source region and the body region of the transistor or between the drain region and the body region of the transistor into the body region as far as the gate electrode, such that a gap between the pn junction and the gate electrode in the body region is bridged by the locally delimited dopant region. | 06-23-2011 |
| 20110147838 | Tunnel Field Effect Transistors - Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region. | 06-23-2011 |
| 20110147471 | METHOD FOR PRODUCING A SEMICONDUCTOR WAFER WITH REAR SIDE IDENTIFICATION - A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification. | 06-23-2011 |
| 20110146410 | PRESSURE SENSOR INCLUDING SWITCHABLE SENSOR ELEMENTS - A semiconductor device includes a first sensor element in a first branch of a Wheatstone bridge and a second sensor element in a second branch of the Wheatstone bridge. The semiconductor device includes a first reference element in the first branch and a second reference element in the second branch. The semiconductor device includes a circuit configured to switch the first sensor element to the second branch and the second sensor element to the first branch. | 06-23-2011 |
| 20110138249 | Apparatus and Method for Detecting an Error Within a Plurality of Coded Binary Words Coded by an Error Correction Code - An apparatus for detecting an error within a plurality of coded binary words coded by an error correction code includes a combiner connected town error detector. The combiner generates a combined binary word by combining a first coded binary word and a second coded binary word of the plurality of coded binary words, so that the determined combined binary word is a code word of the error correction code if the first coded binary word and the second coded binary word are code words of the error correction code, and so that the combined binary word is not a code word of the error correction code if the first coded binary word or the second coded binary word is not a code word of the error correction code. Further, the error detector may determine an error detection bit sequence indicating whether or not the combined binary word is a code word of the error correction code. | 06-09-2011 |
| 20110138231 | HIGH COMPRESSION PROGRAM FLOW TRACE - A system and method provides for generating high compression program flow trace data by generating first program flow trace data whenever a conditional branch instruction of a program is executed by a CPU, generating second program flow trace data whenever an indirect branch instruction of a subset of indirect branch instructions is executed by the CPU, and generating third program flow trace data whenever a stack for storing instruction addresses of the program is manipulated, the manipulation occurring after a CALL instruction to a function or subroutine of the program is executed by the CPU and before a RET instruction is executed by the CPU. The subset of indirect branch instructions excludes RET indirect branch instructions of any function or subroutine for which the stack is not manipulated after a CALL instruction to the functions or subroutines is executed by the CPU and before the RET instruction is executed by the CPU. | 06-09-2011 |
| 20110133922 | TIRE LOCALIZATION SYSTEM - A tire localization system for locating the position of a tire of a vehicle having five or more wheels, includes a number of tire pressure monitoring system (TPMS) wheel modules of a vehicle TPMS, each wheel module being attached to each one of the wheels or a tire thereof, respectively. Each TPMS wheel module includes a radio, frequency identification (RFID) reader. The system further includes a number of RFID tags, each RFID tag being associated with and storing wheel position information of one of the wheels, and each RFID tag being positioned externally of its associated wheel. Each of the RFID readers is arranged, upon activation, to interrogate its associated RFID tag, and the associated RFID tag is arranged, upon interrogation, to transmit its stored position information to the RFID reader for transmission by the TPMS wheel module to a central control unit. A tire localization method is also provided. | 06-09-2011 |
| 20110133304 | Structure and Method for Placement, Sizing and Shaping of Dummy Structures - A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas. | 06-09-2011 |
| 20110133262 | Power Semiconductor Component with Plate Capacitor Structure and Edge Termination - A semiconductor component includes a body with a drift zone, a source zone, a body zone, and a drain zone. A gate forms a MOS structure with the drift zone, with the source zone and with the body zone. An edge termination between the lateral edge and the MOS structure includes a plurality of field rings which enclose the MOS structure. The lateral edge is at the same potential as the drift zone, and the edge termination reduces voltage between the lateral edge and the source zone. A horizontally extending edge plate is disposed at the front side between the lateral edge and the edge termination. The edge plate is at the same potential as the drift zone and forms a plate capacitor structure including a field plate lying above the edge plate. | 06-09-2011 |
| 20110133188 | Process for Simultaneous Deposition of Crystalline and Amorphous Layers with Doping - One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics. | 06-09-2011 |
| 20110128767 | Memory With Intervening Transistor - Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition. | 06-02-2011 |
| 20110127998 | GMR SENSOR WITHIN MOLDED MAGNETIC MATERIAL EMPLOYING NON-MAGNETIC SPACER - An integrated circuit includes a leadframe, and a die having a top surface, a bottom surface, and a plurality of perimeter sides and including at least one magnetic field sensor element disposed proximate to the top surface, wherein the bottom surface is bonded to the leadframe. A molded magnetic material encapsulates the die and at least a portion of the leadframe, and provides a magnetic field substantially perpendicular to the top surface of the die. A non-magnetic material is disposed between the die and the molded magnetic material at least along perimeter sides of the die intersecting a lateral magnetic field component which is parallel to the top surface of the die. | 06-02-2011 |
| 20110127675 | LAMINATE ELECTRONIC DEVICE - A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern. | 06-02-2011 |
| 20110127576 | Bipolar Power Semiconductor Component Comprising a P-type Emitter and More Highly Doped Zones in the P-type Emitter, and Production Method - A bipolar power semiconductor component configured as an IGBT includes a semiconductor body, in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction. The p-doped emitter has a number of heavily p-doped zones having a locally increased p-type doping. | 06-02-2011 |
| 20110127314 | BONDING MATERIAL WITH EXOTHERMICALLY REACTIVE HETEROSTRUCTURES - A bonding material including a meltable joining material and a plurality of heterostructures distributed throughout the meltable joining material, the heterostructures comprising at least a first material and a second material capable of conducting a self-sustaining exothermic reaction upon initiation by an external energy to generate heat sufficient to melt the meltable joining material. | 06-02-2011 |
| 20110121461 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING A SEMICONDUCTOR DEVICE WITH A CLIP - A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip. | 05-26-2011 |
| 20110121458 | Bonding Connection Between a Bonding Wire and a Power Semiconductor Chip - A bonding connection between a bonding wire and a power semiconductor chip is disclosed. The power semiconductor chip has a semiconductor body arranged in which is an active cell region with a multiplicity of cells arranged one following the other in a lateral direction and connected electrically in parallel. The semiconductor body has a surface portion arranged above the active cell region in a vertical direction perpendicular to the lateral direction. Applied to the surface portion is a metallization layer onto which a bonding wire is bonded. The bonding wire comprises an alloy containing at least 99% by weight aluminium and at least one further alloying constituent. The aluminum has a grain structure with a mean grain size which is less than 2 μm. | 05-26-2011 |
| 20110121439 | SEMICONDUCTOR DEVICE WITH PROTRUDING COMPONENT PORTION AND METHOD OF PACKAGING - A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices. | 05-26-2011 |
| 20110119542 | SEMICONDUCTOR DEVICE TEST SYSTEM WITH TEST INTERFACE MEANS - A semiconductor device test system has an interface for use with a semiconductor device test method, and a semiconductor device test method. In a first mode of an interface, in reaction to test signals corresponding to a test standard, for example, a JTAG test standard, and received by the interface from a test device, the interface outputs signals corresponding to the test standard to a semiconductor device to be tested. In a second mode of the interface, in reaction to test signals corresponding to the test standard and received by the interface from a test device, the interface outputs signals that do not correspond to the test standard to a semiconductor device to be tested. | 05-19-2011 |
| 20110116560 | OFDM SPACE-TIME OR SPACE-FREQUENCY BLOCK CODE TRANSMITTER - A transmitter for transmitting OFDM signals includes a space-time or space-frequency encoder to generate coded OFDM symbols by arranging a sequence of OFDM symbols or variants thereof in a predetermined space-time or space-frequency block matrix or a portion thereof. The transmitter also includes a frequency selector to select a particular OFDM carrier frequency out of a number of available OFDM carrier frequencies, and a signal generator to generate OFDM signals by applying the selected OFDM carrier frequency to the coded OFDM symbols. | 05-19-2011 |
| 20110115476 | SENSOR SYSTEM INCLUDING MULTIPLE COMPARATORS - A system including a sensor circuit and comparison circuitry. The sensor circuit is configured to provide a sensed signal. The comparison circuitry is configured to receive an input signal that corresponds to the sensed signal. The comparison circuitry provides output signals that switch state at different levels of the input signal. | 05-19-2011 |
| 20110115096 | ELECTRODEPOSITING A METAL IN INTEGRATED CIRCUIT APPLICATIONS - A method is described in which a contact hole to an interconnect in an insulating layer is fabricated. A barrier layer is subsequently applied. Afterward, a photoresist layer is applied, irradiated and developed. With the aid of a galvanic method, a copper contact is then produced in the contact hole. Either the barrier layer or an additional boundary electrode layer serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production. | 05-19-2011 |
| 20110115068 | Power Semiconductor Module and Method for Operating a Power Semiconductor Module - A power semiconductor module includes a circuit carrier including an insulation carrier having a top side on which a metallization layer is arranged. A power semiconductor chip is arranged on a side of the metallization layer facing away from the insulation carrier, and which has on a top side of the power semiconductor chip facing away from the circuit carrier an upper chip metallization composed of copper or a copper alloy having a thickness of greater than or equal to 1 μm. An electrical connection conductor composed of copper or a copper alloy is connected to the upper chip metallization at a connecting location. A potting compound extends from the circuit carrier to at least over the top side of the power semiconductor chip and completely covers the top side of the power semiconductor chip, encloses the connection conductor at least in the region of the connecting location, and has a penetration of less than or equal to 30 according to DIN ISO 2137 at a temperature of 25° C. | 05-19-2011 |
| 20110115007 | Power Semiconductor Component with Plate Capacitor Structure Having an Edge Plate Electrically Connected to Source or Drain Potential - A lateral power semiconductor component has a front side, a rear side and a lateral edge. The component further includes a drift zone of a first conductivity type, a source zone of the first conductivity type, a body zone of a second conductivity type opposite the first conductivity type, and a drain zone of the first conductivity type. A gate forms a MOS structure with the drift zone, the source zone and the body zone. A horizontally extending field plate above each semiconductor region of the power semiconductor component forms a plate capacitor structure with an edge plate lying under the field plate. The edge plate includes a highly doped semiconductor material and is electrically connected to one of a source potential and a drain potential of the power semiconductor component. | 05-19-2011 |
| 20110113400 | METHOD OF MAKING IN AN INTEGRATED CIRCUIT INCLUDING SIMPLIFYING METAL SHAPES - A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of vias connected thereto. The method further includes segmenting each of the wires into a plurality of bricks according to a set of equally spaced parallel grid lines extending in direction which is perpendicular to the preferred direction such that each wire comprises a series of consecutive bricks with brick boundaries between consecutive bricks occurring at a grid line, defining each brick as a regular or complex brick based on at least one brick criteria, and defining brick groups based on one or more grouping criteria, wherein each group contains one or more consecutive bricks of a same wire and each brick belongs to only one group so that each wire comprises a series of one or more consecutive groups, and wherein groups containing at least one complex brick are defined as complex groups. | 05-12-2011 |
| 20110111565 | DUAL GATE FINFET - A circuit has a fin supported by a substrate. A source is formed at a first end of the fin and a drain is formed at a second end of the fin. A pair of independently accessible gates are laterally spaced along the fin between the source and the drain. Each gate is formed around approximately three sides of the fin. | 05-12-2011 |
| 20110109489 | Data Converter Having a Passive Filter - Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC). | 05-12-2011 |
| 20110109370 | Level Converter - A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal. | 05-12-2011 |
| 20110108971 | LAMINATE ELECTRONIC DEVICE - A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 μm. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip. | 05-12-2011 |
| 20110108916 | Semiconductor Devices and Methods - Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. | 05-12-2011 |
| 20110107595 | SEMICONDUCTOR DEVICE - A method of electrically interconnecting a semiconductor chip to another electronic device including providing a carrier including contact pins and a chip attached to the carrier, the chip having a copper contact pad that faces away from the carrier, extending a copper electrical connector between the contact pins and the contact pad, and diffusion soldering the copper electrical connector to the active area with a solder material including tin to form a solder connection including a contiguous bronze coating disposed between and in direct contact with both the copper electrical connector and the contact pad. | 05-12-2011 |
| 20110105136 | RADIO BASE STATIONS, RADIO COMMUNICATION DEVICES, METHODS FOR CONTROLLING A RADIO BASE STATION AND METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE - In an embodiment, a radio base station is provided. The radio base station may include a transceiver configured to transmit data to a radio communication device and receive data from the radio communication device using a plurality of component carriers, each component carrier including a pre defined frequency band including a plurality of resource elements; a component carrier determiner configured to determine a subset comprising at least one component carrier of the plurality of component carriers, wherein as the at least one component carrier of the subset may be used by the radio communication device for a pre-defined communication mode; and a message generator configured to generate a message including information specifying that the at least one component carrier of the subset may be used by the radio communication device for the pre-defined communication mode. | 05-05-2011 |
| 20110105119 | RADIO BASE STATIONS, RADIO COMMUNICATION DEVICES, METHODS FOR CONTROLLING A RADIO BASE STATION, AND METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE - In an embodiment, a radio base station is provided. The radio base station may include a message generator configured to generate a message including information specifying whether the radio base station is a radio base station which allows handover to another radio base station. | 05-05-2011 |
| 20110105055 | SINGLE POLE MULTI THROW SWITCH - A single pole multi throw switch comprises a first switching unit, a second switching unit coupled to a common port and comprising a parasitic off state capacitance, and a matching unit. The matching unit may be coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive. | 05-05-2011 |
| 20110103150 | NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING - A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells. | 05-05-2011 |
| 20110102054 | POWER SEMICONDUCTOR MODULE AND METHOD FOR OPERATING A POWER SEMICONDUCTOR MODULE - A power semiconductor module includes a normally on, controllable first power semiconductor switch including at least one first power semiconductor chip, and a normally off, controllable second power semiconductor switch including at least one second power semiconductor chip. The load paths of the first power semiconductor switch and of the second power semiconductor switch are connected in series. The control terminals of all first power semiconductor chips are permanently electrically conductively connected to a conductor track to which no load terminal of any of the first power semiconductor chips is permanently electrically conductively connected, and to which no load terminal and no control terminal of any of the second power semiconductor chips are permanently electrically conductively connected. | 05-05-2011 |
| 20110101973 | SENSOR SYSTEM AND METHOD - A sensing system includes a conductor with a current flow path therethrough configured such that a current flowing through the conductor establishes an inhomogeneous magnetic field. A first pair of sensors is situated a first location having a first sensitivity, a second pair of sensors is situated at a second location having a second sensitivity lower than the first sensitivity. The first and second pairs of sensors are configured to measure the inhomogeneous magnetic field at their respective locations. | 05-05-2011 |
| 20110101532 | DEVICE FABRICATED USING AN ELECTROPLATING PROCESS - A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer. | 05-05-2011 |
| 20110101501 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ZONES AND MANUFACTURING METHOD - A semiconductor device includes first semiconductor zones of a first conductivity type having a first dopant species of the first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type. The semiconductor device also includes second semiconductor zones of the second conductivity type including the second dopant species. The first and second semiconductor zones are alternately arranged in contact with each other along a lateral direction extending in parallel to a surface of a semiconductor body. One of the first and second semiconductor zones constitute drift zones and a diffusion coefficient of the second dopant species is at least twice as large as the diffusion coefficient of the first dopant species. A concentration profile of the first dopant species along a vertical direction perpendicular to the surface of the semiconductor body includes at least two maxima. | 05-05-2011 |
| 20110099439 | AUTOMATIC DIVERSE SOFTWARE GENERATION FOR USE IN HIGH INTEGRITY SYSTEMS - Systems, devices and methods of automatic diverse software generation are disclosed. In an embodiment, a method includes providing a base algorithm implementation related to a first hardware profile of a hardware resource, automatically generating a diverse algorithm implementation related to a second hardware profile different from the first hardware profile using the base algorithm implementation and information about the hardware resource, and executing the base algorithm implementation and the diverse algorithm implementation. Embodiments of systems and devices, including microprocessors and compilers, are also disclosed. | 04-28-2011 |
| 20110098075 | MOBILE RADIO COMMUNICATION DEVICES HAVING A TRUSTED PROCESSING ENVIRONMENT AND METHOD FOR PROCESSING A COMPUTER PROGRAM THEREIN - In an embodiment, a mobile radio communication device is provided. The mobile radio communication device may include a mobile radio communication protocol circuit configured to provide a mobile radio base station function for a mobile radio communication with another mobile radio communication device, a network control interface circuit configured to receive communication control signals from a mobile radio network circuit being controlled by a mobile radio network operator to control the mobile radio communication protocol circuit, and a trusted processing circuit configured to process a computer program in a trusted processing environment to provide a trusted processing result, wherein the trusted processing circuit is outside of the mobile radio network operator's domain. | 04-28-2011 |
| 20110097855 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 04-28-2011 |
| 20110097826 | DEVICE AND METHOD FOR DETECTING STRESS MIGRATION PROPERTIES - A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module. | 04-28-2011 |
| 20110096519 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 04-28-2011 |
| 20110095364 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer. | 04-28-2011 |
| 20110095347 | VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH - Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus. | 04-28-2011 |
| 20110093857 | Multi-Threaded Processors and Multi-Processor Systems Comprising Shared Resources - An apparatus is provided comprising at least two processing entities. Shared resources are usable by a first and a second processing entity. A use of the shared resources is detected, and the execution of instructions associated with said processing entities is controlled based on the detection. | 04-21-2011 |
| 20110093714 | SYSTEMS AND METHODS FOR ASYMMETRIC CRYPTOGRAPHIC ACCESSORY AUTHENTICATION - Embodiments relate to systems, methods and devices for asymmetric cryptographic authentication. In an embodiment, a system includes an accessory comprising an authentication chip, the authentication chip comprising a public authentication key, a private authentication key and data signed by a private verification key; and a device comprising a public verification key forming a verification key pair with the private verification key, the device configured to read the data and public authentication key from the authentication chip, verify the data and the public authentication key using the public verification key, and authenticate the accessory for use with the device using the public authentication key if verified. | 04-21-2011 |
| 20110093537 | METHOD FOR DETERMINING ACTIVE COMMUNICATION SESSIONS AND COMMUNICATION SESSION INFORMATION SERVER - A method for ascertaining active communication sessions may include receiving a request to ascertain active communication sessions by a communication session information server; transmitting respective challenges to determine whether communication sessions are currently active from the communication session information server to at least two communication session servers; receiving respective challenge responses from the at least two communication session servers, which indicate one or more active communication sessions controlled by the respective communication session server or indicate that such communication sessions currently do not exist, by the communication session information server; and transmitting a first response, which indicates one or more active communication sessions controlled by the at least two communication session servers or indicates that such communication sessions currently do not exist, by the communication session information server. | 04-21-2011 |
| 20110092001 | LIGHT EMITTING DIODE - A semiconductor device including a wafer-level LED includes a semiconductor structure coupled to first and second electrodes. The semiconductor includes a P-doped portion of a first layer to an N-doped portion of a second layer. The first layer includes a surface configured to emit light. The first electrode is electrically coupled to the P-doped portion of the first layer on a first side of the semiconductor structure. The first side is adjacent to the surface that is configured to emit the light. The second electrode is electrically coupled to the N-doped portion of the second layer on a second side of the semiconductor structure. The second side is also adjacent to the surface that configured to emit light. | 04-21-2011 |
| 20110089994 | Threshold Voltage Modification Via Bulk Voltage Generator - The present disclosure relates to threshold voltage modification via a voltage generator connected to bulk nodes of transistors. | 04-21-2011 |
| 20110089545 | APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES - An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. | 04-21-2011 |
| 20110089532 | INTEGRATED CIRCUIT WITH ESD STRUCTURE - An integrated circuit includes a semiconductor body of a first conductivity type. The semiconductor body includes a first semiconductor zone of a second conductivity type opposite the first conductivity type. The first semiconductor zone extends to a surface of the semiconductor body. A second semiconductor zone of the first conductivity type is embedded in the first semiconductor zone and extends as far as the surface. A third semiconductor zone of the second conductivity type at least partly projects from the first semiconductor zone along a lateral direction running parallel to the surface. A contact structure provides an electrical contact with the first and second semiconductor zones at the surface. The second semiconductor zone is arranged, along the lateral direction, between the part of the third semiconductor zone which projects from the first semiconductor zone and a part of the contact structure in contact with the first semiconductor zone. | 04-21-2011 |
| 20110085359 | ADAPTIVE FREQUENCY JITTER FOR CONTROLLER - In order to convert an input power to one or more DC power levels that are provided to an output load, some aspects of the present disclosure relate to techniques for driving a switching regulator as a function of a pulsed voltage signal. In particular, this pulsed voltage signal is provided substantially at a target frequency, but exhibits frequency jitter that causes the pulsed voltage to vary slightly from the target frequency in time. The frequency jitter has a frequency range that varies as a function of the output load. | 04-14-2011 |
| 20110084369 | DEVICE INCLUDING A SEMICONDUCTOR CHIP AND A CARRIER AND FABRICATION METHOD - A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier. | 04-14-2011 |
| 20110081863 | Phase-Lock in All-Digital Phase-Locked Loops - This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information. | 04-07-2011 |
| 20110081016 | SECURE DATA COMMUNICATION USING ELLIPTIC CURVE CRYPTOLOGY - A contactless device including an contactless communication interface configured to receive a challenge from a contactless reader and a controller configured to generate an enciphered response using elliptic curve cryptology. Moreover, the enciphered response includes the challenge enciphered with a private key stored in non-volatile memory of the contactless device and data can be integrated as part of the challenge and/or the enciphered response. | 04-07-2011 |
| 20110080152 | VOLTAGE REGULATION AND MODULATION CIRCUIT - A voltage regulation and modulation circuit of a contactless device, including an adjustable impedance circuit configured to maintain an amplitude of an input voltage to be less than an amplitude of a reference voltage; a current buffer circuit coupled between the adjustable impedance circuit and a load, and configured to buffer a supply current, which is output from the adjustable impedance circuit, to the load; and a parallel regulator coupled to an output of the current buffer circuit, and configured to maintain a constant supply voltage at the load. | 04-07-2011 |
| 20110078460 | Apparatus for Logging a Configuration of a Microprocessor System and Method for Logging a Configuration of a Microprocessor System - An apparatus includes a logging apparatus and a configuration apparatus. The logging apparatus has a security module operable to create a manipulation-proof log. The configuration apparatus is operable to configure a configurable microprocessor system. The configuration apparatus is further operable to be coupled to the logging apparatus in order to log a configuration of the microprocessor system using the logging apparatus. | 03-31-2011 |
| 20110075496 | Memory Controller Comprising Adjustable Transmitter Impedance - Memory controllers, memory devices and methods are provided in which test data is transmitted and signal parameters are varied. The transmitted test data is read, and based on a comparison between transmitted test data and read test data a transmitter impedance is adjusted. | 03-31-2011 |
| 20110075451 | Power Semiconductor Module and Method for Operating a Power Semiconductor Module - A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use. | 03-31-2011 |
| 20110074480 | Method and Apparatus for the Controlled Delay of an Input Signal - An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith. | 03-31-2011 |
| 20110070695 | METHOD OF FABRICATING A HIGH-TEMPERATURE COMPATIBLE POWER SEMICONDUCTOR MODULE - The invention relates to a method for fabricating a high-temperature compatible power semiconductor module in which a power semiconductor chip is bonded by means of a diffusion solder layer to a substrate and said substrate is bonded by means of silver sintered layer to a base plate, after which a bonding element is bonded to the top chip metallization. To prevent oxidation of the predefined bond area when producing the diffusion solder layer and the sintered silver layer | 03-24-2011 |
| 20110069528 | ELECTRONIC DEVICE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND A METHOD FOR BLOCKING A DEVICE - One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state. | 03-24-2011 |
| 20110069013 | DEVICES AND METHODS FOR CONTROLLING BOTH LED AND TOUCH SENSE ELEMENTS VIA A SINGLE IC PACKAGE PIN - Devices and methods for minimizing a number of I/O pins needed to control LED and touch sense operations are described and disclosed herein. In an embodiment, a method comprises controlling at least one light emitting diode (LED) element via a single pin, and controlling at least one touch sense element via the single pin. In an embodiment, a touch-sensitive light emitting diode (LED) display device comprises at least one LED element, at least one touch sense element, and a controller integrated in an integrated circuit (IC) and coupled to the at least one LED element and the at least one touch sense element via a single pin. The controller is configured to communicate via the pin with the at least one LED element and the at least one touch sense element. | 03-24-2011 |
| 20110068484 | DEVICE AND MANUFACTURING METHOD - A description is given of a device, including a semiconductor chip, a first metal layer laterally extending over the semiconductor chip, the first metal layer having a first thickness. A dielectric layer laterally extends over the first metal layer, and a second metal layer laterally extends over the dielectric layer, the second metal layer having a second thickness that is at least four times larger than the first thickness. | 03-24-2011 |
| 20110068420 | Semiconductor Structure with Lamella Defined by Singulation Trench - A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench. | 03-24-2011 |
| 20110057304 | METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer. | 03-10-2011 |
| 20110053582 | END-USER DEVICES AND METHODS FOR CONTROLLING AN END-USER DEVICE - In an embodiment, an end-user mobile device is provided. The end-user mobile device may include a transmitter configured to broadcast context information based on the occurrence of a pre-determined event. | 03-03-2011 |
| 20110053319 | Method for Fabricating a Circuit Substrate Assembly and a Power Electronics Module Comprising an Anchoring Structure for Producing a Changing Temperature-Stable Solder Bond - A power semiconductor module is fabricated by providing a circuit substrate with a metal surface and an insulating substrate comprising an insulation carrier featuring a bottom side provided with a bottom metallization layer. An anchoring structure is provided comprising a plurality of oblong pillars each featuring a first end facing away from the insulation carrier, at least a subset of the pillars being distributed over the anchoring structure in its entirety, it applying for each of the pillars of the subset that from a sidewall thereof no or a maximum of three elongated bonding webs each extend to a sidewall of another pillar where they are bonded thereto. The anchoring structure is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom metallization layer and anchoring structure by means of a solder packing all interstices between the metal surface and bottom metallization layer with the solder. | 03-03-2011 |
| 20110051643 | METHOD OF TRANSMITTING DATA AND COMMUNICATION DEVICE - A method of transmitting data is described comprising selecting a transmission mode from at least a first and a second transmission mode, wherein according to the first transmission mode data is transmitted in at least two first time periods using first communication resources wherein the at least two first time periods are separated by a first time interval, wherein according to the second transmission mode data is transmitted in at least two second time periods using second communication resources wherein the at least two second time periods are separated by a second time interval, and wherein the first time interval is longer than the second and the first communication resources allow the transmission of a higher amount of data than the second communication resources; and transmitting data to the selected transmission mode. | 03-03-2011 |
| 20110051302 | INTEGRATED POWER DEVICE AND METHOD - A method of protecting a circuit arrangement including an integrated power dissipating device, and a circuit arrangement including an integrated power dissipating device. One method provides measuring a temperature difference between temperatures at a first position and a second position of the arrangement, the second position being distant to the first position; generating a thermal protection signal, and generating the control signal dependent on the thermal protection signal; and the thermal protection signal assuming a first signal level, if the temperature difference rises to a first temperature difference threshold, and assuming a second signal level, if the temperature difference falls to a second temperature difference threshold. | 03-03-2011 |
