| 20110227600 | METHOD OF TESTING SEMICONDUCTOR DEVICE - A method of testing a semiconductor device is provided. In order to provide the same conditions and application of electrical power as a test process in which characteristic functions of a semiconductor device are tested, the number of removal power pins is set. The final number of power pins that can be provided during a normal operation is determined by setting the number of removal power pins. The final number of power pins represents the minimum number of power pins that are requested to be connected for the normal operation of the semiconductor device, and is met by removing a timing margin during the operation of the semiconductor device. Afterwards, a delay test pattern that can be used during a scan mode is applied. When it is determined to be defective by the delay test pattern, a cycle of the delay test pattern is increased. The increased cycle of the delay test pattern may increase the number of switching operations in the delay test pattern or offset ground bouncing caused by excessive current requested per unit time, so that an overkill phenomenon in which a good semiconductor device is determined to be defective can be prevented. | 09-22-2011 |
