| INDILINX CO., LTD. Patent applications |
| Patent application number | Title | Published |
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| 20120036311 | CACHE AND DISK MANAGEMENT METHOD, AND A CONTROLLER USING THE METHOD - A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a (*portion? part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance. | 02-09-2012 |
| 20120030435 | MEMORY DEVICE, MEMORY MANAGEMENT DEVICE, AND MEMORY MANAGEMENT METHOD - Disclosed is a memory device which receives a check command and check information from a Central Processing Unit (CPU), reads data written in a predetermined area of a memory based on the check information in response to the check command, and checks a data pattern of the data read based on the check information. | 02-02-2012 |
| 20120011334 | SSD CONTROLLER, AND METHOD FOR OPERATING AN SSD CONTROLLER - A Solid State Drive (SSD) controller is disclosed. When a data read command is transmitted by a host, the SSD controller may select a representative pointer from at least one first pointer by checking a point in time when data writing is completed in a buffer by at least one memory, read the data from the buffer by referring to a second pointer, and transmit the read data to the host, based on the representative pointer. | 01-12-2012 |
| 20120005559 | APPARATUS AND METHOD FOR MANAGING A DRAM BUFFER - An apparatus and method for managing a dynamic random access memory (DRAM) buffer are disclosed. The DRAM buffer managing apparatus and method may generate an error correction code (ECC) for data to be written in a DRAM buffer, and may write the data and the ECC in the DRAM buffer. | 01-05-2012 |
| 20110302365 | STORAGE SYSTEM USING A RAPID STORAGE DEVICE AS A CACHE - Provided is a storage system using a high speed storage device as a cache. The storage system includes a large-volume of first storage device, a high speed second storage device, and a Random Access Memory (RAM). The large-volume of first storage device corresponds to a Hard Disk Drive (HDD), and the high speed second storage device corresponds to a Solid State Drive (SSD). Also, the high speed second drive is used as a cache. The first storage device manages content files super block by super block, and the second storage device manages cache files block by block. | 12-08-2011 |
| 20110296089 | PROGRAMMING METHOD AND DEVICE FOR A BUFFER CACHE IN A SOLID-STATE DISK SYSTEM - Provided are a method and apparatus for programming a buffer cache in a Solid State Disk (SSD) system. The buffer cache programming apparatus in the SSD system may include a buffer cache unit to store pages, a memory unit including a plurality of memory chips, and a control unit to select at least one of the page as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips. | 12-01-2011 |
| 20110289262 | CONTROLLER FOR SOLID STATE DISK, WHICH CONTROLS SIMULTANEOUS SWITCHING OF PADS - Provided is a controller for a solid state disk, to control simultaneous switching of pads. The controller for the solid state disk may control simultaneous switching of a plurality of output pads or a plurality of input pads that correspond to a plurality of channels. In particular, the controller may properly delay signals driven to the output pads or input pads, to reduce power supplied to the pads, and to prevent ground bouncing, as well as, maintain a quality of signals. | 11-24-2011 |
| 20110276740 | CONTROLLER FOR SOLID STATE DISK WHICH CONTROLS ACCESS TO MEMORY BANK - A controller for a solid state disk is provided. The controller includes a storage module to store an index of at least one idle bank among a plurality of memory banks, and a control module to control an access to the at least one idle bank using the stored index. Here, the access to the at least one idle bank may be controlled based on a state of a channel corresponding to each of the at least one idle bank. | 11-10-2011 |
| 20110271164 | MEMORY CONTROLLER AND MEMORY MANAGEMENT METHOD - Provided is a memory controller that generates Error Correction Code (ECC) information for data based on a required reliability level predetermined based on a type of the data, that computes an ECC code for the data based on the ECC information, and that records the ECC code in a memory based on the ECC information. | 11-03-2011 |
