| IMEC Patent applications |
| Patent application number | Title | Published |
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| 20120133535 | Interleaved Pipelined Binary Search A/D Converter - The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed. | 05-31-2012 |
| 20120132529 | METHOD FOR PRECISELY CONTROLLED MASKED ANODIZATION - The present invention is related to a method for masked anodization of an anodizable layer on a substrate, for example an aluminum layer present on a sacrificial layer, wherein the sacrificial layer needs to be removed from a cavity comprising a Micro or Nano Electromechanical System (MEMS or NEMS). Anodization of an Al layer leads to the formation of elongate pores, through which the sacrificial layer can be removed. According to the method of the invention, the anodization of the Al layer is done with the help of a first mask which defines the area to be anodized, and a second mask which defines a second area to be anodized, said second area surrounding the first area. Anodization of the areas defined by the first and second mask leads to the formation of an anodized structure in the form of a closed ring around the first area, which forms a barrier against unwanted lateral anodization in the first area. | 05-31-2012 |
| 20120129296 | METHOD FOR FORMING AN ORGANIC MATERIAL LAYER ON A SUBSTRATE - A method for forming an organic material layer on a substrate in an in-line deposition system is disclosed. In one aspect, the organic material is deposited with a predetermined non-constant deposition rate profile, which includes a first predetermined deposition rate range provided to deposit at least a first monolayer of the organic material layer with a first predetermined average deposition rate and a second predetermined deposition rate range provided to deposit at least a second monolayer of the organic material layer with a second predetermined average deposition rate. The injection of organic material through the openings of the injector is controlled for realizing the predetermined deposition rate profile. | 05-24-2012 |
| 20120127559 | HOLOGRAPHIC VISUALIZATION SYSTEM COMPRISING A HIGH DATA REFRESH RATE DND DRIVER ARRAY - A DND chip is disclosed. In one aspect, the chip includes a 2D DND array of DND elements logically arranged in rows and columns, and a DND driver architecture for actuating the DND elements. The DND driver has a set of first drive lines along the rows and a set of second drive lines along the columns, a set of first line drivers for each biasing one line from the set of first drive lines and a set of second line drivers for each biasing a line from the set of second drive lines. A plurality of second line drivers are spatially grouped together to serve a block of DND elements, and that plurality of second line drivers are spatially covered substantially completely by at least some DND elements of the block of DND elements. A holographic visualization system including the DND chip is provided. | 05-24-2012 |
| 20120127558 | DIFFRACTIVE OPTICAL NANO-ELECTRO-MECHANICAL DEVICE WITH REDUCED DRIVING VOLTAGE - A DND device is disclosed. In one aspect, the device includes a nano-mirror ( | 05-24-2012 |
| 20120126391 | Methods for Embedding Conducting Material and Devices Resulting from Said Methods - Disclosed are methods for forming semiconductor devices and the semiconductor devices thus obtained. In one embodiment, the method may include providing a semiconductor wafer comprising a surface, forming on the surface at least one device, forming a release layer at least in an area of the surface that encircles the at least one device, forming on the release layer at least one wall structure around the at least one device, and forming at least one cap on the at least one wall structure. In one embodiment, the device may include a substrate comprising a surface, at least one device formed on the surface, a release layer formed at least in an area of the surface that encircles the at least one device, at least one wall structure formed around the at least one device, and at least one removable cap formed on the at least one wall structure. | 05-24-2012 |
| 20120121043 | EHF Wireless Communication Receiver Using Beamforming with a Scalable Number of Antenna Paths - The invention relates to a EHF wireless communication receiver comprising a phased array radio arranged for receiving a beam of signals in a predetermined frequency band. The phased array radio comprises a plurality of antenna paths, each arranged for handling one of the incoming signals and forming a differential I/Q output signal, each antenna path comprises a downconversion part and a phase shifting part for applying a controllable phase shift; a signal combination circuitry is connected to the antenna paths and is arranged for combining the differential I/Q output signals; and a control circuitry is connected to the phase shifting parts of the antenna paths and is arranged for controlling the controllable phase shift. In each antenna path, the phase shifting part is a baseband part downstream from the downconversion part and the phase shifting part comprises a set of variable gain amplifiers arranged for applying controllable gains to the respective downconverted incoming signals in the I/Q branches. The control circuitry sets the controllable gains of the variable gain amplifiers to coefficients of a rotational matrix. | 05-17-2012 |
| 20120117523 | INVERSE LITHOGRAPHY FOR HIGH TRANSMISSION ATTENUATED PHASE SHIFT MASK DESIGN AND CREATION - Various implementations of the invention provide for generation of a high transmission phase shift mask layout through inverse lithography techniques. In various implementations of the present invention, a set of mask data having a plurality of pixels is generated. The transmission value associated with each pixel may then be determined through an inverse lithography technique. With various implementations of the invention, the inverse lithography technique identifies an objective function, minimizes the objective function in relation to a simulation of the optical lithographic process, such that the transmission value, which is greater than 6%, may be determined. | 05-10-2012 |
| 20120115296 | TUNNEL FIELD-EFFECT TRANSISTOR WITH GATED TUNNEL BARRIER - A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced). | 05-10-2012 |
| 20120112262 | Method for producing a floating gate memory structure - Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure. | 05-10-2012 |
| 20120107550 | PHOTON INDUCED FORMATION OF METAL COMPRISING ELONGATED NANOSTRUCTURES - The preferred embodiments provide a method for forming at least one metal comprising elongated nanostructure on a substrate. The method comprises exposing a metal halide compound surface to a photon comprising ambient to initiate formation of the at least one metal comprising elongated nanostructure. The preferred embodiments also provide metal comprising elongated nanostructures obtained by the method according to preferred embodiments. | 05-03-2012 |
| 20120099092 | DETECTION OF CONTAMINATION IN EUV SYSTEMS - A sensor for sensing contamination in an application system is disclosed. In one aspect, the sensor comprises a capping layer. The sensor is adapted to cause a first reflectivity change upon initial formation of a first contamination layer on the capping layer when the sensor is provided in the system. The first reflectivity change is larger than an average reflectivity change upon formation of a thicker contamination layer on the capping layer and larger than an average reflectivity change upon formation of an equal contamination on the actual minors of the optics of the system. | 04-26-2012 |
| 20120097547 | Method for Copper Electrodeposition - The present invention is related to a method for electroplating a copper deposit onto a substrate, wherein the method comprises the steps of: a) immersing the substrate into an electroplating bath having a copper ion concentration comprised between 0.5 mmol·l | 04-26-2012 |
| 20120095361 | MULTI-CHANNEL BIOPOTENTIAL SIGNAL ACQUISITION SYSTEMS - A multi-channel biopotential signal acquisition system is disclosed. In the system, a plurality of biopotential channels is corrected for common-mode interference. In one aspect, each biopotential channel includes an electrode for providing a biopotential input signal and an associated amplifier for amplifying the biopotential input signal and providing a biopotential output signal. The output signal is processed in a processor. Each biopotential output signal is passed to a common-mode feedback system, which determines an average common-mode signal and feeds that signal back to each of the amplifiers in each of the biopotential channels to enhance common-mode rejection ratio of the system. | 04-19-2012 |
| 20120094401 | METHODS OF PROCESSING AND INSPECTING SEMICONDUCTOR SUBSTRATES - A method of inspecting a semiconductor substrate having a back surface and including at least one piece of metal embedded in the substrate comprises directing measuring light towards the back surface of the substrate and detecting a portion of the measuring light received back from the substrate. The method also includes determining a distance between the piece of metal and the back surface based upon the detected measuring light received back from the substrate. | 04-19-2012 |
| 20120094317 | Method and Apparatus for Detecting an Analyte - In one aspect, this disclosure provides a substrate for determining the concentration of an analyte within a sample. The substrate includes a conductive region and a recognition layer, the conductive region including at least one particle and having a first surface operatively coupled with the recognition layer, the recognition layer comprising at least one recognition molecule. The distance between the first surface of the conductive region and the recognition molecule is selected such that when the analyte is bound to the recognition layer the combination of the at least one particle and the analyte exhibits at least one of the following effects when radiation is directed through the conductive region and the recognition layer: (i) a particle plasmon effect, (ii) a particle bulk interband absorption, (iii) analyte molecular absorption, and (iv) absorption by the analyte-particle combination. | 04-19-2012 |
| 20120093456 | Coupling Methods and Systems Using a Taper - Disclosed are optical devices for coupling radiation between an optical waveguide and an external medium. In one embodiment, an optical device is disclosed comprising a semiconductor die comprising an integrated optical waveguide core and an overlying optical waveguide comprising a waveguide taper and a waveguide facet. The overlying optical waveguide at least partially overlies the integrated optical waveguide core, and the waveguide facet is between about 1 μm and 200 μm from an edge of the semiconductor die. In another embodiment, a method is disclosed comprising providing a substrate comprising an integrated semiconductor waveguide and forming on the substrate an overlying waveguide comprising a waveguide taper and a waveguide facet. The overlying waveguide at least partially overlies the integrated semiconductor waveguide. The method further includes cutting the substrate about 1 μm and 200 μm from the waveguide facet. | 04-19-2012 |
| 20120092807 | Metal-Insulator-Metal Capacitor and Method for Manufacturing Thereof - The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiO | 04-19-2012 |
| 20120092674 | Determination of Electromagnetic Properties of Samples - Disclosed are methods and devices for measuring electromagnetic properties of samples. In one embodiment, a device is disclosed that includes a substantially two-dimensional measurement chamber comprising a reflective surface, where the reflective surface has a substantially elliptical shape that forms a part of an ellipse having a first focal point and a second focal point. The device further includes an input/output port located at the first focal point and a sample holder located at the second focal point. | 04-19-2012 |
| 20120086840 | DYNAMIC RANGE ENHANCEMENT - A method of increasing dynamic range of pixels in an imaging sensor is disclosed. In one aspect, two image captures are performed, one at a first short integration time and one at a second optimum integration time. An electrical value obtained from a pixel or group of pixels at the first short integration time is used to predict the second integration time using a comparison with a set of reference values. The reference values relate to a saturation electrical value for each pixel or group of pixels to predict the second integration time. The first short integration time is determined as a fractional multiple of the saturation electrical value. The second integration times are such that there is no saturation of the pixel or group of pixels. Adjustments can be made to the reference values to allow for offset immunity and variability in light levels during the second integration time. | 04-12-2012 |
| 20120080596 | Laser Atom Probe and Laser Atom Probe Analysis Methods - A laser atom probe system and a method for analysing a specimen by laser atom probe tomography are disclosed. The system includes a specimen holder whereon a specimen to be analyzed may be mounted, the specimen having a tip shape. The system further includes a detector, an electrode arranged between the specimen holder and the detector, and a voltage source configured to apply a voltage difference between the specimen tip and the electrode. The system also includes at least one laser system configured to direct a laser beam laterally at the specimen tip and a tip shape monitoring means configured to detect and monitor the tip shape, and/or a means for altering and/or controlling one or more laser parameters of said laser beam(s) so as to maintain, restore or control said specimen tip shape. | 04-05-2012 |
| 20120075767 | Method for Producing a Metal-Insulator-Metal Capacitor for Use in Semiconductor Devices - Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an H | 03-29-2012 |
| 20120075604 | Methods and Systems for Evaluating Extreme Ultraviolet Mask Flatness - Disclosed are methods and systems for determining a topography of a lithographic optical element and/or a holder of a lithographic optical element. In one embodiment, the method includes directing electromagnetic radiation towards a lithographic optical element, where the electromagnetic radiation comprises electromagnetic radiation in a first predetermined wavelength range and electromagnetic radiation in a second predetermined wavelength range. The method further includes using the lithographic optical element to adsorb the electromagnetic radiation in the first predetermined wavelength range, and to reflect at least a portion of the electromagnetic radiation in the second predetermined wavelength range towards a substrate comprising a photosensitive layer, thereby exposing the photosensitive layer to form an exposed photosensitive layer. The method still further includes performing an evaluation of the exposed photosensitive layer and, based on the evaluation, determining a topography of the lithographic optical element. | 03-29-2012 |
| 20120064836 | Amplifier Circuit for a Ranging Transceiver - An amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an input configured to receive an input signal. The amplifier circuit further includes an amplifier connected to the input that is configured to receive the input signal and generate a modulated input signal based on the input signal and one of a first amplification level and a second amplification level. The amplifier comprises a first transistor configured to receive the input signal and a second transistor connected in cascode with the first transistor. The amplifier circuit further includes a switching component configured to switch the amplifier between the first amplification level and the second amplification level. The amplifier circuit still further includes an output connected to the amplifier and configured to output the modulated input signal. | 03-15-2012 |
| 20120064567 | ACTIVE MICRO SIEVE AND METHODS FOR BIOLOGICAL APPLICATIONS - An active sieve device for the isolation and characterization of bio-analytes is provided, comprising a substrate for supporting the bio-analytes. The substrate comprises a plurality of interconnections and a plurality of regions, each region comprising a hole and at least one electrode embedded in or located on the substrate and electrically associated with the hole. Each region further comprises at least one transistor integrated in the substrate and operably connected to the at least one electrode and to at least one of the plurality of interconnections. | 03-15-2012 |
| 20120063646 | SYSTEM AND METHOD FOR MOTION DETECTION AND THE USE THEREOF IN VIDEO CODING - A system and method for motion detection and the use thereof in video coding are disclosed. In one aspect, a method of defining a region of motion within a video frame in a sequence of video frames comprises loading a current video frame and at least one reference video frame from the sequence, the reference video frame being different from the current video frame. The method further comprises applying filtering operations on the current and the reference video frame in order to obtain at least two scales of representation of the current and the reference video frame. The method further comprises determining for each of the scale representations a video-frame like representation of the structural changes between the current and the reference video frame. The method further comprises combining the video-frame like representations of different scales. The method further comprises determining one or more regions of motion from the combination. | 03-15-2012 |
| 20120063496 | Wireless Transmitters - Transmitter circuits for generating baseband signals having low receiver-band noise are disclosed. In one embodiment, the transmitter circuit comprises an active filtering-and-amplifying component comprising a first input configured to receive a first input signal, and a first output configured to output a first output signal. The transmitter circuit further comprises a passive filtering component comprising a second input connected to the first output and configured to receive the first output signal, a passive pole arrangement comprising a number of switchable resistance elements and a capacitance element connected across the plurality of switchable resistance elements, and a second output configured to output a second output signal having reduced noise as compared to the first output signal. The transmitter still further comprises a number of feedback loops connecting the passive filtering component to the first input. | 03-15-2012 |
| 20120063252 | VARIABILITY RESILIENT SENSE AMPLIFIER WITH REDUCED ENERGY CONSUMPTION - An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors. | 03-15-2012 |
| 20120063211 | METHOD FOR IMPROVING WRITABILITY OF SRAM MEMORY - A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell. | 03-15-2012 |
| 20120062978 | METHOD FOR OPERATING A MICROMIRROR DEVICE WITH ELECTROMECHANICAL PULSE WIDTH MODULATION - A method of operating by pulse width modulation a micromirror device is disclosed. In one aspect, the method includes providing a micromirror device having a micromirror element electrostatically deflectable around a rotation axis between a first and second position. The micromirror element is controllable by applying voltage signals to a first and second electrode on one side of the rotation axis and a third and fourth electrode on the other side. The method includes associating an intermediate value of intensity to the micromirror element during a time frame, the intensity being between a first value corresponding to the first position and a second value corresponding to the second position. The method includes switching the micromirror element between the first and second position. The intermediate value corresponds to the ratio of periods in the time frame in which the micromirror element is in the first or second position. | 03-15-2012 |
| 20120060915 | METHOD FOR PLASMA TEXTURING - A dry etching method for texturing a surface of a substrate is disclosed. The method includes performing a first dry etching onto the surface of the substrate thereby forming a surface texture with spikes and valleys, the first dry etching comprising etching the surface of the substrate in a plasma comprising fluorine (F) radicals and oxygen (O) radicals, wherein the plasma comprises an excess of oxygen (O) radicals. The method may further include performing a second dry etching onto the surface texture thereby smoothening the surface texture, the second dry etching comprising chemical isotropic etching the surface texture, obtained after the first dry etching, in a plasma comprising fluorine (F) radicals, wherein the spikes are etched substantially faster than the valleys. | 03-15-2012 |
| 20120057163 | METHOD FOR FORMING A NANOSTRUCTURE PENETRATING A LAYER - A method for forming a nanostructure penetrating a layer and the device made thereof is disclosed. In one aspect, the device has a substrate, a layer present thereon, and a nanostructure penetrating the layer. The nanostructure defines a nanoscale passageway through which a molecule to be analyzed can pass through. The nanostructure has, in cross-sectional view, a substantially triangular shape. This shape is particularly achieved by growth of an epitaxial layer having crystal facets defining tilted sidewalls of the nanostructure. It is highly suitably for use for optical characterization of molecular structure, particularly with surface plasmon enhanced transmission spectroscopy. | 03-08-2012 |
| 20120045892 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A gate insulating film is formed on a semiconductor substrate having a first region in which a first conductivity type transistor is formed and a second region in which a second conductivity type transistor is formed. Next, a metal film and a first metal nitride film are sequentially formed on the gate insulating film. Next, part of each of the metal film and the first metal nitride film that is located in the second region is removed, thereby exposing part of the gate insulating film that is located in the second region. Next, a second metal nitride film made of a same metal nitride as the first metal nitride film is formed on the part of the gate insulating film that is located in the second region. | 02-23-2012 |
| 20120045879 | TUNNEL EFFECT TRANSISTORS BASED ON ELONGATE MONOCRYSTALLINE NANOSTRUCTURES HAVING A HETEROSTRUCTURE - Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these elongate monocrystalline nanostructure Si/Ge TFETs resulting in ultra-high on-chip transistor densities. | 02-23-2012 |
| 20120034762 | Method for Selective Deposition of a Semiconductor Material - A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect. | 02-09-2012 |
| 20120032848 | METHOD AND SYSTEM FOR ANALOG BEAMFORMING IN WIRELESS COMMUNICATION SYSTEMS - A method of analog beamforming in a wireless communication system is disclosed. The system has a plurality of transmit antennas and receive antennas. In one aspect, the method includes determining information representative of communication channels formed between a transmit antenna and a receive antenna of the plurality of antennas, defining a set of coefficients representing jointly the transmit and the receive beamforming coefficients, determining a beamforming cost function using the information and the set of coefficients, determining an optimized set of coefficients by exploiting the beamforming cost function, and separating the optimized set of coefficients into optimized transmit beamforming coefficients and optimized receive beamforming coefficients. | 02-09-2012 |
| 20120032234 | Antiphase Domain Boundary-Free III-V Compound Semiconductor Material on Semiconductor Substrate and Method for Manufacturing Thereof - Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface. The method further comprises at least partially filling the recessed region with a III-V compound semiconductor material overlaying the surface. | 02-09-2012 |
| 20120028401 | Methods for Manufacturing Arrays for CMOS Imagers - Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side. | 02-02-2012 |
| 20120025846 | ON-CHIP TESTING USING TIME-TO-DIGITAL CONVERSION - A method and system for testing the functionality of a through-silicon-via in an integrated circuit is disclosed. In one aspect, the functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. The comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter. | 02-02-2012 |
| 20120025841 | CAPACITANCE MEASUREMENT IN MICROCHIPS - A measurement system for determining the capacitance of a device-under-test in an integrated circuit is disclosed. In one aspect, the measurement system has a reference circuit and a test circuit. Each circuit has first and second diodes that are switched in accordance with a clock cycle to charge and discharge the associated circuit. A method takes average current measurements for each circuit at one voltage level and processes them so that the capacitance of a device-under-test connected to the test circuit can accurately and reliably be determined. Two voltage levels may be used and adjustments are made for voltage threshold of the diodes and also their resistance. | 02-02-2012 |
| 20120018784 | Method for Forming a Nickelsilicide FUSI Gate | 01-26-2012 |
| 20120013022 | METHOD FOR FORMING 3D-INTERCONNECT STRUCTURES WITH AIRGAPS - Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material. | 01-19-2012 |
| 20120013020 | MEMS Device Comprising a Hermetically Sealed Cavity and Devices Obtained Thereof - A MEMS device is disclosed comprising a cavity containing a MEMS component, the cavity being formed in a dielectric layer stack having a thickness t | 01-19-2012 |
| 20120007024 | Triplet Excitation Scavenging in Solid-State Organic Materials - The present invention is directed to solid state organic light emitting devices and to methods for triplet excitation scavenging in such devices. More particularly, the present invention relates to a method for substantially reducing a triplet population in a solid state organic material, the method comprising providing molecules exhibiting non-vertical triplet energy transfer in the solid state organic material or at a distance smaller than a triplet exciton diffusion length from the solid state organic material. | 01-12-2012 |
| 20120006981 | WAVEGUIDE INTEGRATED PHOTODETECTOR - A waveguide integrated photodetector ( | 01-12-2012 |
| 20120002207 | Method for Determining an Analyte in a Sample - In one aspect of the invention, a method or apparatus is described for determining concentration(s) of one or more analytes in a sample using plasmonic excitations. In another aspect, a method relates to designing systems for such concentration determination, wherein metallic nanostructures are used in combination with local electrical detection of such plasmon resonances via a semiconducting photodetector. In certain aspects, the method exploits the coupling of said metallic nanostructure(s) to a semiconducting photodetector, said detector being placed in the “metallic structure's” near field. Surface plasmon excitation can be transduced efficiently into an electrical signal through absorption of light that is evanescently coupled or scattered in a semiconductor volume. This local detection technique allows the construction of sensitive nanoscale bioprobes and arrays thereof. | 01-05-2012 |
| 20110317575 | METHOD AND APPARATUS FOR MULTI-USER MULTI-INPUT MULTI-OUTPUT TRANSMISSION - Embodiments of the present invention relate to methods and systems of transmitting data signals from at least one transmitting terminal with a spatial diversity capability to at least two receiving user terminals, each provided with spatial diversity receiving device. The methods and systems are useful, for example, in communication between terminals, e.g., wireless communication. In certain embodiments, transmission can be between a base station and two or more user terminals, wherein the base station and user terminals are each equipped with more than one antenna. | 12-29-2011 |
| 20110317486 | Methods for Operating a Semiconductor Device - Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body. | 12-29-2011 |
| 20110315951 | METHOD FOR FORMING A CATALYST SUITABLE FOR GROWTH OF CARBON NANOTUBES - The present disclosure is related to a method for forming a catalyst nanoparticle on a metal surface, the nanoparticle being suitable for growing a single nanostructure, in particular a carbon nanotube, the method comprising at least the steps of: providing a substrate, having a metal layer on at least a portion of the substrate surface, depositing a sacrificial layer at least on the metal layer, producing a small hole in the sacrificial layer, thereby exposing the metal layer, providing a single catalyst nanoparticle into the hole, removing the sacrificial layer. The disclosure is further related to growing a carbon nanotube from the catalyst nanoparticle. | 12-29-2011 |
| 20110313270 | NEURAL PROBE WITH MODULAR MICROELECTRODE - The present disclosure relates to a neural probe system comprising: a carrier, at least one planar microelectrode attached to the carrier, the planar microelectrode comprising a set of two or more conductive segments, the set being confined in an area of from 15 μm | 12-22-2011 |
| 20110313175 | 4, 4' DISUBSTITUTED 4H-CYCLOPENTADITHIOPHENE AND NEW METHODS FOR SYNTHESISING THE SAME - The present preferred embodiments relate to a method for the synthesis of a compound having the following general formula: | 12-22-2011 |
| 20110312056 | Plasma Membrane Isolation - The present invention relates to a population of monodisperse magnetic nanoparticles with a diameter between 1 and 100 nm which are coated with a layer with hydrophilic end groups. Herein the layer with hydrophilic end groups comprises an inner layer of monosaturated and/or monounsaturated fatty acids bound to said nanoparticles and bound to said fatty acids, an outer layer of a phospholipid conjugated to a monomethoxy polyethyleneglycol (PEG) comprising a hydrophilic end group, | 12-22-2011 |
| 20110309489 | METHOD FOR FORMING A DOPED REGION IN A SEMICONDUCTOR LAYER OF A SUBSTRATE AND USE OF SUCH METHOD - A method of forming a doped region in a semiconductor layer of a substrate by alloying with doping elements is disclosed. In one aspect, the method includes screen printing a paste layer of doping element paste to the substrate and firing the screen printed paste layer of doping element paste, wherein a highly pure doping element layer is applied to the semiconductor layer after which the paste layer is screen printed to the doping element layer. | 12-22-2011 |
| 20110308603 | METHOD FOR PASSIVATING A SILICON SURFACE - A method of passivating a silicon surface is disclosed. In one aspect, the method includes cleaning the silicon surface by subjecting the silicon surface to a sequence of steps wherein the final step is a chemical oxidation step resulting in a hydrophilic silicon surface. The method may also include drying the cleaned silicon surface using an advanced drying technique, and/or depositing an oxide layer on the silicon surface. | 12-22-2011 |
| 20110308598 | SOLUTION PROCESSING METHOD FOR FORMING ELECTRICAL CONTACTS OF ORGANIC DEVICES - A method for forming, on an organic semiconductor layer, an electrical contact layer comprising a metal, is disclosed. In one aspect, the method includes providing a charge collecting barrier layer on the organic semiconductor layer, providing a liquid composition comprising a precursor for the metal on the charge collecting barrier layer, and performing a sintering process. The charge collecting barrier layer is substantially impermeable to the components of the liquid composition. | 12-22-2011 |
| 20110305099 | HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM - A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line. | 12-15-2011 |
| 20110304987 | DEVICE FOR COOLING INTEGRATED CIRCUITS - The present disclosure is related to a device for cooling the surface of a semiconductor device such as an integrated circuit or the like, the cooling device comprising a plurality of channels ( | 12-15-2011 |
| 20110303280 | FABRICATION METHOD FOR INTERDIGITATED BACK CONTACT PHOTOVOLTAIC CELLS - A method for manufacturing interdigitated back contact photovoltaic cells is disclosed. In one aspect, the method includes providing on a rear surface of a substrate a first doped layer of a first dopant type, and providing a dielectric masking layer overlaying it. Grooves are formed through the dielectric masking layer and first doped layer, extending into the substrate in a direction substantially orthogonal to the rear surface and extending in a lateral direction underneath the first doped layer at sides of the grooves. Directional doping is performed in a direction substantially orthogonal to the rear surface, thereby providing doped regions with dopants of a second dopant type at a bottom of the grooves. Dopant diffusion is performed to form at the rear side of the substrate one of the emitter regions and back surface field regions between the grooves and the other at the bottom of the grooves. | 12-15-2011 |
| 20110291891 | METHOD AND SYSTEM FOR MIXED ANALOG/DIGITAL BEAMFORMING IN WIRELESS COMMUNICATION SYSTEMS - A method is disclosed for mixed analog/digital beamforming in a wireless communication system having transmit and receive antennas and analog front-ends connected to either the transmit antennas or the receive antennas. The method includes determining transmit and receive analog/digital beamforming coefficients by a) determining information representative of communication channels formed between a transmit antenna and a receive antenna, b) defining coefficients representing the transmit analog beamforming coefficients and the receive analog beamforming coefficients, c) determining a beamforming cost function using the information and the coefficients, the cost function taking into account the analog front-ends, d) computing an optimized set of transmit/receive analog beamforming coefficients by exploiting the cost function, e) deriving an estimate of the frequency responses of the communication channels using the information determined in process a, and f) deriving for each channel transmit/receive digital beamforming coefficients using the estimated frequency responses and the optimized beamforming coefficients. | 12-01-2011 |
| 20110291179 | Scalable Interpoly Dielectric Stacks With Improved Immunity to Program Saturation - A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer. | 12-01-2011 |
| 20110282625 | Time Interval Analyzing System and a Method Thereof - A time interval measuring system is disclosed. In one embodiment, the time interval measuring system includes a plurality of time interval analyzers, each having a resolution that differs from a resolution of at least one other time interval analyzer in the plurality of time interval analyzers. The plurality of time interval analyzers are configured to receive a first event signal representing a first event, receive a second event signal representing a second event, and generate digital first estimates representing a time difference between the first event and the second event. The time interval measuring system further includes a post-processing unit configured to receive the digital first estimates and combine the digital first estimates according to at least one algorithm to generate a digital second estimate representing the time difference between the first event and the second event having higher precision than each of the digital first estimates. | 11-17-2011 |
| 20110281541 | Reconfigurable Receiver Architectures - An adaptive front-end architecture for a receiver is disclosed. In one embodiment, the adaptive front-end architecture includes an input configured to receive an input signal and a linear low-noise amplifier connected to the input and configured to amplify the input signal to produce an amplified input signal. The adaptive front-end architecture further includes a first passive mixer arrangement configured to generate first a local oscillator signal and mix the first local oscillator signal with the amplified input signal to produce a first baseband output signal. The adaptive front-end architecture further includes a second passive mixer arrangement configured to generate a second local oscillator signal and mix the second local oscillator signal with the input signal to produce a second baseband output signal. The adaptive front-end architecture further includes a baseband impedance component configured to filter the first baseband signal and/or the second baseband signal using impedance translation. | 11-17-2011 |
| 20110278441 | Transparent Photonic Integrated Circuit - Photonic structures and methods of operating the photonic structures are disclosed. In one embodiment, the photonic structure includes a detector configured to detect radiation of a first wavelength range. The radiation of the first wavelength range is received from an external radiation guide, and the detector is substantially transparent to radiation of a second wavelength range that differs from the first wavelength range. The photonic structure further includes a coupling structure configured to free space couple out of the photonic structure radiation of the second wavelength range. The photonic structure further includes a guiding structure configured to optically guide the radiation of the second wavelength range through the detector. | 11-17-2011 |
| 20110272789 | Nanochannel Device and Method for Manufacturing Thereof - The present disclosure relates to a device comprising a mono-crystalline substrate, the mono-crystalline substrate having at least one recessed region which exposes predetermined crystallographic planes of the mono-crystalline substrate, the at least one recessed region further having a recess width and comprising a filling material and an embedded nanochannel, wherein the width, the shape, and the depth of the embedded nanochannel is determined by the recess width of the at least one recessed region and by the growth rate of the growth front of the filling material in a direction perpendicular to the exposed predetermined crystallographic planes. The present disclosure is also related to a method for manufacturing a nanochannel device. | 11-10-2011 |
| 20110270593 | METHOD AND APPARATUS FOR SIMULATING PHYSICAL FIELDS - In order to design on-chip interconnect structures in a flexible way, a CAD approach is advocated in three dimensions, describing high frequency effects such as current redistribution due to the skin-effect or eddy currents and the occurrence of slow-wave modes. The electromagnetic environment is described by a scalar electric potential and a magnetic vector potential. These potentials are not uniquely defined, and in order to obtain a consistent discretization scheme, a gauge-transformation field is introduced. The displacement current is taken into account to describe current redistribution and a small-signal analysis solution scheme is proposed based upon existing techniques for static fields in semiconductors. In addition methods and apparatus for refining the mesh used for numerical analysis is described. | 11-03-2011 |
| 20110269172 | Micro-Electrode Grid Array for Top and Bottom Recording from Samples - A mixed micro-fluidic multi-electrode grid array (MEGA) device ( | 11-03-2011 |
| 20110260211 | METHOD OF MANUFACTURING A LIGHT EMITTING DIODE - A method of manufacturing a light emitting diode is disclosed. In one aspect, the light emitting diode has a carrier, an active layer structure of III-nitride type materials, and a photonic crystal structure of III-nitride type materials. The active layer structure includes a first active layer with an n-type doped layer and a p-type doped layer and suitably a quantum well structure. The photonic crystal structure includes periodically distributed trenches or periodically distributed pillars spaced by one or more trenches. The photonic crystal structure includes an overgrowth layer within which a diameter of a trench gradually increases, and a directional photonic crystal layer in which the diameter of a trench is substantially constant. The diode may be formed in a method wherein the directional photonic crystal layer is provided on a three-dimensional pattern that exposes selected areas of the first surface of the substrate. | 10-27-2011 |
| 20110257501 | Bio-Hybrid Implant for Connecting a Neural Interface With a Host Nervous System - A bio-hybrid implant suitable for recording and/or stimulating cells, the implant comprising (a) at least one closed insulated chamber ( | 10-20-2011 |
| 20110253981 | METHOD OF MANUFACTURING A VERTICAL TFET - The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs. | 10-20-2011 |
| 20110252891 | Method and Apparatus for Determining Topography of an Object - A method for determining the topography of a static surface ( | 10-20-2011 |
| 20110249259 | Single Molecule Optical Spectroscopy in Solid-State Nanopores in a Transmission-Based Approach - Methods and apparatus in the field of single molecule sensing are described, e.g. for molecular analysis of analytes such as molecular analytes, e.g. nucleic acids, proteins, polypeptides, peptides, lipids and polysaccharides. Molecular spectroscopy on a molecule translocating through a solid-state nanopore is described. Optical spectroscopic signals are enhanced by plasmonic field-confinement and antenna effects and probed in transmission by plasmon-enabled transmission of light through an optical channel that overlaps with the physical channel. | 10-13-2011 |
| 20110248874 | TIME STAMP GENERATION - A circuit and method for providing a digital output indicative of the time at which an event occurred is disclosed. In one aspect, the circuit includes a fine timing circuit configured to determine in which sub-interval of a clock period the event occurred, and a correction circuit configured to correct an erroneous offset between a first and second clock signals in the fine timing circuit. The correction circuit includes a synch circuit configured to determine in which half of the clock period the event occurred so as to correct for erroneous offset in the fine timing circuit. | 10-13-2011 |
| 20110237020 | METHODS FOR CONTROLLING THE CRYSTALLINE NANOFIBRE CONTENT OF ORGANIC LAYERS USED IN ORGANIC ELECTRONIC DEVICES - The present invention relates in a first aspect to methods for producing a nanofibres-containing layer for use as an active layer in an organic electronic device. The method comprising the steps of:
| 09-29-2011 |
| 20110233792 | METHODS AND SYSTEMS FOR MATERIAL BONDING - A device and a method for realizing reliable electrical contacts at low temperature and low pressure between conducting materials on, for example, different substrates are disclosed. In one aspect, a rough and brittle intermetallic layer is formed on a conducting material on a first substrate. A soft solder material layer on the other substrate is used for contacting the brittle and rough intermetallic layer that will break. As the solder material is relatively soft, contact between the broken intermetallic layer and the solder material can be realized over a large portion of the surface area. At that stage, a second intermetallic layer is formed between the solder material and the first intermetallic layer realizing electrical contact. | 09-29-2011 |
| 20110233791 | METHOD FOR PERFORMING PARALLEL STOCHASTIC ASSEMBLY - A method of positioning at least 2 chips simultaneously on a substrate by parallel stochastic assembly in a first liquid is disclosed. In one aspect, the chips are directed to target sites on the substrate within the first liquid. The target sites are covered with a second liquid. The second liquid and the first liquid are immiscible. The chips are attracting the first liquid. A predetermined surface is chosen or treated on each chip such that it is selectively attracted by the second liquid and attracting the first liquid. | 09-29-2011 |
| 20110222856 | All-Optical 2R Regeneration - A method is provided for all-optical regeneration of intensity modulated optical signals. A DFB laser diode is selected such that it has a gain bandwidth comprising the signal wavelength, the signal wavelength being outside the stopband of the DFB laser diode. Furthermore, the DFB laser diode is selected such that it can have a bistable amplification characteristic for the signal wavelength showing a hysteresis with an ascending branch and a descending branch, the ascending branch located at a higher input power level than the descending branch. The DFB laser diode is driven such that it operates in the bistable amplification regime, the descending branch of the hysteresis curve located at an input power level above the lower power level of the optical signal pulses and the ascending branch of the hysteresis curve located at an input power level below the upper power level of the optical signal pulses. | 09-15-2011 |
| 20110210801 | TEMPERATURE MEASUREMENT SYSTEM COMPRISING A RESONANT MEMS DEVICE - A micromechanical resonator device and a method for measuring a temperature are disclosed. In one aspect, the device has a resonator body, an excitation module, a control module, and a frequency detection module. The resonator body is adapted to resonate separately in at least a first and a second predetermined resonance state, selected by applying a different bias, the states being of the same eigenmode but having a different resonance frequency, each resonance frequency having a different temperature dependence. The micromechanical resonator device may have a passive temperature compensated resonance frequency. | 09-01-2011 |
| 20110201098 | Polymer Replicated Interdigitated Electrode Array for Bio(Sensing) Applications - A sensor is disclosed. In one embodiment, the sensor includes an insulating substrate comprising a first zone, a second zone, and an intermediate zone, where the intermediate zone comprises a portion of the second zone that overlaps the first zone. The sensor further comprises a first electrode in the first zone that comprises a first plurality of fingers of a conductive material, a second electrode in the second zone that comprises a second plurality of fingers of the conductive material that are interdigitated with the first plurality of fingers, a plurality of three-dimensional isolation structures, and a plurality of shadow zones, wherein each shadow zone is adjacent to at least one isolation structure and is substantially free of conductive material. The plurality of isolation structures may comprises hills and/or channels. | 08-18-2011 |
| 20110193623 | Large Time Constant Steering Circuit and Instrumentation Amplifier Implementing Same - The present invention relates to a large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels. The present invention further relates to a slow steering current DAC comprising said large time constant steering circuit. The present invention further relates to an instrumentation amplifier device comprising a current balancing instrumentation amplifier for amplifying an input signal to an amplified output signal and a DC servo-loop for removing a DC-component from the input signal. The present invention further relates to an EEG acquisition ASIC comprising said instrumentation amplifier device. | 08-11-2011 |
| 20110180943 | Thin Film Wafer Level Package - Anchor designs for thin film packages are disclosed that, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are performed in order to obtain a desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti—TiN interlayer in the anchor region may be added. The ratio of the total SiGe—SiGe anchor area to the SiO | 07-28-2011 |
| 20110180886 | Method for Manufacturing a Micromachined Device and the Micromachined Device Made Thereof - Methods for manufacturing micromachined devices and the devices obtained are disclosed. In one embodiment, the method comprises providing a structural layer comprising an amorphous semiconductor material, forming a shielding layer on a first portion of the structural layer and leaving exposed a second portion of the structural layer, and annealing the second portion using a first fluence. The method further comprises removing the shielding layer, and annealing the first portion and the second portion using a second fluence that is less than half the first fluence. In an embodiment, the device comprises a substrate layer, an underlying layer formed on the substrate layer, and a sacrificial layer formed on only a portion of the underlying layer. The device further comprises a structural layer that is in contact with the underlying layer and comprises a first region annealed using a first fluence and a second region annealed using a second fluence. | 07-28-2011 |
| 20110178789 | RESPONSE CHARACTERIZATION OF AN ELECTRONIC SYSTEM UNDER VARIABILITY EFFECTS - A method and device for performing a characterization of a description of the composition of an electronic system in terms of components used are disclosed. Performances of the components are described by at least two statistical parameters and one deterministic parameter. In one aspect, the method includes selecting a plurality of design of experiments (DoE) points, performing simulations on the selected DoE points, thus obtaining system responses, and determining a response model using the selected DoE points and the system responses. Selecting the DoE points includes making a first selection of a reduced set of chosen DoE points for the statistical parameters representing the statistical properties of the many possible statistical parameter realizations, and making a second selection of DoE points for the deterministic parameter representing the possible limited set of values that such parameter can take. | 07-21-2011 |
| 20110175492 | Temperature Compensation Device and Method for MEMS Resonator - The present disclosure provides a device including a MEMS resonating element, provided for resonating at a predetermined resonance frequency, the MEMS resonating element having at least one temperature dependent characteristic, a heating circuit arranged for heating the MEMS resonating element to an offset temperature (T | 07-21-2011 |
| 20110169049 | Method for Doping Semiconductor Structures and the Semiconductor Device Thereof - A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer. | 07-14-2011 |
| 20110163615 | Patterned Electret Structures and Methods for Manufacturing Patterned Electret Structures - A patterned electret structure ( | 07-07-2011 |
| 20110163399 | Method for Manufacturing Microelectronic Devices and Devices According to Such Methods - A method is disclosed for manufacturing a sealed cavity in a microelectronic device, comprising forming a sacrificial layer at least at locations where the cavity is to be provided, depositing a membrane layer over the top of the sacrificial layer, patterning the membrane layer in at least two separate membrane layer blocks, removing the sacrificial layer through the membrane layer, and sealing the cavity by sealing the membrane layer, wherein patterning the membrane layer is performed after removal of the sacrificial layer. | 07-07-2011 |
| 20110156000 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device and the device resulted thereof is disclosed. In one aspect, the device has a heterogeneous layer stack of one or more III-V type materials, at least one transmission layer of the layer stack having a roughened or textured surface for enhancement of light transmission. The method includes (a) growing the transmission layer of a III-V type material, (b) providing a mask layer on the transmission layer, the mask layer leaving first portions of the transmission layer exposed, and (c) partially decomposing the first exposed portions of the transmission layer. Suitably redeposition occurs in a single step with decomposition, so as to obtain a textured surface based on crystal facets of a plurality of grown crystals. The resulting device has a light-emitting element. The transmission layer hereof is suitably present at the top side. | 06-30-2011 |
| 20110148414 | MAGNETIC RESONANCE IMAGING OF SINGLE DOMAIN NANOPARTICLES - A method and system are disclosed for gathering information about an object including single domain particles which have a diameter in the range of about 5 to 80 nm. In one aspect, a method includes generating a static magnetic field of less than about 0.1 Tesla on the object and generating an RF energy, pulsed or continuous wave, so as to generate electron paramagnetic resonance of the single domain particles. The method also includes detecting the electron paramagnetic resonance of the single domain particles in the form of an image of the object. The single domain particles may have a predetermined diameter and a predetermined saturation magnetization and the applied magnetic field may be such that the single domain particles reach a magnetization being at least about 10% of the saturation magnetization. The method may be used for detecting tags in an object and for activating tags. | 06-23-2011 |
| 20110147900 | DIELECTRIC LAYER FOR FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RE | 06-23-2011 |
| 20110140087 | SCALABLE QUANTUM WELL DEVICE AND METHOD FOR MANUFACTURING THE SAME - A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap. | 06-16-2011 |
| 20110127650 | Method of Manufacturing a Semiconductor Device and Semiconductor Devices Resulting Therefrom - A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed. | 06-02-2011 |
| 20110116735 | Retro-Reflective Structures - A photonic integrated circuit ( | 05-19-2011 |
| 20110113125 | METHOD FOR DETERMINING A DATA FORMAT FOR PROCESSING DATA AND DEVICE EMPLOYING THE SAME - A method for determining a data format for processing data to be transmitted along a communication path is disclosed. In one aspect, the method includes identifying at run-time an operational configuration based on received information on the conditions for communication on the communication path. The method may also include selecting according to the identified operational configuration, a data format for processing data to be transmitted among a plurality of predetermined data formats. | 05-12-2011 |
| 20110108850 | METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE - An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed. | 05-12-2011 |
| 20110103743 | METHOD AND SYSTEM FOR COUPLING RADIATION - The present invention relates to a coupler ( | 05-05-2011 |
| 20110102011 | METHOD AND DEVICE FOR TESTING TSVS IN A 3D CHIP STACK - A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry. | 05-05-2011 |
| 20110101370 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions. | 05-05-2011 |
| 20110097881 | Method of Forming Mono-Crystalline Germanium or Silicon Germanium - A method is presented for forming mono-crystalline germanium or silicon germanium in a trench. In an embodiment, the method comprises providing a substrate comprising at least one active region that is adjacent to two insulating regions, forming in the active region a trench having a width of less than 100 nm, and forming in the trench a fill layer at a temperature of less than 450° C. that comprises germanium or silicon germanium and substantially fills the trench. The method further comprises heating the fill layer to a temperature sufficient to substantially melt the fill layer and allowing re-crystallization of the substantially melted fill layer, thereby forming mono-crystalline germanium or silicon germanium in the trench. In an embodiment, the method further comprises forming a mono-crystalline germanium or silicon germanium fin by removing at least a portion of the insulating regions. The mono-crystalline fin may be comprised in a fin field-effect-transistor (finFET). | 04-28-2011 |
| 20110096309 | Method and System for Wafer Inspection - A method and system for evaluating a lithographic pattern obtained using multiple-patterning lithographic processing are presented. In one aspect, the method includes aligning a target design with a lithographic pattern. The target design may comprise a first design and a second design. The method further comprises identifying in the lithographic pattern a stitching region based on a region of overlap between the first design and the second design. The method further comprises determining for the identified stitching region whether a predetermined criterion is fulfilled. In some embodiments, determining whether a predetermined criterion is fulfilled may comprise determining a line or trench minimum width. Alternately or additionally, determining whether a predetermined criterion is fulfilled may comprise determining a stitching metric for the identified stitching region, and evaluating whether or not the stitching metric fulfills the predetermined criterion. | 04-28-2011 |
| 20110092834 | ANALOGUE SIGNAL PROCESSORS - An analogue signal processor (ASP) application-specific integrated circuit (ASIC) is disclosed. The ACIS can be used for remotely monitoring ECG signals of a subject that has reduced power consumption. In one aspect, the ASIC performs the functions of: ECG signal extraction with high resolution using ECG readout channel, feature extraction using a band-power extraction channel, adaptive sampling the ECG signals using an adaptive sampling analogue-to-digital converter, and impedance monitoring for signal integrity using an impedance monitoring channel. These functions enable the development of wireless ECG monitoring systems that have significantly lower power consumption but are more efficient that predecessor systems. In one embodiment, the ASP ASIC consumes 30 μW from a 2V supply with compression provided by adaptive sampling providing large reductions in power consumption of a wireless ECG monitoring system of which the ASP ASIC forms a part. | 04-21-2011 |
| 20110089572 | METHOD FOR FABRICATING THROUGH SUBSTRATE VIAS - A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips. | 04-21-2011 |
| 20110089469 | Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound - The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance. | 04-21-2011 |
| 20110088719 | Method and Apparatus for Cleaning a Semiconductor Substrate - Disclosed are systems and methods for cleaning semiconductor substrates, wherein a nucleation structure having nucleation sites is mounted facing a surface of the substrate to be cleaned. The substrate and structure are brought into contact with a cleaning liquid, which is subsequently subjected to acoustic waves of a given frequency. The nucleation template features easier nucleation formation than the surface that needs to be cleaned by, for example, causing the template to have a higher contact angle when in contact with the liquid than the substrate surface to be clean. Therefore, bubbles nucleate on the structure and not on the surface to be cleaned. | 04-21-2011 |
| 20110086507 | METHOD FOR PROVIDING OXIDE LAYERS - A method for providing an oxide layer on a semiconductor substrate is disclosed. In one aspect, the method includes obtaining a semiconductor substrate. The substrate may have a three-dimensional structure, which may comprise at least one hole. The method may also include forming an oxide layer on the substrate, for example, on the three-dimensional structure, by anodizing the substrate in an acidic electrolyte solution. | 04-14-2011 |
| 20110084313 | Methods for Manufacturing Dense Integrated Circuits - One inventive aspect relates to a method for forming integrated circuits and circuits obtained therewith. The method of forming a circuit pattern in a device layer of a semiconductor substrate comprises decomposing the circuit pattern in two constituent orthogonal subpatterns. The method further comprises transferring the pattern of a first subpattern to a hard mask layer overlying the device layer. The method further comprises transferring the pattern of the other subpattern to a photosensitive layer overlying the patterned hard mask layer. The method further comprises patterning the device layer using the patterned hard mask layer and the patterned photosensitive layer as a mask. The method further comprises removing the patterned hard mask layer and the patterned photosensitive layer. Furthermore memory or logic circuits obtained using the above technique are described. | 04-14-2011 |
| 20110084309 | METHOD FOR ENHANCING THE RELIABILITY OF A P-CHANNEL SEMICONDUCTOR DEVICE AND A P-CHANNEL SEMICONDUCTOR DEVICE MADE THEREOF - A method for forming a semiconductor device is disclosed. The device includes a control electrode on a semiconductor P-channel layer having at least a gate dielectric layer. The gate dielectric layer has an exponentially decreasing density of defect levels E | 04-14-2011 |
| 20110079860 | TUNNEL FIELD EFFECT TRANSISTOR WITH IMPROVED SUBTHRESHOLD SWING - The present disclosure provides a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region, a lowly doped up to undoped channel region being in contact with the drain region, the channel region having a longitudinal direction, a highly doped source region in contact with the channel region, the contact between the source region and the channel region forming a source-channel interface, a gate dielectric and a gate electrode covering along the longitudinal direction at least part of the source and channel regions, the gate electrode being situated onto the gate dielectric, not extending beyond the gate dielectric, wherein the effective gate dielectric thickness t | 04-07-2011 |
| 20110075970 | Integrated Photonics Device - The present invention relates to an integrated photonic device ( | 03-31-2011 |
| 20110075446 | Circuit for Converting a Pulsed Input Voltage to a DC Voltage - The present disclosure presents a circuit for converting a pulsed input voltage to a DC output voltage. The circuit comprises input nodes for receiving the pulsed input voltage and output nodes for outputting the DC output voltage. The circuit further comprises a first transistor and a second transistor connected between the input and the output nodes in a synchronous rectifier configuration. The first and second transistors each have a gate connected to a driving circuit configured for alternately charging the gates of the transistors whereby the driving circuit comprises an auxiliary circuit not directly connected to the input nodes and configured for providing a predetermined auxiliary supply voltage to the gates. In an embodiment, the auxiliary circuit comprises a buck DC-DC converter of which an input node is connected to the output nodes and of which an output node is connected to the gates. | 03-31-2011 |
| 20110069952 | Circuit for End-of-Burst Detection - A circuit for end-of-burst detection in a portion of a received bit stream is disclosed. The circuit comprises:
| 03-24-2011 |
| 20110069692 | DEVICE AND METHOD FOR PARALLELIZING MULTICARRIER DEMODULATION - A device for demodulating a stream of data symbols being part of a multicarrier data stream is disclosed. In one aspect, the device includes a platform capable of running processes in parallel. On the platform a parallel code is mapped for demodulating the data symbols. The parallel code is arranged for determining, from at least one previously processed symbol, information for demodulating a currently processed data symbol of the multicarrier data stream. The device may further includes a parallelization module for parallelizing symbols or groups of symbols of the stream of data symbols code according to a modulo-N symbol splitting of the stream of data symbols, wherein N denotes the number of processes that can run in parallel on the platform. The parallelization module is arranged for applying the parallelized stream to the parallel code. | 03-24-2011 |
| 20110068375 | MULTI-GATE SEMICONDUCTOR DEVICES WITH IMPROVED CARRIER MOBILITY - A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer. | 03-24-2011 |
| 20110066054 | METHOD AND ELECTRONIC MEDICAL DEVICE FOR SIMULTANEOUSLY MEASURING AN IMPEDANCE AND A BIOPOTENTIAL SIGNAL - A method and device is disclosed for continuously and simultaneously measuring an impedance signal and a biopotential signal on a biological subject's skin. In one aspect, the method includes attaching input and output electrodes to the biological subject's skin and applying a predetermined alternating current having a first frequency to the output electrodes for creating an alternating voltage signal over the input electrodes. The first frequency is above a predetermined minimum frequency. The method also includes measuring an input signal from the input electrodes which includes a biopotential signal and the alternating voltage signal. The method also includes extracting from the input signal the biopotential signal and the alternating voltage signal, and determining the impedance signal from the alternating voltage signal. The alternating voltage signal is extracted by amplifying and demodulating the input signal using a control signal having a frequency equal to the first frequency. | 03-17-2011 |
| 20110066053 | ADAPTIVE SAMPLING - A method and apparatus is disclosed for adaptively sampling an analogue signal to increase the sampling rate in the presence of high frequency content within the signal, for example, QRS complex of an ECG signal. In one aspect, a change in a derivative of the analogue signal is used to control a voltage-controlled oscillator to provide a clock signal for an analogue-to-digital converter. The change in the derivative is compared to an automatically controlled threshold value. The clock signal controls the sampling rate of the analogue-to-digital converter so that the sampling rate is increased from one level, where only P and T waves are present to another higher level when the QRS complex has been detected. | 03-17-2011 |
| 20110055836 | METHOD AND DEVICE FOR REDUCING POWER CONSUMPTION IN APPLICATION SPECIFIC INSTRUCTION SET PROCESSORS - A method and device for converting first program code into second program code, such that the second program code has an improved execution on a targeted programmable platform, is disclosed. In one aspect, the method includes grouping operations on data for joint execution on a functional unit of the targeted platform, scheduling operations on data in time, and assigning operations to an appropriate functional unit of the targeted platform. Detailed word length information, rather than the typically used approximations like powers of two, may be used in at least one of the grouping, scheduling or assigning operations. | 03-03-2011 |
| 20110051301 | Method for Designing Integrated Electronic Circuits Having Electrostatic Discharge Protection and Circuits Obtained Thereof - A method for designing an integrated electronic circuit ( | 03-03-2011 |
| 20110051300 | Method for Providing Wideband Electrostatic Discharge Protection and Circuits Obtained Therewith - An distributed electronic circuit ( | 03-03-2011 |
| 20110045662 | LOW-TEMPERATURE FORMATION OF LAYERS OF POLYCRYSTALLINE SEMICONDUCTOR MATERIAL - The present invention provides a method for forming a layer ( | 02-24-2011 |
| 20110044089 | Method for Manufacturing a Resistive Switching Memory Cell Comprising a Nickel Oxide Layer Operable at Low-Power and Memory Cells Obtained Thereof - A resistive switching non-volatile memory element is disclosed comprising a resistive switching metal-oxide layer sandwiched between and in contact with a top electrode and a bottom electrode, the resistive switching metal oxide layer having a substantial isotropic non-stoichiometric metal-to-oxygen ratio. For example, the memory element may comprise a nickel oxide resistive switching layer sandwiched between and in contact with a nickel top electrode and a nickel bottom electrode whereby the ratio oxygen-to-nickel of the nickel oxide layer is between 0 and 0.85. | 02-24-2011 |
| 20110039380 | Method for Forming a Floating Gate Non-Volatile Memory Cell - Method for manufacturing a non-volatile memory comprising at least one array of memory cells on a substrate of a semiconductor material, the memory cells being self-aligned to and separated from each other by STI structures, the memory cells comprising a floating gate having an inverted-T shape in a cross section along the array of memory cells, wherein the inverted T shape is formed by oxidizing an upper part of the sidewalls of the floating gates thereby forming sacrificial oxide, and subsequently removing the sacrificial oxide simultaneously with further etching back the STI structures. | 02-17-2011 |
| 20110037179 | SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. In one aspect, the package includes a base frame and a wiring substrate mounted on the base frame. The base frame has two pieces made of a material with respectively a first and a second coefficient of thermal expansion and connected to each other via resilient connecting structures. The wiring substrate has electric wiring tracks providing the electric connection between first and second bond pads, provided for being electrically connected to bond pads on respectively a die and a printed wiring board. The electrical wiring tracks have flexible parts provided to expand and contract along with the resilient connecting structures. | 02-17-2011 |
| 20110032065 | Two Layer Transformer - One aspect of the invention relates to a symmetrical transformer with a stacked coil structure comprising two coils each having at least two turns, said coils being located in two conductive planes. The structure comprises four identical basic elements, each basic element providing a conductive path for part of said coils. The terminals of the transformer are located at opposite sites of the structure so that the structure can be easily connected in a chain. | 02-10-2011 |
| 20110027967 | METHOD FOR INSERTION BONDING AND DEVICE THUS OBTAINED - A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at least one protrusion at the front main surface. The device includes a second substrate having a front main surface and at least one hole extending from the front main surface into the second substrate. The protrusion of the first substrate is inserted into the hole of the second substrate. The hole is formed in a shape wherein the width is reduced in the depth direction and wherein the width of at least a part of the hole is smaller than the width of the protrusion at the location of the metal portion thereof. The protrusion is deformed during insertion thereof in the hole to provide a bond between the part of the hole and the metal portion. | 02-03-2011 |
| 20110015866 | Active Interface Device - An active interface device including a transducer or sensor array having a plurality of transducers or sensors arranged to transform a cell activity into an electrical signal, at least one detection unit for detecting the electrical signal(s), at least one recording unit for recording the electrical signal(s), comprising a plurality of recording channels arranged for being routed to the transducers or sensors, and at least one control unit. The control unit is arranged for addressing the transducers or sensors to the detection unit(s), for activating transducers or sensors, and for routing the recording channels to activated transducers or sensors. | 01-20-2011 |
| 20110013874 | Method for Effective Refractive Index Trimming of Optical Waveguiding Structures and Optical Waveguiding Structures - A method for trimming an effective refractive index of optical waveguiding structures made for example in a high refractive index contrast material system. By compaction of cladding material in a compaction area next to patterns or ridges that are formed in the core material for realizing an optical waveguiding structure, the effective index of refraction of the optical waveguiding structure can be trimmed. Thus, the operating wavelength of an optical component comprising such an optical waveguiding structure can be trimmed. An optical waveguide structure thus obtained is also disclosed. | 01-20-2011 |
| 20110010136 | Micro Electromechanical Device With Stress and Stress Gradient Compensation - Methods for designing a micro electromechanical device are disclosed. In one embodiment, the method comprises extending a floating element between a first anchor point and a second anchor point. The floating element includes a predetermined reference portion. The method further comprises determining a first location for a first stress relieving element on a first flexible section located between the first anchor point and the reference point, and determining a second location for a second stress relieving element on a second flexible section located between the second anchor point and the reference point. The method additionally comprises placing the first and second stress relieving elements at the first and second determined locations, respectively, thereby causing the reference portion to be located within a predetermined reference plane while in at least one predetermined state. | 01-13-2011 |
| 20110008954 | INSULATING BUFFER FILM AND HIGH DIELECTRIC CONSTANT SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode. | 01-13-2011 |
| 20110007851 | METHOD AND DEVICE FOR MULTIPLE INPUT-MULTIPLE OUTPUT DETECTION - A method and device for detecting a symbol transmitted over a communication channel in a multiple input-multiple output communication system are disclosed. In one aspect, the method includes receiving a symbol transmitted over a communication channel of a multiple input-multiple output communication system. The method may also include searching a subset of possible transmitted symbols, the subset having a predetermined size dependent on properties of the communication channel. The method may also include deciding to which symbol of the subset the received symbol corresponds. | 01-13-2011 |
| 20110006431 | METHOD FOR ALIGNING AND BONDING ELEMENTS AND A DEVICE COMPRISING ALIGNED AND BONDED ELEMENTS - The present invention is related to a method for aligning and bonding a first element ( | 01-13-2011 |
| 20110006406 | FABRICATION OF POROGEN RESIDUES FREE AND MECHANICALLY ROBUST LOW-K MATERIALS - A method is provided for producing a porogen-residue-free ultra low-k film with porosity higher than 50% and a high elastic modulus above 5 GPa. The method starts with depositing a SiCOH film using Plasma Enhanced Chemical Vapor Deposition (PE-CVD) or Chemical Vapor Deposition (CVD) onto a substrate and then first Performing an atomic hydrogen treatment at elevated wafer temperature in the range of 200° C. up to 350° C. to remove all the porogens and then performing a UV assisted thermal curing step. | 01-13-2011 |
| 20110005582 | PHOTOVOLTAIC CELLS HAVING METAL WRAP THROUGH AND IMPROVED PASSIVATION - A photovoltaic device is disclosed. In one aspect, the device is formed in a semiconductor substrate. It has a radiation receiving front surface and a rear surface. The device may have a first region of one conductivity type, a second region with the opposite conductivity type adjacent to the front surface, and an antireflection layer. The rear surface is covered by a dielectric layer covering also an inside surface of the via. The front surface has current collecting conductive contacts. The rear surface has conductive contacts extending through the dielectric. A conductive path is in the via for photogenerated current from the front surface. By having the dielectric all over, no aligning and masking is needed. The same dielectric serves to insulate, provide thermal protection, and helps in surface and bulk passivation. It also avoids the need for a junction region near the via, hence reducing unwanted recombination currents. | 01-13-2011 |
| 20110005455 | Method for Manufacturing a Mono-Crystalline Layer on a Substrate - The present invention is related to a method for growing a layer of a mono-crystalline material on a substrate comprising
| 01-13-2011 |
| 20110000504 | Method and Apparatus for Controlling Optimal Operation of Acoustic Cleaning - Methods and apparatuses for cleaning a surface of a substrate are presented. The method comprises positioning a substrate at a controllable distance from a piezoelectric transducer, supplying a cleaning liquid between the substrate and the transducer, applying an oscillating acoustic force to the cleaning liquid by actuating the transducer, and moving the transducer relative to the substrate. The method further comprises, while moving the transducer relative to the substrate, measuring a value that indicates a distance between a surface of the substrate and the transducer, comparing the measured value to a desired value, and adjusting the distance between the surface and the transducer so that the measured value is maintained substantially equal to the desired value. The measured value may be the distance between the surface of the substrate and the transducer or a phase shift between an alternating current and voltage applied to the transducer. | 01-06-2011 |
| 20100328120 | Comparator Based Asynchronous Binary Search A/D Conveter - The present invention is related to an analog-to-digital converter circuit ( | 12-30-2010 |
| 20100327319 | CONTROL OF TUNNELING JUNCTION IN A HETERO TUNNEL FIELD EFFECT TRANSISTOR - Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g. Si) channel and allows to contain the whole doping (e.g. B atoms) entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current. | 12-30-2010 |
| 20100327316 | Method for Manufacturing an III-V Engineered Substrate and the III-V Engineered Substrate Thereof - Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices. | 12-30-2010 |
| 20100323472 | METHOD FOR THE PRODUCTION OF THIN SUBSTRATES - A method is provided for producing a thin substrate with a thickness below 750 microns, comprising providing a mother substrate, the mother substrate having a first main surface and a toughness; inducing a stress with predetermined stress profile in at least a portion of the mother substrate, said portion comprising the thin substrate, the induced stress being locally larger than the toughness of the mother substrate at a first depth under the main surface; such that the thin substrate is released from the mother substrate, wherein the toughness of the mother substrate at the first depth is not lowered prior to inducing the stress. The method can be used in the production of, for example, solar cells. | 12-23-2010 |
| 20100323173 | FABRICATION OF CONDUCTING OPEN NANOSHELLS - A method involving ion milling is demonstrated to fabricate open-nanoshell suspensions and open-nanoshell monolayer structures. Ion milling technology allows the open-nanoshell geometry and upward orientation on substrates to be controlled. Substrates can be fabricated covered with stable and dense open-nanoshell monolayer structures, showing nanoaperture and nanotip geometry with upward orientation, that can be used as substrates for SERS-based biomolecule detection. | 12-23-2010 |
| 20100322555 | Grating Structures for Simultaneous Coupling to TE and TM Waveguide Modes - Disclosed are an integrated optical coupler, and a method of optically coupling light, between an optical element and at least one integrated optical waveguide. The optical coupler includes a grating structure and is adapted for coupling light to waveguide modes with different polarization with low polarization dependent loss. For example, polarization dependent loss may be smaller than 0.5 dB. The waveguide modes may include a Transverse Electric (TE) waveguide mode and a Transverse Magnetic (TM) waveguide mode. The optical coupler may further include a two-dimensional grating structure adapted for providing polarization splitting for a first optical signal of a first predetermined wavelength and for coupling both polarizations forward or backward. | 12-23-2010 |
| 20100321072 | Device and Method for Signal Detection in a TDMA Network - The present invention is related to a circuit ( | 12-23-2010 |
| 20100320606 | Method for Forming MEMS Devices Having Low Contact Resistance and Devices Obtained Thereof - The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted. | 12-23-2010 |
| 20100316166 | METHOD FOR GENERATING A DATA BLOCK FOR TRANSMISSION USING A CPM SCHEME - A method for generating a data block for transmission using a continuous phase modulation scheme is disclosed. In one aspect, the method includes inserting payload data in the data block, the payload data having a plurality of payload symbols, each involving an state change in a continuous phase modulation waveform generated from the data block in one of two opposite directions. It may include inserting state compensation data in the data block for cancelling out the state changes, such that the waveform has an end state at the end of the data block equal to a begin state at the beginning of the data block. The state compensation data is determined by determining from the state changes an overall state change caused by the payload data over the waveform and by selecting a set of compensation symbols for the state compensation data on the basis of the overall state change. | 12-16-2010 |
| 20100316107 | FREQUENCY DOMAIN EQUALIZATION METHOD FOR CONTINUOUS PHASE MODULATED SIGNALS - A method for frequency domain equalization of a cyclic CPM signal received via a channel is disclosed. In one aspect, the method includes representing the received cyclic CPM signal as a matrix model comprising a channel matrix representing influence of the channel, separate from a Laurent pulse matrix and a pseudocoefficient matrix respectively representing Laurent pulses and pseudocoefficients determined by Laurent decomposition of the received cyclic CPM signal. The method may further include applying a channel equalizer on the separate channel matrix and after the equalization. It may further include demodulating the received cyclic CPM signal by the matrix model, the demodulation exploiting known correlation properties of the Laurent pulses and the pseudocoefficients. | 12-16-2010 |
| 20100302961 | METHOD FOR RESOLVING NETWORK CONTENTION - A method for resolving network contention in a wireless network having a plurality of communication devices is disclosed. In one aspect, the method includes determining a set of initial values of at least three parameters of a first device of the plurality, at least one of the at least three parameters being indicative of the transmit power of that first device. The method further includes determining, given the set of initial values, a gain measure obtainable by changing the set of initial values of the at least three parameters into a set of updated values, the gain measure taking into account the parameter indicative of the transmit power. The method further includes deciding according to the determined gain measure on using the set of updated values of the at least three parameters for the first device. Other inventive aspects relate to systems and software stored on computer readable media. | 12-02-2010 |
| 20100301946 | Switchable Multiband LNA Design - A low noise amplifying (LNA) circuit comprising an amplifying section ( | 12-02-2010 |
| 20100301320 | METHOD FOR FABRICATING ORGANIC OPTOELECTRONIC DEVICES - An organic optoelectronic device and a method for manufacturing the same are disclosed. In one aspect, the device has a stack of layers. The stack includes a buffer layer and a first organic semiconductor layer adjacent to the buffer layer at a first side of the buffer layer. The buffer layer includes at least one transition metal oxide doped with a metal. | 12-02-2010 |
| 20100295159 | Method for Formation of Tips - The present invention provides a method ( | 11-25-2010 |
| 20100284860 | MOLECULES SUITABLE FOR BINDING TO A METAL LAYER FOR COVALENTLY IMMOBILIZING BIOMOLECULES - An article is provided for immobilizing functional organic biomolecules (e.g. proteins, DNA, and the like) through a covalent bond to a thiolate or disulfide monolayer to a metal surface wherein an extra activation step of the surface layer or an activation step of the functional biomolecules or bioreceptors could be avoided. The monolayer can contain, but is not limited to, two moieties. One has a group that resists nonspecific adsorption and another has a group that directly (without activation) reacts with functional groups on the biomolecules. In addition, poly(ethylene oxide) groups are incorporated in the monolayer surfaces to resist the nonspecific adsorption and to enhance the specific affinity interactions. A sensor device including these monolayers is also provided to perform reproducible, sensitive, specific and stable bioanalysis. | 11-11-2010 |
| 20100284457 | CROSS-LAYER OPTIMIZATION FOR TRANSMISSION OF VIDEO CODEC OVER WIRELESS NETWORKS - A method and system for configuring at least one video codec at run-time are disclosed. A major limitation for wireless video communication on portable devices is the limited energy budget. In one aspect, the disclosed method and system minimize the energy cost of the two main energy consumers in such a wireless video device, i.e., the energy for video encoding and wireless communication tasks, via a cross-layer approach that explores the trade-off between coding and communication energies. | 11-11-2010 |
| 20100283649 | Sigma-delta-based analog-to-digital converter - An analog to digital converting device is proposed for generating a digital output signal of an RF analog input signal. The device comprises a first analog to digital converter stage, a mixer, a second analog to digital converter stage and a digital filter. The first analog to digital converter stage generates a first and a second output signal. The first output signal is inputted in the filtering means. The second output signal is being down-converted to a signal with an intermediate frequency or DC. Thereafter, this down-converted signal is being fed to the second analog to digital converter stage. The digital output signal of this second stage is further processed together with the first digital output signal in the digital filter to a digital signal representative of the analog input signal. | 11-11-2010 |
| 20100278484 | Waveguide Coupling Probe and Methods for Manufacturing Same - A waveguide coupling probe ( | 11-04-2010 |
| 20100273323 | PRE-TREATMENT METHOD TO INCREASE COPPER ISLAND DENSITY OF CU ON BARRIER LAYERS - A method for producing on-chip interconnect structures on a substrate is provided, comprising at least the steps of providing a substrate and depositing a ruthenium-comprising layer on top of said substrate, and then performing a pre-treatment of the Ru-comprising layer electrochemically with an HBF | 10-28-2010 |
| 20100268918 | ASIP ARCHITECTURE FOR EXECUTING AT LEAST TWO DECODING METHODS - A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system includes at least one application specific processor having an instruction set having arithmetic operators excluding multiplication, division and power. The processor is selected for execution of approximations of each of the at least two data decoding methods. The system also includes at least a first memory unit, e.g. background memory, for storing data. The system also includes a transfer unit for transferring data from the first memory unit towards the at least one programmable processor. The transfer unit includes a data shuffler. The system may also include a controller for controlling the data shuffler independent from the processor. | 10-21-2010 |
| 20100264538 | METHOD FOR PRODUCING ELECTRICAL INTERCONNECTS AND DEVICES MADE THEREOF - A method for the fabrication of electrical interconnects in a substrate is disclosed. In one aspect, the method includes providing a substrate having a first main surface. The method may further include producing a ring structure in the substrate from the first main surface, which surrounds an inner pillar structure and has a bottom surface. The method may further include filling the ring structure with a dielectric material. The method may further include providing a conductive inner pillar structure, thereby forming an interconnect structure, which forms an electrical path from the bottom surface up until the first main surface. This conductive inner pillar structure can for example be provided by removing the inner pillar structure leaving a pillar vacancy and partially filling the vacancy with a conductive material. The dielectric material may be applied in liquid phase. | 10-21-2010 |
| 20100250187 | METHOD AND SYSTEM FOR ANALYZING PERFORMANCE METRICS OF ARRAY TYPE CIRCUITS UNDER PROCESS VARIABILITY - A method is disclosed for analyzing a performance metric of an array type electronic circuit under process variability effects. The electronic circuit has an array with a plurality of array elements and an access path being a model of the array type electronic circuit. The model includes building blocks having all hardware to access one array element in the array. Each building block has at least one basic element. In one aspect, the method includes deriving statistics of the access path due to variations in the building blocks under process variability of the basic elements, and deriving statistics of the full array type electronic circuit by combining the results of the statistics of the access path under awareness of the array architecture. | 09-30-2010 |
| 20100238449 | METHOD AND APPARATUS FOR DETERMINING THE JUNCTION DEPTH OF A SEMICONDUCTOR REGION - A method of determining a value of a depth of a semiconductor junction of a substrate using a photomodulated optical reflectance measurement technique is disclosed. In one aspect, the method includes obtaining a substrate which has at least a first region including the semiconductor junction. The method further includes obtaining a reference region. the method further includes performing at least one sequence of: a) selecting a set of measurement parameters for the photomodulated optical reflectance measurement, b) measuring on the at least a first region a first optical signal representative of the substrate with the semiconductor junction using the selected set of parameters, c) measuring on the reference region a second optical signal using the selected set of parameters, and d) determining the ratio of the first optical signal to the second optical signal, and thereafter extracting from the ratio the depth of the semiconductor junction. | 09-23-2010 |
| 20100230668 | Organic Light-Emitting Device with Field-Effect Enhanced Mobility - A two-terminal organic light-emitting device structure is presented with low absorption losses and high current densities. Light generation and emission occur at a predetermined distance from any metallic contact, thereby reducing optical absorption losses. High current densities and thus high emitted light intensity are achieved by combining two types of conduction in one device: by combining space charge limited conduction and field-effect conduction or by combining ohmic conduction and field-effect conduction, thereby optimizing the current densities. This results in a very high local concentration of excitons and therefore a high light intensity, which can be important for applications such as organic lasers, and more in particular electrically pumped organic lasers. | 09-16-2010 |
| 20100224215 | Method for Reducing the Damage Induced by a Physical Force Assisted Cleaning - Disclosed is a method for performing a physical force-assisted cleaning process on a patterned surface of a substrate, including providing a substrate having at least one patterned surface, supplying a cleaning liquid to the patterned surface, and applying a physical force to the cleaning liquid in contact with the patterned surface, whereby the physical force leads to bubble formation in the cleaning liquid. Furthermore, and prior to applying the physical force, an additive is supplied to the surface, and the additive is maintained in contact with the surface for a given time, the additive and the time being chosen so that a substantially complete wetting of the surface by the cleaning liquid is achieved. | 09-09-2010 |
| 20100222695 | Autonomous Wireless System for Evoked Potential Measurements - The present invention provides a Vestibular Evoked Myogenic Potential monitoring system comprising an autonomous integrated system. The integrated system comprises an output being arranged for transferring a stimulation signal via an actuator to an equilibrium organ of a person, a processing and controlling block having an integrated radio and antenna, and an array of electrodes being attachable in the vicinity of at least one muscle of said person and being arranged for recording the responsive signal and for transferring this signal to the processing and controlling block. The processing and controlling block of the integrated system is arranged for generating a stimulus, for storing and processing the recorded signals, and for sending the processed data via a WL link to a processor. | 09-02-2010 |
| 20100219481 | METHOD FOR MANUFACTURING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF - A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack. | 09-02-2010 |
| 20100216308 | METHOD FOR ETCHING 3D STRUCTURES IN A SEMICONDUCTOR SUBSTRATE, INCLUDING SURFACE PREPARATION - A method is provided for producing 3D structures in a semiconductor substrate using Deep Reactive Ion Etching (DRIE), comprising at least the steps of: providing a substrate, and then grinding the backside of the substrate in order to achieve a thinned substrate, wherein extrusions and native oxides are left after said grinding step, and then performing a surface treatment selected from the group consisting of a wet etching step and a dry etching step in order to remove at least said native oxides and extrusions on the surface of said backside of the substrate which are causes for the grass formation during subsequent etching, and then performing deep reactive ion etching in order to achieve 3D vias. | 08-26-2010 |
| 20100210073 | Method for Encapsulating a Device in a Microcavity - Manufacturing a semiconductor device involves forming ( | 08-19-2010 |
| 20100207177 | METHOD FOR PRODUCING A COPPER CONTACT - A method for producing a contact through the pre-metal dielectric (PMD) layer of an integrated circuit, between the front end of line and the back end of line, and the device produced thereby are disclosed. The PMD layer includes oxygen. In one aspect, the method includes producing a hole in the PMD, depositing a conductive barrier layer at the bottom of the hole, depositing a CuMn alloy on the bottom and side walls of the hole, filling the remaining portion of the hole with Cu. The method further includes performing an anneal process to form a barrier on the side walls of the hole, wherein the barrier has an oxide including Mn. The method further includes performing a CMP process. | 08-19-2010 |
| 20100204415 | SELFASSEMBLED GRAFTED POLYMERIC LAYER FOR USE IN BIOSENSOR TECHNOLOGY - A water soluble functional polyethylene glycol-grafted polysiloxane polymer comprising a polysiloxane backbone and polyethylene glycol side chains is provided having the general formula: | 08-12-2010 |
| 20100191349 | METHOD AND SYSTEM FOR OPERATING IN HARD REAL TIME - A method for managing the operation of an electronic system by taking into account various cost constraints of the system is disclosed. In one aspect, the method includes selecting a working mode for a plurality of tasks in a pro-active way using predictive control mechanism while guaranteeing hard real time constraints. The system is operated at the selected working mode for the corresponding tasks. | 07-29-2010 |
| 20100189402 | Method for Effective Refractive Index Trimming of Optical Waveguiding Structures and Optical Waveguiding Structures - A method for trimming an effective refractive index of optical waveguiding structures made for example in a high refractive index contrast material system. By compaction of cladding material in a compaction area next to patterns or ridges that are formed in the core material for realizing an optical waveguiding structure, the effective index of refraction of the optical waveguiding structure can be trimmed. Thus, the operating wavelength of an optical component comprising such an optical waveguiding structure can be trimmed. An optical waveguide structure thus obtained is also disclosed. | 07-29-2010 |
| 20100186006 | PROGRAMMABLE DEVICE FOR SOFTWARE DEFINED RADIO TERMINAL - A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the scalar cluster. Each of the at least two vector clusters provides a vector data path and a vector register file and is arranged for executing at least one vector instruction different from vector instructions performed by any other vector cluster of the at least two vector clusters. | 07-22-2010 |
| 20100180513 | METHOD FOR IMPROVING MECHANICAL PROPERTIES OF POLYMER PARTICLES AND ITS APPLICATIONS - A method for improving the mechanical hardness of polymer particles is provided, the method comprising subjecting the polymer particles to a thermal cycle of heating and subsequently cooling. The method is applicable for use with combinations of preferably three monomers, the monomers having hydrophilic and hydrophobic groups in their polymer chain in order to achieve preferential orientation of the polymer chains in a polar solvent after applying the heating cycles of the invention (for example, but not limited to, polymethylmethacrylate and polystyrene based terpolymers and copolymers). Polymeric abrasives used in slurry compositions for polishing copper and their use in a chemical mechanical polishing method are also provided. | 07-22-2010 |
| 20100178810 | Connecting Scheme for Orthogonal Assembly of Microstructures - In the present disclosure a device for sensing and/or actuation purposes is presented in which microstructures ( | 07-15-2010 |
| 20100176421 | DAMASCENE CONTACTS ON III-V CMOS DEVICES - A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 μm and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device. | 07-15-2010 |
| 20100173127 | METHOD FOR PRODUCING A CRYSTALLINE GERMANIUM LAYER ON A SUBSTRATE - The present invention provides a method for providing a crystalline germanium layer on a crystalline base substrate having a crystalline surface. The method comprises cleaning the base substrate for removing contaminants and/or native oxides from the surface, providing an amorphous germanium layer on the surface of the base substrate while exposing to the base substrate to a hydrogen source such as e.g. a hydrogen plasma, a H | 07-08-2010 |
| 20100171025 | WAVELENGTH-SENSITIVE DETECTOR WITH ELONGATE NANOSTRUCTURES - A wavelength-sensitive detector is provided that is based on elongate nanostructures, e.g. nanowires. The elongate nanostructures are parallel with respect to a common substrate and they are grouped in at least first and second units of a plurality of parallel elongate nanostructures. The elongate nanostructures are positioned in between a first and second electrode, the first and second electrodes lying respectively in a first and second plane substantially perpendicular to the plane of substrate, whereby all elongate nanostructures in a same photoconductor unit are contacted by the same two electrodes. Circuitry is added to read out electrical signals from the photoconductor units. The electronic density of states of the elongate nanostructures in each unit is different, because the material, of which the elongate nanostructures are made, is different or because the diameter of the elongate nanostructures is different. Each unit of elongate nanostructures therefore gives a different response to incident photons such that wavelength-specific information can be derived with the device. | 07-08-2010 |
| 20100167446 | Method for Manufacturing a Junction - The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction. | 07-01-2010 |
| 20100163870 | Structure and Method for Testing MEMS Devices - A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a plane, the at least one structure being clamped at at least one side. The method further includes exerting a force, such as a mechanical force, on the at least one structure. The force may have a predetermined amplitude and a component perpendicular to the substrate. Still further, the method includes determining the deflection of the at least one structure perpendicular to the plane of the substrate, and correlating the deflection of the at least one structure to the presence of a sacrificial layer between the substrate and the structure. | 07-01-2010 |
| 20100159676 | Method For Manufacturing A Mono-Crystalline Semiconductor Layer on a Substrate - The described system relates to a method for forming a layer of a mono-crystalline semiconductor material on a substrate comprising providing a substrate, growing epitaxially a template comprising at least one monolayer of a semiconductor material on the substrate, thereafter depositing an amorphous layer of said semiconductor material on the template, and performing a thermal treatment or a laser anneal, thereby converting substantially all of the amorphous layer of the semiconductor material into a mono-crystalline layer of said semiconductor material. According to an embodiment, the semiconductor material is Ge, and the substrate is a Si substrate. The template is preferably a few monolayers thick. | 06-24-2010 |
| 20100156447 | Method for Calibrating a Transmission Line Pulse Test System - Calibration method for calibrating transient behaviour of a TLP test system. The system comprises a TLP generator, probe needles, nominally impedance matched transmission lines and measurement equipment, connected between the transmission lines and the TLP generator, for detecting transient behaviour of a device under test by simultaneously capturing voltage and current waveforms as a result of generated pulses. The calibration method comprises (a) applying the TLP test system on an open and capturing first voltage and current waveforms; (b) applying the TLP test system on a calibration element having a known finite impedance and a known transient response and capturing second voltage and current waveforms; (c) transforming the captured first and second current and voltage waveforms to the frequency domain, and (d) determining calibration data for the transient behaviour of the TLP test system on the basis of the transformed first and second voltage and current waveforms. | 06-24-2010 |
| 20100155687 | METHOD FOR MANUFACTURING A RESISTIVE SWITCHING MEMORY DEVICE AND DEVICES OBTAINED THEREOF - A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices. | 06-24-2010 |
| 20100153033 | JUNCTION-PHOTOVOLTAGE METHOD AND APPARATUS FOR CONTACTLESS DETERMINATION OF SHEET RESISTANCE AND LEAKAGE CURRENT OF SEMICONDUCTOR - A junction-photovoltage method and apparatus for contactless determination of an electrical/physical parameter of a semiconductor structure having at least one p-n junction located at a surface is disclosed. In one aspect, the method includes illuminating the surface with the p-n junction with a light beam of a first wavelength to create excess carriers at the surface. The method also includes modulating the light intensity of the light beam at a single predefined frequency. The method also includes determining a first photo-voltage at a first position inside the illuminated area and a second photo-voltage at least a second position outside the illuminated area. The method also includes calculating an electrical/physical parameter of the semiconductor structure based on the first and second photo-voltage. | 06-17-2010 |
| 20100142824 | METHOD AND APPARATUS FOR REAL-TIME/ON-LINE PERFORMING OF MULTI VIEW MULTIMEDIA APPLICATIONS - A method and apparatus for real-time/on-line performing of multi-view multimedia applications are disclosed. In one aspect, a method of computing a disparity value of a pixel includes computing from two input images a plurality of first costs for a pixel, each cost associated with a region selected from a plurality of regions a first type, the regions covering the pixel and being substantially equal in size and shape. The method also includes computing from the first costs a plurality of second costs each associated with a region selected from a plurality of regions of a second type, the regions of the second type covering the pixel, at least some of the regions of the second type having a substantially different size and/or shape. The method further includes selecting from the second costs the minimal cost and selecting the corresponding disparity value as the disparity value. | 06-10-2010 |
| 20100142105 | Bidirectional ESD Power Clamp - The disclosed method and device relates to a bidirectional ESD power clamp, comprising a semiconductor structure (BigNFET; BigPFET) having a conductive path connected between first and second nodes and having a triggering node via which the conductive path can be triggered. An ESD transient detection circuit is connected between the first and second nodes and to the triggering node and comprises a first part for detecting an occurrence of a first ESD transient on the first node. The semiconductor structure is provided on an insulator substrate, such that a parasitic conductive path between said first and second nodes via the substrate is avoided. The ESD transient detection circuit further comprises a second part for detecting an occurrence of a second ESD transient on the second node. | 06-10-2010 |
| 20100140619 | PHOTOVOLTAIC DEVICE - The present invention is related to a photovoltaic device, the device comprising a first layer of a first semiconductor material of a first conductivity type, a second layer of a second semiconductor material of the opposite conductivity type of the first layer, and a third layer of a third porous semiconductor material situated between the first layer and the second layer. The present invention also provides a method for producing the photovoltaic device. | 06-10-2010 |
| 20100139763 | METHOD FOR PRODUCING AN EMITTER STRUCTURE AND EMITTER STRUCTURES RESULTING THEREFROM - A method for forming an emitter structure on a substrate and emitter structures resulting therefrom is disclosed. In one aspect, a method includes forming, on the substrate, a first layer comprising semiconductor material. The method also includes texturing a surface of the first layer, thereby forming a first emitter region from the first layer, wherein the first emitter region has a first textured surface. The method also includes forming a second emitter region at the first textured surface, the second emitter region having a second textured surface. | 06-10-2010 |
| 20100133660 | METHOD FOR PRODUCING INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS - The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate ( | 06-03-2010 |
| 20100129920 | METHOD AND SYSTEM FOR MEASURING PHYSICAL PARAMETERS WITH A PIEZOELECTRIC BIMORPH CANTILEVER IN A GASEOUS OR LIQUID ENVIRONMENT - A piezoelectric bimorph cantilever is used for determining physical parameters in a gaseous or liquid environment. The sensor works as a driven and damped oscillator. Contrary to common cantilever sensor systems, the piezoelectric film of the bimorph cantilever acts as both a sensor and an actuator. Using at least two resonance mode of the bimorph cantilever, at least two physical parameters can be measured simultaneously in a gas or a liquid. An optimized piezoelectric cantilever and a method to produce the cantilever are also described. | 05-27-2010 |
| 20100128764 | CALIBRATION METHOD FOR NON-IDEAL TRANSCEIVERS - A method of determining non-ideality characteristics introduced on a signal by a transceiver is disclosed. The transceiver has an up-conversion transmitter and a down-conversion receiver. In one aspect, the method includes: a) generating a signal comprising at least one known training symbol, b) up-converting this signal with a first frequency to a first signal in the transmitter, c) transferring the first signal from the transmitter to the receiver, d) down-converting with a second frequency this transferred first signal to a second signal in the receiver, the second frequency being different from but linked to the first frequency, e) detecting at least one of the training symbols in the second signal; and f) separating, in the frequency domain, at least one of the components of at least one of the detected training symbols for determining the non-ideality characteristics. | 05-27-2010 |
| 20100119229 | METHOD AND SYSTEM FOR MULTIPLEXER WAVEGUIDE COUPLING - An optical device for optically multiplexing or demultiplexing light of different predetermined wavelengths is provided, the optical device comprising at least one first waveguide ( | 05-13-2010 |
| 20100112782 | METHOD FOR REDUCING THE THICKNESS OF SUBSTRATES - The current invention presents a method for thinning wafers. The method uses a two-step process, whereby first the carrier wafer ( | 05-06-2010 |
| 20100109095 | METHOD FOR FABRICATING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF - A method for manufacturing a dual work function semiconductor device and the device made thereof are disclosed. In one aspect, a method includes providing a gate dielectric layer over a semiconductor substrate. The method further includes forming a metal layer over the gate dielectric layer. The method further includes forming a layer of gate filling material over the metal layer. The method further includes patterning the gate dielectric layer, the metal layer and the gate filling layer to form a first and a second gate stack. The method further includes removing the gate filling material only from the second gate stack thereby exposing the underlying metal layer. The method further includes converting the exposed metal layer into an metal oxide layer. The method further includes reforming the second gate stack with another gate filling material. | 05-06-2010 |
| 20100075486 | FORMATION OF SINGLE CRYSTAL SEMICONDUCTOR NANOWIRES - A method is provided for growing mono-crystalline nanostructures onto a substrate. The method comprises at least the steps of first providing a pattern onto a main surface of the substrate wherein said pattern has openings extending to the surface of the substrate, providing a metal into the openings of the pattern on the exposed main surface, at least partly filling the opening with amorphous material, and then annealing the substrate at temperatures between 300° C. and 1000° C. thereby transforming the amorphous material into a mono-crystalline material by metal mediated crystallization to form the mono-crystalline nanostructure. | 03-25-2010 |
| 20100075056 | METHOD OF FABRICATING A POROUS ELASTOMER - A method is provided for fabricating a porous elastomer, the method comprising the steps of: providing a predetermined amount of a liquid elastomer and a predetermined amount of a porogen; mixing the liquid elastomer and the porogen in vacuum until a homogenous emulsion without phase separation is formed; curing the homogenous emulsion until polymerizations of the emulsion is reached, thereby forming a cured emulsion; and removing the porogen from the cured emulsion. The method can advantageously be used for forming biocompatible porous elastomers and biocompatible porous membranes. | 03-25-2010 |
| 20100072531 | Method for Forming a Memory Cell Comprising a Capacitor Having a Strontium Titaniumoxide Based Dielectric Layer and Devices Obtained Thereof - A method is disclosed for manufacturing Sr | 03-25-2010 |
| 20100071718 | Method for Removing a Hardened Photoresist - A method for removing a hardened photoresist from a semiconductor substrate. An example method for removing a hardened photoresist layer from a substrate comprising a low-κ dielectric material preserving the characteristics of the low-k dielectric material includes: a)—providing a substrate comprising a hardened photoresist layer and a low-κ dielectric material at least partially exposed; b)—forming C═C double bonds in the hardened photoresist by exposing the hardened photoresist to UV radiation having a wavelength between 200 nm and 300 nm in vacuum or in an inert atmosphere; c)—breaking the C═C double bonds formed in step b) by reacting the hardened photoresist with ozone (O | 03-25-2010 |
| 20100068751 | Method and System for Artifact Reduction - A method is presented for obtaining characteristics of a target physical entity by providing an excitation signal to the target physical entity and simultaneously measuring the response of the target physical entity. Analog signal processing is performed on the measured response to eliminate artifacts arising from a signal path outside the target physical entity and determining the characteristics from the signal processed measured response. The excitation signal and the analog signal processing are selected such that after analog signal processing of the measured signal, the analog measured signal contains artifacts which are localized in time. | 03-18-2010 |
| 20100065824 | METHOD FOR REDUCING FERMI-LEVEL-PINNING IN A NON-SILICON CHANNEL MOS DEVICE - A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created. | 03-18-2010 |
| 20090294777 | METHOD FOR FORMING A GROUP III NITRIDE MATERIAL ON A SILICON SUBSTRATE - Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 μmol/cm | 12-03-2009 |
