IMEC VZW Patent applications |
Patent application number | Title | Published |
20160141391 | Method for Reducing Contact Resistance in MOS - A method for growing a III-V semiconductor structure on a Si | 05-19-2016 |
20160141174 | MOLYBDENUM DISULFIDE FILM FORMATION AND TRANSFER TO A SUBSTRATE - A method is provided for forming an unsupported MoS | 05-19-2016 |
20160131523 | SPECTROSCOPY SYSTEM WITH DISPLACEMENT COMPENSATION AND SPECTROSCOPY METHOD USING THE SPECTROSCOPY SYSTEM - A spectroscopy system includes detectors configured to obtain detection spectrums of respective detection areas that are located at different positions of an object; and an information processor configured to obtain a target spectrum of a target area by using position information of the detection areas and the detection spectrums obtained by the detectors. | 05-12-2016 |
20160128612 | SPECTROSCOPIC APPARATUS FOR BIOLOGICAL MATERIAL AND SPECTROSCOPIC METHOD USING THE SAME - A spectroscopic apparatus and method for analyzing a biological material are provided. The spectroscopic apparatus may analyze a biological material which has an internal non-uniform tissue depending on a position thereof. The apparatus may include at least one detector configured to obtain respective detection spectrums corresponding to a plurality of measurement regions that are at mutually different positions of the biological material, and an information processor to determine whether the measurement regions are normal by mutually comparing the detection spectrums, or converting contribution degrees of data for a specific component of the biological material by differentiating the detection spectrums. | 05-12-2016 |
20160126131 | Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure - An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other. | 05-05-2016 |
20160126109 | Method for Manufacturing a Transistor Device Comprising a Germanium Channel Material on a Silicon Based Substrate, and Associated Transistor Device - Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si | 05-05-2016 |
20160118542 | Method for Fabricating CMOS Compatible Contact Layers in Semiconductor Devices - A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer. | 04-28-2016 |
20160118295 | Method for Forming Contact Vias - A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique. | 04-28-2016 |
20160112063 | System and method for compressed sensing - A system for compressed sensing comprising: a compressive sampling module configured for providing a CS-sampled signal and a signal reconstruction module configured for receiving and allocating a first plurality of measurement windows comprising a number of samples from the CS-sampled signal, calculating a corresponding first plurality of reconstruction windows based on the first plurality of measurement windows and calculating a first version of a reconstructed signal based on the first plurality of reconstruction windows. The signal reconstruction module is also configured to allocate a second plurality measurement windows overlapping in content with the first plurality of measurement windows, calculate a second plurality of reconstruction windows based on the second plurality of measurement windows, calculate a second version of the reconstructed signal based on the second plurality of reconstructed windows and generate a reconstructed signal based on values from the first version and the second version of the reconstructed signal. | 04-21-2016 |
20160110492 | Error Resilient Digital Signal Processing Device - The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data. | 04-21-2016 |
20160106355 | System and Method for Monitoring a Subject's Eye - A system and a method for monitoring subject's eyes are disclosed. In one embodiment, spectral profiles of a frame substantially around a subject's eye are received from an image capturing device. Further, a state of the subject's eye in the frame is detected using the spectral profiles received from the image capturing device. | 04-21-2016 |
20160049310 | Method for Selective Oxide Removal - A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure. | 02-18-2016 |
20160032475 | Method for Nanowire Cluster Formation - A cluster of non-collapsed nanowires, a template to produce the same, methods to obtain the template and to obtain the cluster by using the template, and devices comprising the cluster are described. The cluster and the template both have an interconnected region and an interconnection-free region. | 02-04-2016 |
20160027876 | Dual Channel FinFET CMOS Device with Common Strain-Relaxed Buffer and Method for Manufacturing Thereof - A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge. | 01-28-2016 |
20160027777 | FinFET DEVICE WITH DUAL-STRAINED CHANNELS AND METHOD FOR MANUFACTURING THEREOF - A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed. | 01-28-2016 |
20160027528 | Sample-and-Hold Circuit for an Interleaved Analog-to-Digital Converter - The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage. | 01-28-2016 |
20160025931 | INTEGRATED GRATING COUPLER AND POWER SPLITTER - An optical device is provided for coupling an external optical signal into a plurality of on-chip photonic sub-circuits provided on a substrate. The optical device comprises: a planar waveguide layer on the substrate; a diverging grating coupler configured to couple the external optical signal to the planar waveguide layer and to thereby create an on-chip diverging optical beam in the planar waveguide layer; and a plurality of channel waveguides formed in the waveguide layer. Each channel waveguide of the plurality of channel waveguides comprises a waveguide transition structure having a waveguide aperture oriented towards the diverging grating coupler. For each channel waveguide of the plurality of channel waveguides the position and the width of the corresponding waveguide aperture and the angle and the shape of the waveguide transition structure are individually selected to capture a predetermined portion of the on-chip diverging optical beam. | 01-28-2016 |
20150353351 | Compact Fluid Analysis Device and Method to Fabricate - The present disclosure relates to a device for analyzing a fluid sample. In one aspect, the device includes a fluidic substrate that comprises a micro-fluidic component embedded in the fluidic substrate configured to propagate a fluid sample via capillary force through the device and a means for providing a fluid sample connected to the micro-fluidic component. The device also includes a lid attached to the fluidic substrate at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component. The fluidic substrate may be a silicon fluidic substrate and the lid may be a CMOS chip. In another aspect, embodiments of the present disclosure relate to a method for fabricating such a device, and the method may include providing a fluidic substrate, providing a lid, and attaching, through a CMOS compatible bonding process, the fluidic substrate to the lid to close the fluidic substrate at least partly. | 12-10-2015 |
20150340503 | Method of Producing a III-V Fin Structure - A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate. | 11-26-2015 |
20150335257 | Hyperdrive and Neuroprobes for Stimulation Purposes - A kit of parts for electrical stimulation and/or recording of activity of excitable cells in a tissue is described. The kit of parts comprises on the one hand a probe guiding means comprising a plurality of accommodation channels, each channel being adapted for accommodating a probe device having a plurality of stimulation means and/or recording means located on a die. At least one of the plurality of accommodation channels has a curved shape. The kit of parts also comprises at least one probe device for electrical stimulation and/or recording of activity of excitable cells in a tissue, the probe device comprising a plurality of stimulation means and/or recording means located on a die having a thinned and etched surface for providing flexibility to the probe device. | 11-26-2015 |
20150333481 | Hybrid Waveguide Lasers and Methods for Fabricating Hybrid Waveguide Lasers - The present disclosure relates to a method for integrating a sub-micron III-V waveguide laser on a semiconductor photonics platform as well as to a corresponding device/system. The method comprises providing on a semiconductor substrate an electrically insulating layer, etching a trench having a width in the range between 50 nm and 800 nm through the electrically insulating layer, thereby locally exposing the silicon substrate, providing a III-V layer stack in the trench by local epitaxial growth to form a channel waveguide, and providing a light confinement element for confining radiation in the local-epitaxial-grown channel waveguide. | 11-19-2015 |
20150333122 | Vertical Nanowire Semiconductor Structures - An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%. | 11-19-2015 |
20150302795 | Digital Driving of Active Matrix Displays - A method for digital driving of an active matrix display with a predetermined frame rate is described. The display contains a plurality of pixels organized in a plurality of rows and a plurality of columns. The method includes representing each of the plurality of pixels of an image to be displayed within a frame by an n-bit digital image code. The method also includes dividing the image frame into sub-frames, which may be of substantially equal duration. Within each sub-frame, the method includes sequentially selecting at least one of the plurality of rows twice. Upon a first selection, a first digital code is written to the selected row and upon a second selection a second digital code is written to the selected row. There is a predetermined time delay between the second selection and the first selection. Digital driving circuitry is also described. | 10-22-2015 |
20150287807 | Method for Manufacturing a Transistor Device - A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially growing a strained layer on the substrate (defect free), epitaxially growing the channel layer on the epitaxially grown strained layer, and providing a gate structure on the channel layer. In this example, the method also includes selectively etching into the channel layer and at least partially in the epitaxially grown strained layer, thereby using the gate structure as a mask, and thereby creating a protrusion extending from the substrate. The protrusion may comprise a portion of the channel layer and at least an upper portion of the epitaxially grown strained layer, and may allow for elastic relaxation in the portions. | 10-08-2015 |
20150285996 | Integrated Photonic Coupler - The present invention relates to an integrated photonic device comprising a photonic substrate, and an integrated waveguide provided in or on this substrate. The waveguide is adapted for conducting radiation of a predetermined wavelength. The device further comprises a sub-wavelength grating optically connected to the waveguide, which provides a first periodic variation of the refractive index in at least one first spatial direction. The device also comprises a diffracting grating arranged over the sub-wavelength grating for coupling radiation of the predetermined wavelength in and/or out of the integrated waveguide via the sub-wavelength grating. The diffracting grating provides a second periodic variation of the refractive index in at least one second spatial direction. The first periodic variation has a first pitch that is less than half of the predetermined wavelength, while the second periodic variation has a second pitch that is at least half of the predetermined wavelength. | 10-08-2015 |
20150280950 | Signal Processing - Described herein is a multi-level to binary converter in which a cascade of differential limiting amplifiers are utilised for each signal path to provide both increased gain and increased bandwidth without having to trade one off against the other. Where the multi-level data is duobinary, cascaded amplifiers are coupled to a XOR logic gate. In each path, a copy of the duobinary signal is level shifted using an adjustable threshold before amplification in an amplifier. The shifted and amplified signal is then fed to another amplifier where it undergoes the same steps. The outputs from each path are fed to the XOR logic gate to generate the desired binary signal, corresponding to a decoded synchronized NRZ data stream. Such a multi-level to binary converter is capable of performing at data rates of 50 to 80 Gb/s and above, and can easily be integrated within a chip for high-speed electrical backplane communication, optical backplanes or optical fibre links. | 10-01-2015 |
20150276873 | Test Circuits - Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode. | 10-01-2015 |
20150276624 | Quality Assessment of Directed Self-Assembling Method - A method for evaluating the quality of a directed self-assembling method used for generating directed self-assembling patterns. The method for evaluating comprises obtaining at least one set of parameter values for a parameterized set of processing steps and material properties characterizing the directed self-assembling method, thus characterizing a specific directed self-assembling method used for generating a directed self-assembled pattern. The method furthermore comprises obtaining a scattered radiation pattern on the directed self-assembled pattern obtained using the directed self-assembling method characterized by the set of parameter values, thus obtaining scattered radiation pattern results for the directed self-assembled pattern. The method furthermore comprises determining based on the scattered radiation pattern results a qualification score and correlating the qualification score with the set of parameter values. | 10-01-2015 |
20150244547 | Circuitry and Method for Multi-Level Signals - Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n−1) different reference values, and having N sets of (n−1) output terminals for outputting N sets of (n−1) output signals indicating whether the value of the multi-level signal is below or above the (n−1) reference values. The circuitry also includes N sets of (n−1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n−1) sample-and-hold circuits for generating at least one binary signal having a period N*T. | 08-27-2015 |
20150243509 | Method for Producing Fin Structures of a Semiconductor Device in a Substrate - A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures. | 08-27-2015 |
20150228502 | Contact Formation in Ge-Containing Semiconductor Devices - A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of:
| 08-13-2015 |
20150228497 | Plasma Method for Reducing Post-Lithography Line Width Roughness - The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the substrate in a plasma reactor, and subjecting the substrate to a plasma treatment at a temperature lower than zero degrees Celsius, such as between zero and −110° C. The plasma treatment may be a H | 08-13-2015 |
20150222344 | Modulation Circuit for a Radio Device and A Method Thereof - The present disclosure relates to a modulation circuit and a method for suppressing energy content of spectral side lobes caused by high-frequency content present in a baseband signal, with the energy content of the spectral side lobes being outside an intended operational bandwidth in a modulated radio-frequency signal. An example circuit is configured to: receive a digital baseband signal, feed the digital baseband signal to a first and a second signal path, with the first signal path comprising a first mixer and the second signal path comprising a delay circuit and a second mixer. The first mixer and the second mixer may receive a same local oscillator signal, and may respectively provide a first radio-frequency signal and a second radio-frequency signal that are delayed with respect to each other. The example circuit is further configured to generate an output radio-frequency signal by combining the first and second radio-frequency signals. | 08-06-2015 |
20150221805 | Implantable SERS Sensing Device and Method to Fabricate - A method for manufacturing a SERS sensing device ( | 08-06-2015 |
20150216481 | System and Method for Acquisition of Biopotential Signals with Motion Artifact Reduction in Real Time Operation - A biopotential signal acquisition system comprising an analogue readout unit configured to receive an analogue biopotential signal and to extract an analogue measured biopotential signal and an analogue reference signal, and an ADC unit configured to provide a digital version of the analogue measured biopotential signal and the analogue reference signal. The system also includes a first digital filter unit comprising a cascaded integrator-comb filter configured to provide a first digital filtered version of the digital measured biopotential signal and the reference signal, and a second digital filter unit configured to calculate a digital motion artifact estimate based on the first digital filtered version signals. | 08-06-2015 |
20150196909 | Microstructured Micropillar Arrays for Controllable Filling of a Capillary Pump - The embodiments of the present disclosure relate to a micro-fluidic device comprising a substrate, a cavity in the substrate and a plurality of micro-pillar columns located inside the cavity. The micro-pillars columns are configured to create a capillary action when a fluid sample is provided in the cavity. A micro-fluidic channel is present between two 5 walls of any two adjacent micro-pillars in a same micro-pillar column. Each of the two walls comprises a sharp corner along the direction of a propagation path of the fluid sample in the micro-fluidic channel thereby forming a capillary stop valve. A notch provided in a sidewall of the cavity acts as a capillary stop valve. | 07-16-2015 |
20150189199 | Imaging Sensors - Described herein is a pixel readout circuit which provides readout at two sensitivity levels depending on the amount of electrons generated by a pixel photodiode in the circuit. A floating diffusion capacitor operates to store charge up to a saturation value determined by its capacitance and an overflow capacitor is provided in an overflow region for storing charge above the saturation value of the floating diffusion capacitor. Readout at a high sensitivity level is provided when the floating diffusion capacitor is not saturated and readout at a lower sensitivity level is provided when there is saturation and subsequent overflow to the overflow region. Connection of the floating diffusion capacitor to the overflow capacitor shares the charge over the combined capacitance of the two capacitors and provides readout at a lower sensitivity without loss of charge. | 07-02-2015 |
20150179605 | Method for Aligning Micro-Electronic Components - Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid. | 06-25-2015 |
20150177459 | Radiation Coupler - Semiconductor photonics devices for coupling radiation to a semiconductor waveguide are described. An example photonics device comprises a semiconductor-on-insulator substrate comprising a semiconductor substrate, a buried oxide layer positioned on top of the semiconductor substrate, and the semiconductor waveguide on top of the buried oxide layer to which radiation is to be coupled. The example device also comprises a grating coupler positioned on top of the buried oxide layer and configured for coupling incident radiation to the semiconductor waveguide. The semiconductor substrate has a recessed portion at the backside of the semiconductor substrate for receiving incident radiation to be coupled to the semiconductor waveguide via the backside of the semiconductor substrate and the grating coupler. | 06-25-2015 |
20150173683 | System and Method for Acquisition of Biopotential Signals with Motion Artifact Reduction - A biopotential signal acquisition system including an analogue readout unit configured to receive an analogue biopotential signal, which may be acquired from at least one electrode attached to a body; and to extract an analogue measured biopotential signal and an analogue reference signal. The system also includes an ADC unit configured to provide a digital version of the analogue measured biopotential signal and the analogue reference signal, a digital filter unit configured to calculate a digital motion artifact estimate based on the digital version of the measured biopotential signal and the reference signal. The system further comprises a reference signal processing unit configured to convert the reference signal into a new reference signal being provided to the digital filter unit based on the correlation between the measured biopotential signal and the reference signal. | 06-25-2015 |
20150162212 | Method for Fabricating CMOS Compatible Contact Layers in Semiconductor Devices - A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer. | 06-11-2015 |
20150155179 | Method to Pattern Substrates - A method for creating a pattern on a substrate ( | 06-04-2015 |
20150153283 | Capillary flow plasmonic sensor - In a first aspect, a micro-fluidic device is presented, comprising: a micro-fluidic channel having an inner surface; a sensing region inside the micro-fluidic channel configured for adsorbing at least one analyte, the sensing region comprising a plurality of pillars positioned along the length of the inner surface of the micro-fluidic channel wherein the plurality of pillars are configured for creating an electromagnetic field localization thereby making the sensing region suitable for sensing plasmonic or surface enhanced Raman signals when irradiated; characterized in that: the plurality of pillars are further configured for creating a capillary action in the micro-fluidic channel when a fluid sample is present in the micro-fluidic channel. In a second aspect, a multiplexed plasmonic microchip for detecting at least one analyte in a fluid sample is presented, comprising: a plurality of micro-fluidic devices as presented in the first aspect; a supply system for providing the fluid sample to the plurality of micro-fluidic devices. Further, a method for detecting analytes is presented using a device according the first or second aspect. | 06-04-2015 |
20150151301 | Device and Method for Performing Digital PCR - A micro-fluidic device | 06-04-2015 |
20150137275 | Titanium Nitride Electrode - The present invention relates to a method for decreasing the impedance of a titanium nitride element for use in an electrode component. The method comprises obtaining a titanium nitride element and hydrothermally treating the titanium nitride element by immersing the titanium nitride element in a liquid comprising water while heating said liquid. | 05-21-2015 |
20150130062 | Method for Manufacturing Germanide Interconnect Structures and Corresponding Interconnect Structures - Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide. | 05-14-2015 |
20150119747 | System and Method for Acquisition of Biopotential Signals With Electrode-Tissue Impedance Measurement - A system for the acquisition of biopotential signals, comprising at least a first electrode configured for detecting a biopotential signal within a signal bandwidth of interest and being connected to an impedance detection module that provides a first electrode voltage. The impedance detection module comprises a current generation circuit connected in parallel to an amplifier. The current generation circuit comprises an AC current generator configured to generate a first current signal through the first electrode. The first current signal has a frequency outside of the signal bandwidth of interest. The current generation circuit also comprising a capacitor connected between the input of the amplifier and the AC current generator so as to isolate the AC current generator from the amplifier input at the signal bandwidth of interest. The system also including a signal processor configured to calculate a component value of a first and a second electrode-tissue impedance based on a difference between the first electrode voltage and a second electrode voltage. | 04-30-2015 |
20150115277 | Episubstrates for Selective Area Growth of Group III-V Material and a Method for Fabricating a Group III-V Material on a Silicon Substrate - The embodiments disclose a silicon substrate with a group III-V material and a method for fabricating a group III-V material on a silicon substrate. The method involves providing a silicon substrate. A first layer formed atop the silicon substrate, is subsequently patterned to expose the underlying silicon substrate. A group III-V material layer is formed over the patterned first layer and also on the exposed silicon substrate. The group III-V material layer is subjected to chemical mechanical polishing (CMP) to expose the first layer resulting in the formation of a plurality of areas suitable for growing a device layer on the silicon substrate. | 04-30-2015 |
20150111351 | Method for Manufacturing a Field Effect Transistor of a Non-Planar Type - A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench. | 04-23-2015 |
20150111335 | Module-Level Processing of Silicon Photovoltaic Cells - A method for module-level processing of photovoltaic cells is provided. The method includes: bonding at least one crystalline silicon photovoltaic substrate to a carrier by means of an adhesive layer, thereby leaving part of the adhesive layer uncovered; after bonding, exposing the uncovered part of the adhesive layer and the at least one crystalline silicon photovoltaic substrate to a plasma; and removing a surface portion of the at least one crystalline photovoltaic substrate. The method may further include performing an annealing step of the adhesive before bonding the at least one photovoltaic substrate to the carrier, and performing an outgassing step of the adhesive after bonding the at least one photovoltaic substrate to the carrier. The method may further include module-level rear side processing of the at least one crystalline silicon photovoltaic substrate to make a photovoltaic module. | 04-23-2015 |
20150105297 | Electrical Polynucleotide Mapping - A micro-fluidic device for mapping a DNA or RNA strand labeled at a plurality of specific sites with labels suitable for generating a detection signal when interacting with a detector element, the device comprising:
| 04-16-2015 |
20150093816 | Compact Fluid Analysis Device and Method to Fabricate - The present disclosure relates to a device for analyzing a fluid sample. In one aspect, the device includes a fluidic substrate that comprises a micro-fluidic component embedded in the fluidic substrate configured to propagate a fluid sample via capillary force through the device and a means for providing a fluid sample connected to the micro-fluidic component. The device also includes a lid attached to the fluidic substrate at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component. The fluidic substrate may be a silicon fluidic substrate and the lid may be a CMOS chip. In another aspect, embodiments of the present disclosure relate to a method for fabricating such a device, and the method may include providing a fluidic substrate, providing a lid, and attaching, through a CMOS compatible bonding process, the fluidic substrate to the lid to close the fluidic substrate at least partly. | 04-02-2015 |
20150091142 | Layer Deposition on III-V Semiconductors - The present disclosure relates to a method ( | 04-02-2015 |
20150084661 | Method for the Extraction of Recombination Characteristics at Metallized Semiconductor Surfaces - The present disclosure relates to methods for determining recombination characteristics at metallized semiconductor surfaces and of metallized semiconductor junctions, based on photo-conductance decay measurements. Dedicated test structures are used comprising a plurality of metal features in contact with a semiconductor surface at predetermined locations, the metal features being provided in a plurality of zones, each of the plurality of zones having a different metal coverage. The method comprises performing a photo-conductance decay measurement in each of the plurality of zones, thereby determining effective lifetimes for different injection levels as a function of metal coverage; and extracting the recombination characteristics from the determined effective lifetimes. | 03-26-2015 |
20150064889 | Method for Dopant Implantation of FinFET Structures - The present disclosure is related to a method for implanting dopant elements in a structure comprising a plurality of semiconductor fins separated by field dielectric areas. The method includes depositing an etch stop layer on the fins, depositing a BARC layer on the etch stop layer, depositing a resist layer on the BARC layer, removing a portion of the resist layer by lithography steps to thereby expose an area of the BARC layer, removing the BARC layer in the exposed area by a dry etch process using the remaining resist layer as a mask, implanting dopant elements into the fins present in the area, using the BARC and resist layers as a mask, and removing the remainder of the resist and BARC layers. | 03-05-2015 |
20150028428 | III-V Semiconductor Device with Interfacial Layer - A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same. | 01-29-2015 |
20140377936 | Method for Forming a Strained Semiconductor Structure - The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer. | 12-25-2014 |
20140374867 | Pinned Photodiode (PPD) Pixel Architecture With Separate Avalanche Region - Described herein is a pinned photodiode pixel architecture having a p-type substrate that is independently biased with respect to a pixel area to provide an avalanche region between an n-type region and a p-type region formed on the substrate. Such a pinned photodiode pixel can be used in imaging sensors that are used in low light level conditions. | 12-25-2014 |
20140368920 | Micro-Mirror Arrays - Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror element arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt axis range, and each micro-mirror element in the second section has a second tilt axis range, with the first tilt axis range being less than the second tilt axis range. | 12-18-2014 |
20140363744 | Solid-State Battery and Method for Manufacturing Thereof - A solid-state battery cell includes an anode, a cathode, and a solid electrolyte matrix. At least the anode or the cathode may include an active electrode material having pores. Further, an inner surface of the pores may be coated with a first surface-ion diffusion enhancement coating. The solid electrolyte matrix may further include an electrically insulating matrix for a solid electrolyte. The electrically insulating matrix may have pores or passages and an inner surface of the pores or the passages may be coated with a second surface-ion diffusion enhancement coating. | 12-11-2014 |
20140312700 | Reconfigurable PV Configuration - A PV module is described with an array of PV cells whereby the module is reconfigurable, allowing different configurations to be applied after installation and during operation, i.e. at run-time. The run time configuration of the module has controllable devices. The main controllable devices are any of (individually or in combination): a) switches which determine the parallel/series connections of the cells as well as hybrid cases also. b) switches between the cells and local dc/dc converters and/or among the DC/DC converters; c) actively controlled bypass diodes placed in order to allow excess current to flow in the occurrence of a mismatch. | 10-23-2014 |
20140295613 | METHOD FOR FABRICATING HETEROJUNCTION INTERDIGITATED BACK CONTACT PHOTOVOLTAIC CELLS - The disclosed technology generally relates photovoltaic devices, and more particularly to methods of fabricating heterojunction interdigitated back contact photovoltaic cells having interdigitated emitter regions and back surface field regions. In one aspect, a method of forming on a substrate a patterned n+ a-Si:H layer and a patterned p+ a-Si:H layer, the patterned n+ a-Si:H layer and the patterned p+ a-Si:H layer being interdigitated and electrically isolated from each other, the method comprising: forming a patterned p+ a-Si:H layer on the substrate, the patterned p+ a-Si:H layer covering first regions of the substrate surface and leaving second regions of the substrate surface exposed; depositing a first intrinsic a-Si:H layer on the substrate; depositing an n+ a-Si:H layer on the first intrinsic a-Si:H layer; providing a patterned masking layer covering the n+ a-Si:H layer at least in the second regions; and selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer in regions not covered by the masking layer and stopping at an underlying portion of the p+ a-Si:H layer substantially without removing a substantial amount of the underlying portion of the p+ a-Si:H layer, wherein selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer comprises etching in a solution comprising a diluted TMAH solution. | 10-02-2014 |
20140247089 | Two Stage Source-Follower Based Filter - A filter, comprising: two source-follower stages connected in series and in between input nodes and output nodes, wherein inner nodes connect the two stages; and a frequency dependent feedback circuit connected between the input and output nodes, wherein the filter comprises additional frequency dependent feedback circuits connected between input nodes and inner nodes and between output nodes and inner nodes, the additional frequency dependent feedback circuits comprising capacitors. | 09-04-2014 |
20140235187 | Front-End System for a Radio Transmitter - Front-end systems for a transmitter included in a radio device are disclosed. An example front-end system may comprise a voltage-to-power mixer. The voltage-to-power mixer may be configured to up-convert a baseband signal to a high-frequency signal by multiplying the baseband signal with a local oscillator signal. Additionally, the voltage-to-power mixer may include a voltage feedback circuit. The example front-end system may further comprise a two-stage power amplifier. The two-stage power amplifier may be configured to amplify the high-frequency signal. | 08-21-2014 |
20140234219 | Method and Device for Detecting Analytes | 08-21-2014 |
20140197862 | METHODS FOR CHARACTERIZING SHALLOW SEMICONDUCTOR JUNCTIONS - The disclosed technology generally relates to methods of characterizing semiconductor materials, and more particularly to methods of characterizing shallow semiconductor junctions. In one aspect, the method of characterizing shallow semiconductor junctions comprises providing a substrate comprising a shallow junction formed at a first main surface, where the shallow junction is formed substantially parallel to the first main surface. The method additionally comprises providing a dielectric layer on the first main surface. The method additionally comprises iterating, at least twice, a combination of processes including providing a respective charge on a predetermined area of the dielectric layer via a charge applicator, and measuring a corresponding junction photovoltage for the predetermined area. The method further comprises deriving at least one of an average hole/electron mobility or a dose of active dopants in the substrate corresponding to the predetermined area, based on the respective charges and the corresponding junction photo voltages. | 07-17-2014 |
20130187680 | Complementary Logic Device Comprising Metal-to-Insulator Transition Material - A complementary logic technology is disclosed whereby a logic gate comprises at least two metal-to-insulator transition (MIT) elements and at least two thermoelectric elements, each MIT element being thermally coupled to a corresponding thermoelectric element. In logic gates, each electric signal at an input terminal of a logic gate is first converted into two complementary thermal signals, and these thermal signals in turn determine the status of the output terminal of the logic gate, thereby generating an electrical output signal inverse to the electrical input signal or an output signal which is a Boolean operation on input signals. The parallel connection(s) of thermoelectric elements of the logic gate is used to create corresponding thermal signals for each electrical input signal. The MIT elements of the logic gate are then arranged to, in response to the associated thermal signals, execute a Boolean operation. | 07-25-2013 |
20130074017 | Illumination-Source Shape Definition in Optical Lithography - A method and system are described for determining lithographic processing conditions for a lithographic process. After obtaining input, a first optimization is made for illumination source and mask design under conditions of allowing non-rectangular sub-resolution assist features. Thereafter, mask design is optimized in one or more further optimizations for which only rectangular sub-resolution assist features are allowed. The latter results in good lithographic processing while limiting the complexity of the mask design. | 03-21-2013 |
20130063846 | ESD Protection Device With Reduced Clamping Voltage - Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q | 03-14-2013 |
20130061673 | Three-Mass Coupled Oscillation Technique for Mechanically Robust Micromachined Gyroscopes - A micromachined gyroscope is disclosed comprising a substrate, three masses m | 03-14-2013 |