| HYPRES, INC. Patent applications |
| Patent application number | Title | Published |
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| 20110288823 | WIDEBAND DIGITAL SPECTROMETER - A processor, comprising a first data input configured to receive a stream of samples of a first signal having a spectral space, the stream having a data rate of at least 4 GHz; a second data input configured to receive a stream of samples of a second signal; a multitap correlator, configured to receive the first stream of samples and the second stream of samples, and producing at least one correlation output for each respective sequential sample of the first signal received; and a programmable control configured to alter a relationship of the stream of samples of the first signal and the stream of samples of the second signal, to thereby select, under program control, an alterable correlation output. | 11-24-2011 |
| 20110167241 | SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE - A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays. | 07-07-2011 |
| 20100329401 | SYSTEM AND METHOD FOR CONTROLLING COMBINED RADIO SIGNALS - A method for controlling a combined waveform, representing a combination of at least two signals having orthogonal frequency multiplexed signal components, comprising: receiving information defining the at least two signals; transforming the information defining each signal to a representation having orthogonal frequency multiplexed signal components, such that at least one signal has at least two alternate representations of the same information, and combining the transformed information using the at least two alternate representations, in at least two different ways, to define respectively different combinations; analyzing the respectively different combinations with respect to at least one criterion; and outputting a respective combined waveform or information defining the waveform, representing a selected combination of the transformed information from each of the at least two signals selected based on the analysis. | 12-30-2010 |
| 20100149011 | SUPERCONDUCTING ANALOG-TO-DIGITAL CONVERTER - A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an N | 06-17-2010 |
| 20100066576 | Superconductor Multi-Level Quantizer - A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capable to adjust the flux threshold for at least one of the JJ comparators. The quantizer is so configured a feedback current from the output is capable to shift the flux threshold for each of the JJ comparators. | 03-18-2010 |
| 20100026537 | Superconductor Analog-to-Digital Converter - A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an N | 02-04-2010 |
| 20090315021 | DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS - An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed. | 12-24-2009 |
| 20090237106 | DIGITAL PROGRAMMABLE PHASE GENERATOR - A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective phase shift for any of 2 | 09-24-2009 |
| 20090232510 | DIGITAL RADIO FREQUENCY TRANCEIVER SYSTEM AND METHOD - A transceiver architecture for wireless base stations wherein a broadband radio frequency signal is carried between at least one tower-mounted unit and a ground-based unit via optical fibers, or other non-distortive media, in either digital or analog format. Each tower-mounted unit (for both reception and transmission) has an antenna, analog amplifier and an electro-optical converter. The ground unit has ultrafast data converters and digital frequency translators, as well as signal linearizers, to compensate for nonlinear distortion in the amplifiers and optical links in both directions. In one embodiment of the invention, at least one of the digital data converters, frequency translators, and linearizers includes superconducting elements mounted on a cryocooler. | 09-17-2009 |
| 20090232507 | DIGITAL RADIO FREQUENCY TRANCEIVER SYSTEM AND METHOD - A transceiver architecture for wireless base stations wherein a broadband radio frequency signal is carried between at least one tower-mounted unit and a ground-based unit via optical fibers, or other non-distortive media, in either digital or analog format. Each tower-mounted unit (for both reception and transmission) has an antenna, analog amplifier and an electro-optical converter. The ground unit has ultrafast data converters and digital frequency translators, as well as signal linearizers, to compensate for nonlinear distortion in the amplifiers and optical links in both directions. In one embodiment of the invention, at least one of the digital data converters, frequency translators, and linearizers includes superconducting elements mounted on a cryocooler. | 09-17-2009 |
| 20090232191 | DIGITAL RADIO FREQUENCY TRANCEIVER SYSTEM AND METHOD - A transceiver architecture for wireless base stations wherein a broadband radio frequency signal is carried between at least one tower-mounted unit and a ground-based unit via optical fibers, or other non-distortive media, in either digital or analog format. Each tower-mounted unit (for both reception and transmission) has an antenna, analog amplifier and an electro-optical converter. The ground unit has ultrafast data converters and digital frequency translators, as well as signal linearizers, to compensate for nonlinear distortion in the amplifiers and optical links in both directions. In one embodiment of the invention, at least one of the digital data converters, frequency translators, and linearizers includes superconducting elements mounted on a cryocooler. | 09-17-2009 |
| 20090086533 | SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE - A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays. | 04-02-2009 |
