HYPERSTONE GMBH Patent applications |
Patent application number | Title | Published |
20150220433 | METHOD FOR MANAGING FLASH MEMORIES HAVING MIXED MEMORY TYPES USING A FINELY GRANULATED ALLOCATION OF LOGICAL MEMORY ADDRESSES TO PHYSICAL MEMORY ADDRESSES - A method manages a flash memory for a computer system having flash chips divided into separately erasable physical memory blocks with a limited maximum erasure frequency. The memory blocks are divided into writable pages being subdivided into addressable subpages. The subpages are addressed by a computer via logical sector addresses being converted into physical subpage addresses. The flash memory has a first area containing single-level flash chips with a higher maximum erasure frequency, and a second area containing multi-level flash chips with a lower maximum erasure frequency. If write operations in the first area exceed an upper threshold for a filling level of written memory blocks, a written memory block having a low erasure counter is searched for in the first area, whose valid subpages are transferred into a memory block of the second area. The address allocations for the transferred subpages are updated. | 08-06-2015 |
20140068390 | HYBRID DECODING OF BCH CODES FOR NONVOLATILE MEMORIES - An apparatus and a method for correcting data errors in a data block. The data block contains original data which are supplemented by such a security syndrome that the data block effects a correction of at most t data errors, wherein a parallel-operating quick corrector is used. The quick corrector is only designed for a correction of a subset t | 03-06-2014 |
20110302359 | METHOD FOR MANAGING FLASH MEMORIES HAVING MIXED MEMORY TYPES - A method manages a flash memory having a plurality of physical blocks. The blocks of the memory are addressed by logic block addresses which are converted into physical block addresses. In each block a deletion counter is run in which the number of deletions of the block is counted, and two regions having different types of flash chips are present. A first region contains single-level flash chips with a large maximum deletion frequency, and a second region contains multi-level flash chips with a lower maximum deletion frequency. When writing to the memory the address conversion of the logic addresses into physical addresses is carried out such that all blocks of the first region are written, when all blocks of the first region have been written and a further writing process is initiated, the block in the first region having the lowest deletion counter is copied into a blank block in the second region. | 12-08-2011 |
20100306456 | METHOD FOR EVEN UTILIZATION OF A PLURALITY OF FLASH MEMORY CHIPS - A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well. | 12-02-2010 |
20100250837 | Method for Addressing Page-Oriented Non-Volatile Memories - A method for addressing memory pages of a non-volatile memory in a memory system with a memory controller and a further volatile memory. The non-volatile memory is organized in erasable memory blocks with a multiplicity of memory pages, and each memory page, containing a number of sectors, can be written individually. The volatile memory holds an address translation table specifying an assignment of logical memory page addresses to physical memory page addresses. By way of the memory controller, a reconstruction table is stored as a copy of the address translation table in one or more memory blocks in the non-volatile memory, a log book table with data records containing changed assignments of logical memory page addresses to physical memory page addresses, is carried in the volatile memory and, if the log book table exceeds a predetermined size, a changed reconstruction table is stored in the non-volatile memory. | 09-30-2010 |