HYPERION CORE, INC.
|HYPERION CORE, INC. Patent applications|
|Patent application number||Title||Published|
|20140351563||ADVANCED PROCESSOR ARCHITECTURE - The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic-Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units such that a signal. from the register file crosses the execution unit and is receipt by the register file in one clock cycle; and wherein a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles.||11-27-2014|
|20140310696||TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARDWARE MODIFICATION - The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.||10-16-2014|
|20130191817||Optimisation of loops and data flow sections - The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.||07-25-2013|
|20120216012||SEQUENTIAL PROCESSOR COMPRISING AN ALU ARRAY - The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.||08-23-2012|
|20120137075||System and Method for a Cache in a Multi-Core Processor - The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.||05-31-2012|
Patent applications by HYPERION CORE, INC.