| HIMAX TECHNOLOGIES LIMITED Patent applications |
| Patent application number | Title | Published |
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| 20120135201 | Semiconductor Structures and Method for Fabricating the Same - A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure. | 05-31-2012 |
| 20120127120 | TOUCH DEVICE AND TOUCH POSITION LOCATING METHOD THEREOF - A touch device and a touch position locating method thereof are provided. The touch position locating method includes the following steps. A plurality of target blocks are selected from a plurality of sensing blocks of a touch panel. The target blocks are detected at the same time to obtain a plurality of touch sensing data. Reference data is obtained according to the touch sensing data. Subtraction operations between the reference data and the touch sensing data are performed respectively, so as to obtain a plurality of adjusted touch sensing data. A location of a touch point on the touch panel is calculated according to the adjusted touch sensing data. | 05-24-2012 |
| 20120119829 | REPAIR AMPLIFICATION CIRCUIT AND METHOD FOR REPAIRING DATA LINE - A repair amplification circuit includes a controlling unit, a first operational amplifier, a second operational amplifier, a first switching unit, and a second switching unit. Under a detection mode, the controlling unit generates a detecting signal according to a testing signal transmitted by a unnecessary repair segment in a test picture. Under an operation mode, the controlling unit generates a switching signal according to a repair controlling signal related to the detecting signal. The first switching unit and the second switching unit are controlled by the switching signal, so as to transmit the driving signal to one of the first operational amplifier and the second operational amplifier, and to transmit a positive polarity repairing signal generated by the first operational amplifier or a negative polarity repairing signal generated by the second operational amplifier to a necessary repair segment. | 05-17-2012 |
| 20120105607 | Image Display System and Image Display Method Thereof - An image display system and image display method thereof. The image display system includes a multimedia receiving port, a 3D content detection engine, a format converter and an image display device. The multimedia receiving port is operative to receive a video signal. The 3D content detection engine analyzes one image of the video signal to determine whether the video signal includes 3D content. When the 3D content detection engine determines that the video signal includes 3D content, the format converter is enabled to convert the video signal into a 3D format, to display 3D video on the image display device. When no 3D content is contained in the received video signal, the format converter is not enabled, and the image display device displays the non-format converted video signal. | 05-03-2012 |
| 20120105419 | Driving Circuit for Liquid Crystal Pixel Array and Liquid Crystal Display Using the Same - A driving circuit with reduced power consumption and a liquid crystal display using the same. The driving circuit includes at least a power circuit, a source driver and a VCOM driver. The power circuit is coupled to a power supply to receive a power signal to generate a positive supply voltage and an inverted power signal. The source driver includes a first source operational amplifier. The first source operational amplifier is powered by the positive supply voltage and a power ground, to couple a positive polarity display voltage to a first terminal of a first display capacitor of a pixel array. The VCOM driver includes a VCOM operational amplifier. The VCOM operational amplifier provides a second terminal of the first display capacitor with a VCOM voltage, and a negative power terminal of the VCOM operational amplifier is coupled to the inverted power signal. | 05-03-2012 |
| 20120105406 | Driving Circuit for Liquid Crystal Pixel Array and Liquid Crystal Display Using the Same - A driving circuit and a liquid crystal display using the same. In the driving circuit, a first switch and a second switch are provided in a VCOM driver thereof. The first switch is designed to be turned on to a ground a VCOM terminal of a display capacitor, and the second switch is designed to be turned on to couple a constant voltage level DC VCOM to the VCOM terminal of the display capacitor. In addition, a timing controller of the driving circuit is designed for reducing power consumption, which controls the statuses of the first and second switches and determines when to allow a positive polarity voltage to be coupled to the display capacitor to charge the display capacitor for positive polarity display. | 05-03-2012 |
| 20120081980 | MEMORY - A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line signal. The first and the second reference bit line generators respectively detect voltage level variations of the first and last bit lines according to the pre-word line signal, so as to generate a first and a second cut-back signals. The first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits the first and the second cut-back signals to the word line decoder, and the word line decoder generates a word line signal according to the first and the second cut-back signals and the pre-word line signal. | 04-05-2012 |
| 20120068744 | Phase Locked Loop Circuits - A phase locked loop circuit is provided. The PLL circuit receives an input clock signal and generates an output clock signal according to internal clock signals with phase shifting which are generated according to the input clock signal. The PLL circuit includes a selector, a dividing unit, a converter, a low pass filer (LPF), and a modulator. The selector selects one of the internal clock signals to serve as a selection clock signal according to an enable signal. The first dividing unit performs dividing operations to the selection clock signal to generate the output clock signal and a feedback clock signal. The converter detects phase difference between the feedback clock signal and a reference clock signal to generate a detection signal. The LPF performs a filtering operation to the detection signal to generate a filtering signal. The modulator modulates the filtering signal to generate the enable signal. | 03-22-2012 |
| 20120062247 | TEST SYSTEM AND METHOD - A test system for testing a capacitive touch sensor is provided. The test system includes a resistor, a signal generator and a micro controller. A first end of the resistor is electrically connected to a sensing port of the capacitive touch sensor. The signal generator provides a test voltage to a second end of the resistor according to control information. In this way, the resistor generates a test current according to the test voltage, and the capacitive touch sensor provides a voltage difference to the sensing port according to a plurality of switching signals, and converts the test current into test information. The micro controller generates the control information according to a test table, and compares the test information according to the test table, so as to determine whether an operation of the capacitive touch sensor is normal. | 03-15-2012 |
| 20120062193 | VOLTAGE REGULATION CIRCUIT - A voltage regulation circuit including a differential input unit, a source follower and a driving unit is provided. The differential input unit has a first input terminal and a second input terminal for receiving a reference voltage and a system voltage respectively. Further, the differential input unit compares the reference voltage and the system voltage and accordingly generates a control voltage. The source follower is electrically connected between the differential input unit and the driving unit, and generates an adjustment voltage according to the control voltage. The differential input unit, the source follower and the driving unit form a feedback loop, so that the driving unit fixes a source voltage to the system voltage according to the adjustment voltage. | 03-15-2012 |
| 20120056842 | Sensing Apparatus for Touch Panel and Sensing Method Thereof - A sensing apparatus for a touch panel includes: sensitive capacitors formed between intersections of first electrodes and the second electrodes; a first sensing circuit, for positioning two locations of the first electrodes by sensing changed capacitance values of the sensitive capacitors corresponding to the two locations of the first electrodes; a second sensing circuit, for positioning two locations of the second electrodes by two objects by sensing changed capacitance values of the sensitive capacitors corresponding to the two locations of the second electrodes; and a third sensing circuit for sequentially positioning two locations of the scanned electrodes by sensing changed capacitance values of the sensitive capacitors corresponding to the two locations of the scanned electrodes, wherein a control circuit determines the two touch points according to the two locations of the first electrodes, and the two locations of the second electrodes and the two locations of the scanned electrodes. | 03-08-2012 |
| 20120044241 | THREE-DIMENSIONAL ON-SCREEN DISPLAY IMAGING SYSTEM AND METHOD - The present invention is directed to a 3D OSD imaging system and method. A depth generator generates at least one image depth map according to a 2D image, and an image mixer superimposes an OSD image on the 2D image, thereby resulting in a 2D image with OSD. An OSD unit provides an OSD depth map and the OSD image, and a depth mixer superimposes the OSD depth map on the image depth map, thereby resulting in a composite depth map. A depth-image-based rendering (DIBR) unit generates a left image and a right image according to the 2D image with OSD and the composite depth map. | 02-23-2012 |
| 20120044162 | POSITIONING METHOD AND DRIVING APPARATUS FOR TOUCH PANEL - A positioning method and a driving apparatus for a touch panel having a plurality of sense electrodes in an axis direction are disclosed. The driving apparatus detects the sense electrodes to obtain a plurality of sensed values. The driving apparatus counts the number of multiple candidate electrodes, wherein the candidate electrode is an electrode having a sensed value larger than a first threshold value. The first threshold value is increased and the number of the candidate electrodes is counted again if the number of the candidate electrodes is larger than a second threshold value. At least one electrode is selected as a positioning electrode from the candidate electrodes if the number of the candidate electrode is not larger than the second threshold value. A position of a touch point on the touch panel in the axis direction is calculated based on the position and sensed value of the positioning electrode. | 02-23-2012 |
| 20120032935 | DRIVING DEVICE OF FLAT PANEL DISPLAY AND DRIVING METHOD THEREOF - A driving device and a driving method of a flat panel display are provided. The driving device includes a driving circuit, an output buffer and a buffer control module. The driving circuit outputs a pixel data during a valid data period, and an input terminal of the output buffer receives the output of the driving circuit. The buffer control module turns off the output buffer during a blanking data period, and turns on the output buffer during the valid data period in order to reduce power consumption of the output buffer, and maintain an image quality of the flat panel display. | 02-09-2012 |
| 20120013587 | DRIVING DEVICE FOR DYNAMIC BIAS AND DRIVING METHOD THEREOF - A driving device and a driving method for dynamic bias are provided. The driving device includes a buffer and a bias control unit. An input terminal of the buffer receives a data voltage, and an output terminal of the buffer is connected to a load through a switch. The bias control unit connected to the buffer controls a bias of the buffer dynamically. During a transition period of the data voltage, the bias control unit controls the buffer in a normal bias state. During a power-saving period, the bias control unit controls the buffer in a low bias state, and controls the buffer in the normal bias state during a turning-off period of the switch. The driving device controls the buffer to sustain data voltage quickly during the turning-off period of the switch, so as to avoid the data voltage received by the load having errors and reduce power consumption. | 01-19-2012 |
| 20120008244 | ELECTRICAL-OVERSTRESS PROTECTION CIRCUIT FOR AN INTEGRATED CIRCUIT - An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode. | 01-12-2012 |
| 20120005507 | Display Devices and Control Methods - A display device includes a host, a control unit, and a display unit. The control unit receives host data from the host and then generates input data. The control unit includes first, second, and third memories and an arbiter. The first memory stores the input data to serve as first stored data. The second memory stores second stored data and outputs it for generating output data. The third memory stores third stored data. When the amount of the first stored data is greater than a first threshold value, the arbiter performs a writing operation to write the first stored data into the third memory. When the amount of the second stored data is lower than a second threshold value, the arbiter performs a reading operation to read the third stored data to being written into the second memory. The display unit displays images according to the output data. | 01-05-2012 |
| 20120004880 | Temperature Sensor and Temperature Sensing Method - A temperature sensor is provided. The temperature sensor includes: a temperature sensing unit for sensing a temperature and outputting a temperature sensing signal; an analog-to-digital converter (ADC), coupled to the temperature sensing unit, for converting the temperature sensing signal to a digital value, having an ADC output range; a calibration unit, coupled to the ADC, for correlating the ADC output range with at least one temperature range; a memory unit, coupled to the calibration unit, recording the ADC output range, and the at least one temperature range, and the correlation therebetween. | 01-05-2012 |
| 20120001857 | Filter for Removing DC Signal and High Frequency Noise and Method Thereof for Touch Sensor - A filtering system, adapted to remove a direct current (DC) component and a high frequency noise component of a touch-sensed signal is provided. The filtering system includes: an analog to digital converter for transforming the touch-sensed signal into a discrete-time input signal; a direct current removing unit for removing direct current components of the discrete-time input signal to obtain a differentiated signal; a de-noise unit for removing noise components of the differentiated signal to obtain a de-noise signal; and a reconstructive unit for processing the de-noise signal to obtain an output signal. | 01-05-2012 |
| 20110316591 | Spread Spectrum Clock System and Spread Spectrum Clock Generator - A spread spectrum clock generator includes a triangular wave generator, a digital wave modulator, a sigma delta modulator, and a selector. The triangular wave generator transforms one of the input clock signals into an original triangular wave signal, in which the input clock signals have the same frequency and phases different from each other. The digital wave modulator adjusts the waveform of the original triangular wave signal to generate an adjusted triangular wave signal and a first square wave signal according to an inputted control signal. The sigma delta modulator, electrically connected to the digital wave modulator, accumulates magnitude values of the adjusted triangular wave signal to generate a second square wave signal. The selector selects one of the input clock signals as an output clock signal based on voltage levels of the first square wave signal and the second square wave signal. | 12-29-2011 |
| 20110302338 | MICROCONTROLLER - A microcontroller is disclosed, which includes a memory, a first storage unit, a plurality of second storage units, a multiplexer and a micro-controller unit (MCU). The first storage unit is for being written into with a first code. The second storage units are for being written into with a plurality of second codes. The multiplexer writes the first code and one of the said second codes into the memory according to a control signal so that the memory generates a system code. The MCU reads out the system code come from the memory to perform operations. | 12-08-2011 |
| 20110293110 | DE-POP CIRCUIT AND AN ASSOCIATED AUDIO SYSTEM - A de-pop circuit adaptable to an audio circuit is disclosed. A high-pass filter generates a high-pass output signal according to an output signal of the audio circuit. A blockage circuit receives the high-pass output signal and a control signal, and generates an enable signal to activate the audio circuit according to the control signal and the high-pass output signal. | 12-01-2011 |
| 20110285701 | Stereo-Matching Processor Using Belief Propagation - In accordance with at least some embodiments of the present disclosure, a processor for performing stereo matching of a first image and a second image is described. The processor may include a first pipeline stage configured to generate data costs associated with a first tile selected from the first image, wherein the data costs is generated based on pixels in the first tile and corresponding pixels in the second image. The processor may include a second pipeline stage configured to generate disparity values associated with the first tile and an outbound message from the first tile to one of neighboring tiles in the first image, wherein the disparity values and the outbound message are generated based on the data costs and inbound messages from the neighboring tiles to the first tile. The processor may further include a third pipeline stage configured to store the disparity values and the outbound message in a memory, wherein the outbound message is used by the second pipeline stage as one of the inbound messages during processing of a second tile selected from the first image. | 11-24-2011 |
| 20110279424 | DISPLAY DEVICE AND DRIVING CIRCUIT THEREOF - A display device including a display panel and a driving circuit is provided, wherein the driving circuit includes a synchronizer and a driver. The synchronizer synchronizes a plurality of external control signals according to an internal clock and accordingly generates a plurality of internal control signals. The driver reads the internal control signals according to the internal clock and accordingly generates a plurality of driving signals to drive the display panel. | 11-17-2011 |
| 20110273462 | SYSTEM AND METHOD FOR STORING AND ACCESSING PIXEL DATA IN A GRAPHICS DISPLAY DEVICE - A graphics display device comprises a first and second memory, and a data transfer controller coupled with the first and second memory. In some embodiments, a method of storing pixel data comprises receiving and latching first pixel data associated with a first pixel, receiving second pixel data associated with a second pixel, and concurrently writing the first pixel data in the first memory and the second pixel data in the second memory. In other embodiments, a method of accessing pixel data of an image frame comprises accessing the first and second memory for reading out pixel data of each pair of adjacent pixels, when the image frame has an odd total number of pixels determining whether a final pixel data is in a latched state, and reading out the final pixel data from the data transfer controller when the final pixel data is in the latched state. | 11-10-2011 |
| 20110261604 | MEMORY CELL AND AN ASSOCIATED MEMORY DEVICE - A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage transistor is always turned on. A wordline is coupled to a gate of the access transistor of each sub-cell, and complementary bit lines are respectively coupled to sources/drains of the access transistors of the pair of sub-cells, such that data bit may be accessed between the bit line and the corresponding storage transistor through the corresponding access transistor. | 10-27-2011 |
| 20110260758 | HALF-POWER BUFFER AMPLIFIER - A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground. | 10-27-2011 |
| 20110255867 | PHASE SELECTOR - A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal. | 10-20-2011 |
| 20110255596 | FRAME RATE UP CONVERSION SYSTEM AND METHOD - The invention is directed to a frame rate up conversion (FRUC) system and method. A motion estimation (ME) unit is configured to generate at least one motion vector (MV) according to a frame input. A triple-line buffer based motion compensation (MC) unit is configured to generate an interpolated frame according to the MV, a reference frame and a current frame, thereby generating a frame output with a frame rate higher than a frame rate of the frame input. | 10-20-2011 |
| 20110254814 | SYSTEM AND METHOD FOR HANDLING IMAGE DATA TRANSFER IN A DISPLAY DRIVER - In a display driver, image data are assembled with synchronization information to form a stream of digital data. The stream of digital data is transmitted from a timing controller to a data driver along with a timing signal having phase-delayed pulses obtained from an external clock received by the timing controller. In response to the timing signal, the data driver can extract a synchronizing signal from the synchronization information embedded in the stream of digital data, and use the synchronizing signal for generating an internal clock signal. Encoded image data in the stream of digital data then can be retrieved according to the internal clock signal. | 10-20-2011 |
| 20110250860 | RECEIVER AND METHOD FOR DYNAMICALLY ADJUSTING SENSITIVITY OF RECEIVER - A receiver and a method for dynamically adjusting sensitivity of the receiver are provided. The receiver includes a detection unit and a receiving unit. The detection unit detects an input signal group, and outputs a detection result. The receiving unit receives the input signal group according to a sensitivity. Wherein, the receiving unit dynamically adjusts the sensitivity used for receiving the input signal group according to the detection result of the detection unit. | 10-13-2011 |
| 20110249870 | METHOD OF OCCLUSION HANDLING - In a method of occlusion handling, a reference frame and a current frame are first provided, and at least one foreground object is determined. At least a covered region or an uncovered region with respect to the foreground object is determined. The covered region is then interpolated exclusively accordingly to the current frame, or the uncovered region is interpolated exclusively according to the reference frame. | 10-13-2011 |
| 20110249188 | METHOD OF BLOCK-BASED MOTION ESTIMATION - In a method of block-based motion estimation a motion vector map is obtained by obtaining a motion vector of each macroblock (MB) in the current frame with respect to the reference frame. The motion vector of each MB in an interpolated frame is then determined according to the motion vector map. | 10-13-2011 |
| 20110248950 | SCANNING METHOD OF A TOUCH PANEL - A scanning method of a touch panel is provided. The touch panel has a horizontal channel group including a plurality of horizontal channels and a vertical channel group including a plurality of vertical channels. According to the scanning method, N channels may be scanned simultaneously, wherein the N channels are selected from the horizontal channel group or the vertical channel group, the N channels are not adjacent to each other, N is a positive integer, and N is less than a channel amount of the selected channel group. Thereby, the scanning speed and the sensing accuracy of the touch panel using the scanning method are enhanced. | 10-13-2011 |
| 20110242083 | DISPLAY AND PIXEL CIRCUIT THEREOF - A display panel is disclosed. The display panel includes a data line, a scan line, a first switch connected to a first voltage, a second switch connected to a second voltage, and a pixel. The pixel is further comprised of a data transistor having a first source/drain electrode connected to the data line, a gate electrode connected to the scan line and a second source/drain electrode, a driving transistor having a first source/drain electrode connected via a first switch to the first voltage, a gate electrode connected via the second switch to the second voltage and a second source/drain electrode, a storage capacitor having a first electrode connected to the gate electrode of the driving transistor and a second electrode connected to the first source/drain electrode of the driving transistor and to the second source/drain electrode of the data transistor, and a lighting device having an anode electrode connected to the second source/drain electrode of the driving transistor and a cathode electrode connected to a third voltage. | 10-06-2011 |
| 20110242076 | DEVICE FOR DRIVING DATA AND METHOD THEREOF USED FOR LIQUID CRYSTAL DISPLAY - A device for driving data used for a liquid crystal display includes: a first latch circuit and a second latch circuit for forming first latched data and second latched data; a first regulating circuit and a second regulating circuit for regulating the first latched data or the second latched data; a first switch, a second switch, a third switch and a fourth switch respectively coupled between the first latch circuit or the second circuit and the first regulating circuit or the second regulating circuit. The first and the second latched data become a first pair of differential signals when the first switch and the fourth switch are turned on. The first and the second latched data become a second pair of differential signals which are opposite to the first pair of differential signals when the second switch and the third switch are turned on. | 10-06-2011 |
| 20110241752 | Mixed-voltage I/O buffer - A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level. | 10-06-2011 |
| 20110234262 | DRIVER CIRCUIT OF DISPLAY DEVICE - A driver circuit includes a mode control unit and a plurality of source drivers to drive a display panel including pixel cells on each scan line. Each source driver has M driving channels, and two subsets of the driving channels are respectively in a first mode and a second mode according to a preset mode sequence. The 1 | 09-29-2011 |
| 20110234198 | Differential Reference Voltage Generator - A differential reference voltage generator generates a first differential reference voltage and a second differential reference voltage. The differential reference voltage generator includes a first operational amplifier, a first transistor, a first resistor, and a second resistor. The first operational amplifier has a negative terminal adapted to receive a reference voltage. The first transistor has a source receiving a power supply voltage and has a gate electrically connected to an output terminal of the first operational amplifier. The first resistor has a first terminal electrically connected to a drain of the first transistor, and has a second terminal electrically connected to a positive terminal of the first operation amplifier. The second resistor has a first terminal electrically connected to the second terminal of the first resistor, and a second terminal electrically connect to a current mirror. | 09-29-2011 |
| 20110228174 | LIGHT SOURCE CONTROL METHOD OF PROJECTOR - A light source control method of a projector is provided. The light source control method includes the following steps. A frame data of a frame period is received. Gray distributions of a plurality of colors in the frame data are obtained by analyzing the frame data. Whether to shut all or a portion of a plurality of color light sources of the projector is determined according to the gray distributions of the colors. Therefore, the power consumption of the projector can be reduced. | 09-22-2011 |
| 20110221762 | CONTENT-ADAPTIVE OVERDRIVE SYSTEM AND METHOD FOR A DISPLAY PANEL - A content-adaptive overdrive system and method, for a display panel, include a frame difference device and an overdrive device. The frame difference device generates a frame difference map according to a current frame and a previous frame. The frame difference map includes a number of flags respectively indicating similarity between corresponding pixels or blocks of the current frame and the previous frame. The overdrive device adaptively performs an overdrive function based on the frame difference map, the current frame, the previous frame and an overdrive lookup table, hence resulting in an overdrived frame. | 09-15-2011 |
| 20110216057 | Timing Controller and Clock Signal Detection Circuit Thereof - The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time. | 09-08-2011 |
| 20110194025 | METHOD AND SYSTEM OF HIERARCHICAL MOTION ESTIMATION - A method and system of hierarchical motion estimation include a reference frame and a current frame being downsampled, and the downsampled reference frame being stored. A coarse motion vector (MV) map is generated according to the downsampled reference frame and the downsampled current frame. Scan lines adjacent to a center scan line corresponding to a downsampled scan line in the downsampled reference frame are retrieved and then stored. A refined MV map is generated according to the coarse MV map, the current frame and the stored scan lines adjacent to the center scan line. | 08-11-2011 |
| 20110181519 | System and method of driving a touch screen - A system of driving a touch screen comprises a touch sensitive panel including a plurality of first sensor lines parallel to a first direction and a plurality of second sensor lines parallel to a second direction, a driving circuit coupled with the first sensor lines, a first sensing circuit, and a controller coupled with the first sensing circuit. The driving circuit is configured to sequentially apply a first scanning signal through each of the first sensor lines. The first sensing circuit can report a plurality of first response signals that are transmitted through the second sensor lines in response to each applied first scanning signal. The controller can identify one or more touch location based on the first response signals reported by the first sensing circuit, and track each identified touch location. In other embodiments, methods of driving a touch screen are also described. | 07-28-2011 |
| 20110175937 | GAMMA VOLTAGE GENERATION CIRCUIT - A gamma voltage generation circuit is provided. The gamma voltage generation circuit includes a plurality of resistor strings, a plurality of second resistors and a plurality of switches. Each of the resistor strings has a plurality of first resistors connected in series. Each of ends of the first resistors provides a gamma reference voltage. Each of second resistors is connected in series with the resistor strings. Each of the switches is coupled to a corresponding one of the resistor strings, selects and outputs one of the gamma reference voltages provided by the ends of the first resistors of the corresponding one of the resistor strings according to a control signal. Therefore, levels of the gamma voltages can synchronously displaced, so that the effects presented by pixels with different common voltage levels are similar or equal. | 07-21-2011 |
| 20110175896 | DISPLAY DRIVING CIRCUIT AND METHOD THEREOF - A display driving circuit has a scan switch, an assistant unit, several storage switches, and several storage units. The scan switch couples to a data line. The assistant unit couples to the scan switch. The storage switches couple to the assistant unit. Each storage unit couples to the assistant unit by one of the storage switches. The assistant unit is shared by the storage units to compensate for several driving voltages or several driving currents of the storage units. | 07-21-2011 |
| 20110175877 | GAMMA VOLTAGE GENERATION CIRCUIT - A gamma voltage generation circuit is provided. The gamma voltage generation circuit includes a resistor string, a first switch, and a second switch. The resistor string includes a plurality of resistors connected in series. An output terminal of the first switch is coupled to a first end of the resistor string. An output terminal of the second switch is coupled to a second end of the resistor string. The first switch selects and outputs one of a first high reference voltage and a second high reference voltage to the first end of the resistor string according to a control signal. The second switch selects and outputs one of a first low reference voltage and a second low reference voltage to the second end of the resistor string according to the control signal. | 07-21-2011 |
| 20110175663 | GAMMA VOLTAGE GENERATION CIRCUIT - A gamma voltage generation circuit is provided. An offset voltage generator generates a first offset voltage by dividing a voltage difference between a first input voltage and a second input voltage based on a first code. A first voltage shifting circuit of a voltage level shifter shifts down a first reference voltage by the first offset voltage to output a first level-shifted voltage. A second voltage shifting circuit of the voltage level shifter shifts down a second reference voltage by the first offset voltage to output a second level-shifted voltage. Each of resistors of a resistor string outputs one of the gamma voltages. A first end and a second end of the resistor string are respectively coupled to a first output terminal and a second output terminal of the voltage level shifter. | 07-21-2011 |
| 20110175652 | FRACTIONAL-N PHASE-LOCKED LOOP - A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, to form a second loop. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference. | 07-21-2011 |
| 20110169544 | SOURCE DRIVER - A source driver, which has a first resistor string, a first digital-to-analog converter, and a channel buffer, is provided. The first resistor string has a plurality of resistors connected in series, wherein each of the resistors of the first resistor string provides a corresponding gamma voltage. The first digital-to-analog converter is coupled to the resistors of the first resistor string. The digital-to-analog converter selectively outputs one of gamma voltages provided by the resistors as a first output voltage according to a data code. The channel buffer is coupled to an output terminal of the first digital-to-analog converter to output a second output voltage by shifting a voltage level of the first output voltage. | 07-14-2011 |
| 20110164022 | Common Voltage Driving Circuit for High-Resolution TFT-LCD - A common voltage driving circuit configured to output a common voltage to high-resolution TFT-LCD is provided. The common voltage driving circuit includes: a first pad coupled to a common electrode loading of an LCD for sensing a common voltage of the common electrode loading; a second pad coupled to the common electrode loading; a first amplifying device receiving a high level voltage and the sensed common voltage of the common electrode loading for generating a first overdrive voltage to the second pad thereby improving transient response of the common voltage with high level; and a second amplifying device receiving a low voltage level voltage and the sensed common voltage of the common electrode loading for generating a second overdrive voltage to the second pad thereby improving transient response of the common voltage with low level. | 07-07-2011 |
| 20110157103 | Display Device and Driving Circuit - A display device is provided, including a panel, source driver chips, a gate driver chip, a printed circuit board and transmission lines. The panel includes light emitting elements and display cells. The display cells are respectively connected to data lines and gate lines. The source driver chips output pixel signals to the data lines. At least one source driver chip includes a timing controller integrated therein for generating timing control signals and the pixel signals according to an image control signal provided by a host. The gate driver chip outputs corresponding scan signals to the gate lines. The transmission lines are routed on the printed circuit board and connect to the source driver chips. | 06-30-2011 |
| 20110157072 | TOUCH PANEL - A touch panel including a plurality of panel capacitors, a first switching unit, a second switching unit, a first charging unit, a control unit and a counter is provided. Each of the panel capacitors is sequentially selected as an object capacitor. The first switching unit and the second switching unit switch the voltages received by the two terminals of the object capacitor. The control unit controls a first charging current provided by the first charging unit according to the variation in the terminal voltages of the object capacitor, and generates a comparison signal accordingly. The counter counts the comparison signal and the touch panel identifies the variation in the capacitance value of the object capacitor by using a count value generated by the counter. | 06-30-2011 |
| 20110148843 | PIXEL CIRCUIT - A pixel circuit has an organic light emitting diode, a driving transistor, a capacitor and a first switch. The organic light emitting diode has a first end coupled to a first power source terminal. The driving transistor has a source and a drain respectively coupled to a second power source terminal and a second end of the light emitting diode. The capacitor couples a gate of the driving transistor to a reference voltage terminal. The first switch couples the second end of the light emitting diode to the capacitor, and couples the gate and the drain of the driving transistor together when a first scan signal is asserted. | 06-23-2011 |
| 20110148829 | PIXEL CIRCUIT - A pixel circuit has an organic light emitting diode, a driving transistor, a capacitor and a first switch. The organic light emitting diode has a first end coupled to a first power source terminal. The driving transistor has a source and a drain respectively coupled to a second power source terminal and a second end of the light emitting diode. The capacitor couples a gate of the driving transistor to a reference voltage terminal. The first switch couples the second end of the light emitting diode to the capacitor, and couples the gate and the drain of the driving transistor together when a first scan signal is asserted. | 06-23-2011 |
| 20110141237 | DEPTH MAP GENERATION FOR A VIDEO CONVERSION SYSTEM - In accordance with at least some embodiments of the present disclosure, a process for generating a depth map for converting a two-dimensional (2D) image to a three-dimensional (3D) image is described. The process may include generating a depth gradient map from the 2D image, wherein the depth gradient map is configured to associate one or more edge counts with one or more depth values, extracting an image component from the 2D image, wherein the image component is associated with a color component in a color space, determining a set of gains to adjust the depth gradient map based on the image component, and generating the depth map by performing depth fusion based on the depth gradient map and the set of gains. | 06-16-2011 |
| 20110134165 | METHOD FOR GENERATING A GAMMA TABLE - A method for generating a gamma table is provided. The method is applied to a display, and the display obtains n-bit corrected gray levels [y(1), . . . , y(2 | 06-09-2011 |
| 20110134164 | METHOD FOR GENERATING A GAMMA TABLE - A method for generating a gamma table is provided. The method is applied to a display, and the display obtains n-bit corrected gray levels [y(1), . . . , y(2 | 06-09-2011 |
| 20110134093 | SYSTEM AND METHOD OF DRIVING A LIQUID CRYSTAL DISPLAY - A driver unit comprises a latch circuit for holding digital image data in a voltage state, a digital-to-analog converter, and a voltage compensator circuit for raising the analog display voltage. The digital-to-analog converter can access content of the digital image data from the voltage state in the latch circuit, and convert the digital image data into analog display signals. In other embodiments, a method of driving a liquid crystal display comprises storing digital image data in a latch circuit under a voltage state, accessing a content of the digital image data from the voltage state held in the latch circuit, selecting a reference voltage according to the content of the digital image data for converting the digital image data into analog display signals, and raising the analog display voltage for obtaining a driving voltage. | 06-09-2011 |
| 20110128174 | DIGITAL TO ANALOG CONVERTER - A digital to analog converter with two outputs controlled by an input signal with n-bits is disclosed. A reference voltage circuit generates (2 | 06-02-2011 |
| 20110128047 | HALF-POWER BUFFER AMPLIFIER - A half-power buffer amplifier includes a buffer stage having a first-half buffer stage and a second-half buffer stage. An output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. A switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. | 06-02-2011 |
| 20110122122 | SOURCE DRIVER AND OPERATION METHOD THEREOF AND FLAT PANEL DISPLAY - A source driver, an operation method thereof, and a flat panel display using the same are provided. The source driver includes a data channel, a switch and a switch controller. The data channel latches a pixel data according to timing of a line letch signal, and converts the latched pixel data to a driving signal for driving a display panel. The data channel decides a polarity of the driving signal according to a polarity signal. A first end of the switch is coupled to the data channel to receive the driving signal. The switch controller adjusts a pulse width of the line letch signal to obtain a control signal for controlling the switch according to the polarity signal. A pulse width of a first pulse is smaller than that of a second pulse in the control signal after the polarity signal is changed. | 05-26-2011 |
| 20110116331 | METHOD FOR INITIALIZING MEMORY DEVICE - A method for initializing a memory device is provided. The method includes a step for transmitting at least N+1 clock cycles to the memory device, wherein the N is an amount of bits of output serial data of the memory device. During a clock cycle of the at least N+1 clock cycles, a first start/stop signal is transmitted to the memory device. During another clock cycle of the at least N+1 clock cycles, a second start/stop signal is transmitted to the memory device. | 05-19-2011 |
| 20110113172 | UTILIZATION-ENHANCED SHARED BUS SYSTEM AND BUS ARBITRATION METHOD - A utilization-enhanced shared bus system and bus arbitration method are disclosed. An arbiter arbitrates among multiple masters according to active requests sent from the masters. The arbiter sends a passive request to one of the masters in an idle period of the shared bus according to respective status of the masters. Accordingly, the master that receives the passive request may access a shared resource in the idle period. | 05-12-2011 |
| 20110102395 | METHOD AND SYSTEM OF CONTROLLING HALT AND RESUME OF SCANNING AN LCD - A system and method of controlling scanning actions of an LCD is disclosed. A timing controller (Tcon) output enable (OE) generator generates an original OE signal, and a noise detection unit generates a noise-detected signal upon detecting noise. An OE mask generator generates a mask signal according to the noise-detected signal and the original OE signal. A masking unit generates a resultant OE signal according to the mask signal and the original OE signal. | 05-05-2011 |
| 20110102394 | METHOD AND SYSTEM OF CONTROLLING HALT AND RESUME OF SCANNING AN LCD - A method and system of controlling halt and resumption of scanning actions of an LCD is disclosed. An incoming video source is monitored, and current scan line position and corresponding polarity are recorded. When an abnormal video source is detected, the LCD scanning is stopped at a halt scan line of a halt frame with a halt polarity. After a normal video source has been detected again, determination is made of a proper resumptive scan line and/or a resumptive polarity. The panel scanning is resumed at the resumptive scan line equal to the halt scan line and/or with the resumptive polarity matching the halt polarity. | 05-05-2011 |
| 20110102037 | CIRCUIT FOR RESETTING SYSTEM AND DELAY CIRCUIT - A reset circuit and a delay circuit are provided. The delay circuit includes a first resistor module, a second resistor module, a switch module and a capacitor module. First terminals of the first and the second resistor modules are coupled respectively to a first voltage and a second voltage. The switch module have a control terminal served as a input terminal of the delay circuit, a first terminal served as a output terminal of the delay circuit, a second terminal coupled to a second terminal of the first resistor module, and a third terminal coupled to a second terminal of the second resistor module. In the delay circuit, the first terminal selectively connected to the second terminal or the third terminal in accordance with the control terminal. The capacitor module couples between the first terminal of the switch module and the second voltage. | 05-05-2011 |
| 20110095831 | PVT-INDEPENDENT CURRENT-CONTROLLED OSCILLATOR - The invention discloses a PVT-independent current-controlled oscillator, including a PV-controller, a current-controlled oscillator and a T-controller. The current-controlled oscillator is coupled to the PV-controller and outputs an oscillation frequency. The T-controller is coupled to the PV-controller and the current-controlled oscillator, providing a total current to be shared by the PV-controller and the current-controlled oscillator, wherein the PV-controller decreases the shared current of the current-controlled oscillator by increasing the shared current of the PV-controller if the oscillation frequency is higher than a predetermined frequency due to a process variation of the current-controlled oscillator, and increases the shared current of the current-controlled oscillator by decreasing the shared current of the PV-controller if the oscillation frequency is lower than the predetermined frequency due to the process variation of the current-controlled oscillator, thereby dynamically adjusting the oscillation frequency. | 04-28-2011 |
| 20110095737 | VOLTAGE REGULATOR, AND INTEGRATED CIRCUIT USING THE SAME - A voltage regulator and an integrated circuit using the voltage regulator is provided. The voltage regulator has a bandgap reference circuit, an operational amplifier, a power transistor and a voltage divider. The bandgap reference circuit generates a bandgap reference voltage. The operational amplifier receives the bandgap reference voltage and a feedback voltage to output a control signal for the power transistor. The power transistor is powered by a first voltage source and transforms the first voltage source to a second voltage source according to the control signal. The second voltage source is divided by the voltage divider to generate the feedback voltage and is further used in powering the bandgap reference circuit and the operational amplifier. | 04-28-2011 |
| 20110090608 | ELECTRICAL-OVERSTRESS PROTECTION CIRCUIT FOR AN INTEGRATED CIRCUIT - An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode. | 04-21-2011 |
| 20110084945 | Output Amplifier of Source Driver - An output amplifier includes an amplifier circuit, an output stage circuit, a first switch transistor, and a second switch transistor. The amplifier circuit is used for amplifying an input pixel signal to generate the inverted signal and the non-inverted signal. The output stage circuit has a first output terminal for passing a supply voltage from a supply terminal or passing a ground voltage from a ground terminal to the pixel circuit according to the inverted signal and the non-inverted signal. The first switch transistor passes or blocks the supply voltage according to a high impedance signal, and the second switch transistor passes or blocks the ground voltage according to the inverted high impedance signal. | 04-14-2011 |
| 20110084761 | Output Amplifier of Source Driver - An output amplifier includes an amplifier circuit, a driving stage circuit, an output stage circuit, a first unity gain buffer, and a second unity gain buffer. The amplifier circuit provides an inverted signal and a non-inverted signal, in which the amplifier circuit amplifies an input pixel signal to generate the inverted signal and the non-inverted signal. The output stage circuit passes a supply voltage or a ground voltage to the pixel circuit according to the inverted signal and the non-inverted signal. The driving stage circuit passes the supply voltage or the ground voltage to the pixel circuit. The first unity gain buffer enhances and passes the inverted signal from the amplifier circuit to the driving stage circuit. The second unity gain buffer passes and enhances the non-inverted signal from the amplifier circuit to the driving stage circuit. | 04-14-2011 |
| 20110084745 | OUTPUT BUFFER WITH SLEW-RATE ENHANCEMENT OUTPUT STAGE - An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage. | 04-14-2011 |
| 20110084733 | DRIVING CIRCUIT WITH SLEW-RATE ENHANCEMENT CIRCUIT - A driving auxiliary circuit receiving an input voltage to control an output voltage of an operational amplifier via a first switch and a second switch is provided. A pull-low circuit turns on the first switch, including a first input terminal coupled to a high voltage source providing a high voltage and a first output terminal for controlling the voltage level of the output voltage. The output voltage is charged to be equal to the input voltage when the input voltage exceeds the output voltage. A pull-high circuit turns on the second switch, including a second input terminal coupled to the high voltage source providing the high voltage and a second output terminal for controlling the voltage level of the output voltage. The output voltage is discharged to be equal to the input voltage when the output voltage exceeds the input voltage. | 04-14-2011 |
| 20110069088 | SOURCE DRIVER AND CHARGE SHARING FUNCTION CONTROLLING METHOD THEREOF - A source driver includes a driver unit and a data analysis unit. The driver unit drives a display panel according to a video signal. The data analysis unit, which is coupled to the driver unit, analyzes gray level distribution of the video signal, and the data analysis unit enables or disables a charge sharing function of the driver unit according to an analysis result. As a result, the charge sharing function is enabled optionally during different charge sharing periods, and thus the power consumption in the source driver and the operation temperature of the source driver could be reduced as compared with the prior art. | 03-24-2011 |
| 20110068848 | MULTI-CHANNEL INTEGRATOR - A multi-channel integrator is provided. The multi-channel integrator includes an integrator and a plurality of channels. Each of the channels includes an input selector and a unit-gain amplifier. The input selector has a common terminal, a first selecting terminal and a second selecting terminal. The input selector selectively electrically connects the common terminal to the first selecting terminal or to the second selecting terminal. The first selecting terminal of the input selector is coupled to an input terminal of the integrator. An input terminal of the unit-gain amplifier is coupled to the second selecting terminal of the input selector. | 03-24-2011 |
| 20110063279 | DISPLAY AND SOURCE DRIVER THEREOF - A pixel circuit has a light emitting diode, a first driving transistor, a second driving transistor, a capacitor, and a switch unit. When a scan signal is asserted, the switch unit couples sources/drains of the second driving transistor respectively to a first and a second source/drain of the first driving transistor, and couples a gate and second source/drain of the first driving transistor together. When the scan signal is de-asserted, the switch unit decouples one of the sources/drains of the second driving transistor from the first/second source/drain of the first driving transistor, and decouples the gate from the second source/drain of the first driving transistor. | 03-17-2011 |
| 20110063233 | READOUT APPARATUS AND MULTI-CHANNEL READOUT APPARATUS FOR TOUCH PANEL - A readout apparatus and a multi-channel readout apparatus for a touch panel are provided to integrate different types of readout circuit. The readout apparatus set to a first mode reads the touch panel with a small amount of charges through an integrator. The readout apparatus set to a second mode reads a sensing current of a current type touch panel through a current to voltage converting unit and an inverting amplifier, so as to save a chip area. The multi-channel readout apparatus set to a third mode applies multiple channels to alternatively share an integrator to read the touch panel with a large amount of charges, so that an amount of feedback capacitors (integral capacitors) having a great area can be greatly reduced. Therefore, readout apparatus of the present invention can not only reduce a chip area, but can also be applied to various types of the touch panel. | 03-17-2011 |
| 20110055610 | PROCESSOR AND CACHE CONTROL METHOD - A processor and a cache control method are provided herein. The processor includes a plurality of caches and a control unit. The caches are respectively controlled by a plurality of cache enable signals to be activated. The control unit generates the cache enable signals according to a power mode for selecting and accessing a subset of the caches in response to the power mode, wherein the number of the subset of the caches is determined by the power mode. Therefore, the processor can activate the caches as requirement according to the power mode for reducing power consumption of the caches. | 03-03-2011 |
| 20110050677 | SOURCE DRIVER - A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module. | 03-03-2011 |
| 20110050665 | SOURCE DRIVER AND COMPENSATION METHOD FOR OFFSET VOLTAGE OF OUTPUT BUFFER THEREOF - A source driver and a compensation method for an offset voltage of an output buffer are provided. The source driver includes a storage element, an output buffer, a sampling unit and a first switch. The output buffer has a first input terminal coupled to the storage element and a second input terminal coupled to an output terminal thereof. The output buffer enhances an input signal of the first input terminal and thereby outputs an output signal via the output terminal. The sampling unit respectively transmits a pixel signal and the output signal to the first input terminal of the output buffer and the storage element during a first sub-period for storing an offset voltage of the output buffer in the storage element. The first switch transmits the pixel signal to the storage during a second sub-period for compensating the pixel signal with the offset voltage stored in the storage element. | 03-03-2011 |
| 20110050189 | BOOSTER AND VOLTAGE DETECTION METHOD THEREOF - A booster and a voltage detection method thereof are provided herein. The booster includes a charge pump circuit and a voltage detection circuit. The charge pump circuit is controlled by a switching signal to generate an actual voltage according to the basis voltage, wherein the actual voltage is a product of the basis voltage multiplied by a first preset multiplier. The voltage detection circuit is coupled to the charge pump circuit. The voltage detection circuit selects one of a plurality of first multipliers to serve as the first preset multiplier according to a comparison result between the basis voltage and a target voltage, and generates the switching signal corresponding to the first preset multiplier. Therefore, the booster can properly select the first preset multiplier to generate the actual voltage as the basis voltage changes. | 03-03-2011 |
| 20110043493 | METHOD FOR DETERMINING AN OPTIMUM SKEW AND ADJUSTING A CLOCK PHASE OF A PIXEL CLOCK SIGNAL AND DATA DRIVER UTILIZING THE SAME - A data driver including a receiver, a skew adjusting circuit and a processing device is provided. The receiver samples image data on a data bus according to a processed pixel clock signal. The image data includes pixel data during active periods and a test pattern repeatedly inserted in the image data during blanking periods. The skew adjusting circuit receives a pixel clock signal and adjusts a clock phase of the pixel clock signal by delaying the pixel clock signal with a controllable skew according to a feedback control signal so as to generate the processed pixel clock signal. The processing device stores a predetermined test pattern synchronized with the inserted test pattern, determines an optimum skew by comparing the sampled test patterns with the predetermined test pattern, and generates the feedback control signal including information indicating the optimum skew. | 02-24-2011 |
| 20110038397 | SPREAD-SPECTRUM GENERATOR - A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI). | 02-17-2011 |
| 20110037753 | PIXEL CIRCUIT - A pixel circuit has a light emitting diode, a first driving transistor, a second driving transistor, a capacitor, and a switch unit. When a scan signal is asserted, the switch unit couples sources/drains of the second driving transistor respectively to a first and a second source/drain of the first driving transistor, and couples a gate and second source/drain of the first driving transistor together. When the scan signal is de-asserted, the switch unit decouples one of the sources/drains of the second driving transistor from the first/second source/drain of the first driving transistor, and decouples the gate from the second source/drain of the first driving transistor. | 02-17-2011 |
| 20110037457 | READOUT APPARATUS FOR CURRENT TYPE TOUCH PANEL - A readout apparatus for a current type touch panel is provided. The readout apparatus includes a current-to-voltage converter, a voltage gain unit and an analog-to-digital converter (ADC). The current-to-voltage converter converts a sensing current of the current type touch panel to a sensing voltage. An input end of the voltage gain unit is coupled to an output end of the current-to-voltage converter for receiving the sensing voltage. An input end of the ADC is coupled to an output end of the voltage gain unit. An output end of the ADC generates a digital code. | 02-17-2011 |
| 20110032240 | BUFFERING CIRCUIT WITH REDUCED DYNAMIC POWER CONSUMPTION - A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption. | 02-10-2011 |
| 20110025662 | TIMING CONTROLLER AND LIQUID DISPLAY DEVICE - An embodiment of the invention provides a timing controller. The timing controller comprises a frequency detector, a signal generator and a multiplexer. The frequency detector receives a reference clock signal and an input clock signal to generate a decision signal. The signal generator generates a first signal and a second signal. The multiplexer receives and outputs one of the first signal and the second signal according to the decision signal. | 02-03-2011 |
| 20110019085 | FILM-MODE VIDEO STREAM HANDLING METHOD AND SYSTEM - One embodiment of the present invention sets forth a method for detecting a bad edit. The method includes receiving a 3:2 film-mode video signal comprising a sequence of video fields, for each of the sequence of video fields, determining a state for the each video field based on a first moving-pixel count for the each video field with respect to a previous same-parity video field for the each video field and a second moving-pixel count for a first immediately preceding field for the each video field with respect to a second previous same-parity field for the first immediately preceding field, and identifying the 3:2 film-mode video signal as a bad edit if a predetermined state transition has been detected in the sequence of video fields. | 01-27-2011 |
| 20110018851 | LIQUID CRYSTAL DISPLAY AND CHARGE PUMP THEREOF - A charge pump with limited peak current and improved application flexibility and an LCD having the same. The charge pump has more than three switches in a charge path and more than three switches in a pump path. Furthermore, the charge pump has a voltage detector detecting voltage of the output terminal of the charge pump and a charge pump controller controlling the switches based on the detected voltage. According to the detected voltage, the charge pump controller determines the number of turning-on switches in the charge path and determines the number of turning-on switches in the pump path. | 01-27-2011 |
| 20110018801 | Visual Input/Output Device with Light Shelter - A visual input/output device with a light shield is disclosed. The device includes an active area for performing visual input/output tasks, and a non-active area surrounding the active area in the peripheral area of the device. The light shield is formed in the non-active area for substantially preventing unwanted light from interfering with the active area. The light shield is formed on a same layer as a color filter in the active area, and the light shield is made of black pigment or carbon. | 01-27-2011 |
| 20110018792 | MULTIMODE SOURCE DRIVER AND DISPLAY DEVICE HAVING THE SAME - A multimode source driver for driving a display device in provided, including a bus swapping circuit, connecting a first data bus to one of first and second internal buses and connecting a second data bus to the other one of the first and second internal buses according to a swapping control signal, a start pulse swapping circuit, receiving a first start pulse and a second start pulse to provide a first swap start pulse and a second swap start pulse according to the swapping control signal, a first shift register, triggered by the first swap start pulse to generate a first series of latch signals, a second shift register, triggered by the second swap start pulse to generate a second series of latch signals, a shift multiplexer, outputting a third series of latch signals by selecting the first series and second series of latch signals, a plurality of latch multiplexers, each configured to selectively transmit pixel data from the first or second internal bus according to a mode control signal, a plurality of latch units, configured to latch the pixel data from the latch multiplexers, and an output unit, configured to provide a plurality of driving voltages. | 01-27-2011 |
| 20110013853 | APPROACH FOR DETERMINING MOTION VECTOR IN FRAME RATE UP CONVERSION - One embodiment of the present invention sets forth a method for determining a first motion vector for a first block in a first frame. The method includes selecting a plurality of candidate blocks corresponding to the first block and a first set of candidate motion vectors for the plurality of candidate blocks from a reference frame, selecting one or more neighbor blocks neighboring the first block and a second set of motion vectors for the one or more neighbor blocks from the first frame, calculating an index based on a difference between the first block and the each candidate block, a reliability factor associated with the second set of the motion vectors, a first distance between the first block and each of the one or more neighbor blocks, and a second difference between each of the first set of candidate motion vectors and each of the second set of the motion vectors for each of the plurality of candidate blocks, selecting a matching block corresponding to the first block from the plurality of candidate blocks based on the indexes, and determining the first motion vector according to the matching block. | 01-20-2011 |
| 20110013852 | APPROACH FOR DETERMINING MOTION VECTOR IN FRAME RATE UP CONVERSION - One embodiment of the present invention sets forth a frame-up conversion method for preparing an interpolated frame. The method comprises (a) selecting a second block neighboring a first block within a first frame, (b) defining a first search window according to a second motion vector for the second block to identify a first matching block, (c) defining a second search window according to a location of the first matching block to identify a second matching block, (d) updating the first matching block to be the second matching block and updating the second search window and the second matching block or setting the second matching block as a target matching block based on whether the second matching block is the first matching block, (e) repeating (d) until the target matching block is set, determining the first motion vector by reference to the target matching block, and preparing the interpolated frame according to the first motion vector. | 01-20-2011 |
| 20100329323 | DATA RECEIVER AND METHOD FOR ADJUSTING THE SAME - A data receiver and a method for adjusting the same are provided. The data receiver has an equalizer, a clock data recovery unit, an equalizer controller, and a decoder. The equalizer compensates incoming signal according to a configuration, and outputs corrected signal. The CDR unit uses a clock to sample the corrected signal from the equalizer and generates phase information of the clock. The decoder decodes the raw data. Each cycle of the clock is divided into a plurality of phases, and the phase information indicates the one of the phases that the corrected signal sampled therein. In a testing mode, the equalizer controller applies a plurality of setup values to the configuration individually and records the phase information for tuning the configuration. Therefore, the accuracy of the equalizer is improved and the good signal quality is obtained. | 12-30-2010 |
| 20100328252 | SWITCHED-CAPACITOR TRACKING APPARATUS OF TOUCH PANEL AND OPERATING METHOD THEREOF - A switched-capacitor tracking apparatus including a variable capacitor, an auxiliary capacitor, and a plurality of switches, and an operating method thereof are provided. In a charge period, a first reference voltage charges a panel capacitor, and a second reference voltage charges the variable capacitor. In a detection period, a control circuit detects a parallel connected voltage of the panel capacitor and the variable capacitor. The control circuit compares a third reference voltage and the parallel connected voltage. According to a comparison result, the control circuit dynamically determines whether to parallel connect the auxiliary capacitor to the variable capacitor. If all the comparison results accumulated in a statistics period are a first logic value, then the control circuit increases a capacitance of the variable capacitor. Moreover, if all the comparison results are a second logic value in the statistics period, then the control circuit decreases the capacitance of the variable capacitor. | 12-30-2010 |
| 20100328126 | DIGITAL TO ANALOG CONVERTER - An embodiment of a digital to analog converter (DAC) with two outputs is provided. The DAC is controlled by an n-bits input signal and comprises a reference voltage circuit generating (2n+1) reference voltages, a first switch array and a second switch array. The first switch array receives and outputs 2 | 12-30-2010 |
| 20100326744 | TOUCH PANEL - A touch panel has a panel capacitor, a first capacitor, and a second capacitor. The panel capacitor and the first capacitor are charged and discharged cyclically according to a first phase signal and a second phase signal, such that an input voltage associated with the panel capacitor and the first capacitor is applied to a control circuit. The control circuit charges and discharges a second capacitor based on the input voltage and a reference voltage to compensate the difference between the input voltage and the reference voltage. The capacitance of the panel capacitor could be calculated based on the frequency of charging and discharging the second capacitor. | 12-30-2010 |
| 20100321413 | SYSTEM AND METHOD FOR DRIVING A LIQUID CRYSTAL DISPLAY - The invention describes a system and method for driving a display device that includes an array of pixels respectively coupled with a plurality of scanning lines along a first direction and a plurality of data lines along a second direction, each of the data lines being adapted to transmit a driving signal that is amplified in a high-driving mode of operation. In one embodiment, the method comprises reading digital data associated with each of a plurality of pixels along one or more scanning line, evaluating a distribution of gray scale levels for pixels coupled along the one or more scanning line based on the content of the digital data, and determining whether the distribution of gray scale levels meets a condition for generating a control signal to disable the high-driving mode of operation. | 12-23-2010 |
| 20100321412 | SYSTEM AND METHOD FOR DRIVING A LIQUID CRYSTAL DISPLAY - The invention describes a system and method for driving a display device that includes an array of pixels respectively coupled with a plurality of scanning lines along a first direction and a plurality of data lines along a second direction, each of the data lines being adapted to transmit a driving signal that is amplified in a high-driving mode of operation. In one embodiment, the method comprises reading first digital data associated with a first pixel, reading second digital data associated with a second pixel, and based on the content of the first and second digital data determining whether one or more condition for generating a control signal to disable the high-driving mode of operation is satisfied. | 12-23-2010 |
| 20100321370 | Display system and source driver thereof - A source driver includes a gamma voltage generator, in which the gamma voltage generator includes a first gamma resistor string and a second gamma resistor string. The first gamma resistor string receives a first gamma reference voltage and generates a plurality of first gamma voltages. The second gamma resistor string receives a second gamma reference voltage and generates a plurality of second gamma voltages, in which the second gamma voltages have different voltage values from the first gamma voltages. The switch circuit selects the first gamma voltages or the second gamma voltages as output gamma voltages according to a timing control signal. The digital to analog converter selects one of the output gamma voltages as a driving voltage corresponding to a received digital pixel data for driving a first pixel region or a second pixel region of the sub-pixel. | 12-23-2010 |
| 20100321362 | Gamma Voltage Generator and Source Driver - A gamma voltage generator adapted in a source driver and a source driver adapted in a display panel are provided. The source driver comprises a DAC and a gamma voltage generator comprising a first and a second arithmetic circuit and a gamma voltage string. The first arithmetic circuit receives a first gamma reference voltage and at least one first tuning voltage to supply a first reference voltage. The second arithmetic circuit receives a second gamma reference voltage and at least one second tuning voltage to supply a second reference voltage. The gamma resistor string has two ends coupled to the first and the second arithmetic circuits to receive the first and the second reference voltages respectively to generate a plurality of gamma voltages. The DAC receives digital pixel data and the gamma voltages to generate a plurality of driving voltages to a pixel array of the display panel. | 12-23-2010 |
| 20100321361 | Source driver - A source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a gamma resistor string, a second resistor, a plurality of first switches and a second switch. The first resistors are electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage, in which the first resistors have first ends and second ends for providing gamma voltages. The second resistor has a first end electrically connected to the gamma resistor string and a second end receiving a third gamma reference voltage. The first switches are uniformly conducted to the first ends or the second ends of the first resistors according to a timing control signal for passing the gamma voltages. | 12-23-2010 |
| 20100321282 | DISPLAY MODULE - A display module including a first circuit board, a display panel and at least a die is disclosed. The display panel is disposed on the first circuit board and electrically connected to the first circuit board through a bonding wire. The die is disposed on the first circuit board and electrically connected to the first circuit board. | 12-23-2010 |
| 20100315396 | TIMING CONTROLLER, DISPLAY AND CHARGE SHARING FUNCTION CONTROLLING METHOD THEREOF - A display, which includes a display panel, a timing controller, and a source driver is provided. The timing controller analyzes gray level distribution of a video data to obtain an analysis result. The source driver is coupled between the display panel and the timing controller for driving the display panel to display a corresponding frame according to a video signal provided by the timing controller, and further the timing controller enables or disables a charge sharing function of the source driver in the display according to the analysis result. As a result, the charge sharing function is enabled optionally during different charge sharing periods, and thus the power consumption and the operation temperature of the source driver could be reduced as compared with the prior art. | 12-16-2010 |
| 20100309213 | Adaptive Stepping-Control System and Method for Dynamic Backlight Control - An adaptive stepping-control system and method for dynamic backlight control (DBLC) is disclosed. A stepping-control unit adjusts output of a dynamic backlight control (DBLC) device, such that the backlight luminance generated from a backlight unit may change smoothly. The amount of change of the backlight luminance per unit time (or stepping rate) varies according to the content of the image data. | 12-09-2010 |
| 20100293405 | INTEGRATED CIRCUIT WITH REDUCED ELECTROMAGNETIC INTERFERENCE INDUCED BY MEMORY ACCESS AND METHOD FOR THE SAME - The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random codes according to a predetermined delay parameter. The request receiver obtains an input clock signal according to a plurality of data requests and spreads the spectrum of the input clock signal based on the random codes to derive a non-periodic output clock signal. The memory unit accesses image data to be displayed in response to the data requests and the output clock signal. | 11-18-2010 |
| 20100289953 | SYSTEM AND METHOD FOR PROCESSING MULTIMEDIA DATA USING AN AUDIO-VIDEO LINK - A multimedia processor includes an audio processor configured to process an audio input signal to generate an audio output signal and an assistant signal, and a video processor coupled with the audio processor and configured to process video input signal and the assistant signal to generate a video output signal simultaneously according to the video input signal and the assistant signal. Provided with the assistant signal, the video processor acquires more video processing-related information for rendering video content in a more realistic manner. Mal-motion detection can thus be prevented, and video quality can be improved. | 11-18-2010 |
| 20100289791 | SOURCE DRIVER AND DRIVING METHOD THEREOF - A source driver includes a plurality of first data channel pairs, a plurality of second data channel pairs, a first switch group, a second switch group, a third switch group, and a fourth switch group. Each of the first data channel pairs includes a first odd channel and a first even channel. The channels outputting voltages having the same polarity are short circuited together through the switch groups during a charge sharing period. As a result, the swings of the voltages of data lines coupled the corresponding channel are reduced, and further power consumption in the source driver could be reduced as compared with the related art. | 11-18-2010 |
| 20100283768 | Output Buffer Adapted to a Source Driver and Source Driver - An output buffer adapted to a source driver and a source driver are provided. The output buffer comprises an input and an output stage. The input stage comprises an input node, a first and a second output terminal. The output stage comprises a PMOS, a NMOS, a first and a second switches. The first and the second switch are connected between the gate of the PMOS, the first output terminal and the gate of the PMOS, the voltage supply respectively to both receive a latch signal. When the latch signal is in a first state, the first and the second switches disable the output stage. When the latch signal is in a second state, the first and the second switches enable the output stage to transfer an analog data from a DAC of the source driver to the output node connected to the drain of the PMOS and NMOS. | 11-11-2010 |
| 20100277216 | I/O Buffer Circuit - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 11-04-2010 |
| 20100259523 | SOURCE DRIVER - A source driver adaptive to driving a plurality of data lines on a display panel is provided herein. The source driver includes a plurality of channels and an output switch. The channels generate driving voltages to drive the display panel. The output switch includes a plurality of output multiplexers, so as to selectively connect the channels to data lines of the display. Each of the output multiplexers connects at least one of the channels to one of the data lines while being activated, wherein the output multiplexers are sequentially activated within a frame period. The source driver utilizes the output switch to sequentially delay a control signal, for controlling the output multiplexers to be sequentially activated within the frame period. Therefore, an electromagnetic interference can be reduced for ensuring the source driver operates normally. | 10-14-2010 |
| 20100259522 | DRIVER CIRCUIT OF DISPLAY DEVICE - A driver circuit includes a mode control unit and a plurality of source drivers to drive a display panel including N pixel cells on each scan line. Each source driver has M driving channels, and a first subset of the driving channels and a second subset of the driving channels are respectively in a first mode and a second mode according to a preset mode sequence, wherein M≧N. The 1 | 10-14-2010 |
| 20100259510 | Apparatus for data encoding in LCD Driver - A source driver includes an external data bus and a receiver configured to receive data signals from the external data bus, the receiver having an encoder configured to encode the data signals and output encoded signals such that a toggling rate of the encoded signals is less than a toggling rate of the data signals, an internal data bus configured to transmit the encoded signals, and a plurality of driving channels configured to receive the encoded signals from the internal data bus and to output driving voltages. | 10-14-2010 |
| 20100259465 | OUTPUT BUFFER, SOURCE DRIVER, AND DISPLAY DEVICE UTILIZING THE SAME - An output buffer providing a data signal to a data line and including an input stage circuit, an output stage circuit, and a control circuit is disclosed. The input stage circuit receives an input signal. The output stage circuit generates the data signal according to the input signal and includes a first P-type transistor. The control circuit selectively provides a first voltage or a second voltage to a bulk of the first P-type transistor. | 10-14-2010 |
| 20100259304 | POWER DETECTING DEVICE, POWER SUPPLY DEVICE USING THE SAME AND REFERENCE VOLTAGE GENERATOR - A power detecting device, a power supply device using the same, and a reference voltage generator are provided. The power detecting device adapted to detect a power voltage of a display device includes a bandgap voltage generating circuit, a voltage regulating circuit, and a power-on reset circuit. The bandgap voltage generating circuit provides a reference voltage via an output terminal thereof. The voltage regulating circuit and the power-on reset circuit are coupled to the output terminal of the bandgap voltage generating circuit. When the power voltage doesn't reach a threshold voltage, the voltage regulating circuit increases the reference voltage referred by the power-on reset circuit. When the power voltage reaches the reference voltage, the power-on reset circuit generates a reset signal to reset the display device. Therefore, when the power voltage doesn't reach a stable, the power-on reset circuit will not be incorrectly started by increasing the reference voltage. | 10-14-2010 |
| 20100259232 | SYSTEM AND METHOD FOR DRIVING A POWER SUPPLY DEVICE IN AN INITIAL ACTIVATION STAGE - The present application describes a system and method for driving a power supply device in an initial activation stage. In one embodiment, the method comprises providing in the power supply device at least one voltage regulator that is coupled with a voltage output adapted to supply a power voltage to a client device, receiving a signal indicative of an activation of the power supply device, and converting the at least one voltage regulator to an equivalent shunting circuit coupled between the voltage output and a reference voltage. Before power voltages are applied at the outputs of the power supply device, shunting paths are thus provided for releasing undesired currents. | 10-14-2010 |
| 20100220095 | SOURCE DRIVER WITH LOW POWER CONSUMPTION AND DRIVING METHOD THEREOF - A source driver adapted to drive a display panel and a driving method thereof are provided herein. The source driver includes an output buffer and a first pre-charge circuit. The output buffer has a first input terminal receiving a pixel signal and has both of a second input terminal and an output terminal coupled to the display panel. The first pre-charge circuit charges the output terminal of the output buffer to a preset voltage associated with the pixel signal for a pre-charge period. The output buffer is inactivated during the pre-charge period and is activated for a preset period after the pre-charge period. Therefore, power consumption of the source driver can be reduced. | 09-02-2010 |
| 20100220084 | SOURCE DRIVER WITH LOW POWER CONSUMPTION AND DRIVING METHOD THEREOF - A source driver with low consumption and the driving method thereof are provided herein. The source driver includes an output buffer with a first input terminal receiving a pixel signal, a second input terminal, and an output terminal coupled to the second input terminal and a display panel. The source driver also includes a pre-charge circuit pre-charges a first terminal of the display panel to a first preset voltage or a second preset voltage for a pre-charge period according to a polarity of a common voltage coupled to the display panel. The second preset voltage is smaller than the first preset voltage. The output buffer is inactivated during the pre-charge period and activated for a preset period after the pre-charge period. Therefore, the present invention reduces power consumption of the source driver. | 09-02-2010 |
| 20100188379 | Display and Method for Driving the Same - A display comprises a panel, a gate driver and a plurality of source drivers. The panel comprises a plurality of pixels arranged in an array. The gate driver is provided for selectively activating a gate line of the panel. The source drivers, during a line period, receive a plurality of transfer pulses, each of which corresponds to one of the source drivers. The source drivers drive one row of the pixels corresponding to the activated gate line, while triggered by the corresponding transfer pulse, wherein the transfer pulses are not all identical. A method for driving a display is also disclosed herein. | 07-29-2010 |
| 20100182307 | OUTPUT BUFFERING CIRCUIT, AMPLIFIER DEVICE, AND DISPLAY DEVICE WITH REDUCED POWER CONSUMPTION - An output buffering circuit of a driver device for a display includes a first amplifier circuit having a first input stage, coupled between an upper power supply and a lower power supply, and a first output stage, coupled between the upper power supply and a first intermediate power supply that is greater than the lower power supply, and a second amplifier circuit having a second input stage coupled between the upper power supply and the lower power supply, and a second output stage coupled between a second intermediate power supply that is lower than the upper power supply and the lower power supply. | 07-22-2010 |
| 20100182070 | OUTPUT BUFFER AND SOURCE DRIVER UTILIZING THE SAME - An output buffer including a first input stage circuit, a first output stage circuit, a second output stage circuit, a first switching module, and a second switching module is disclosed. The first output stage circuit is coupled to a first data line. The second output stage circuit is coupled to a second data line. The first switching module is coupled between the first input stage circuit and the first output stage circuit. The second switching module is coupled between the first input stage circuit and the second output stage circuit. | 07-22-2010 |
| 20100177935 | METHOD OF MOTION DETECTION USING ADAPTIVE THRESHOLD - A method of motion detection using an adaptive threshold, adaptive for determining whether a plurality of target pixels in a current scan line are moving pixels or not, is provided. First, a first threshold is given for determining whether the target pixels in the current scan line are moving pixels. Then, a number of moving pixels in a previous scan line of the current scan line is calculated and determined whether larger than a second threshold. If the number of moving pixels is larger than the second threshold, the first threshold is adjusted by a decrement, and then whether the target pixels in the current scan line are moving pixels is determined by using the adjusted first threshold. | 07-15-2010 |
| 20100177934 | METHOD OF MOTION DETECTION USING MOTION INFORMATION OF NEIGHBORING PIXELS - A method of motion detection using motion information of neighboring pixels, adaptive for determining whether a plurality of target pixels in a current field are moving pixels, is provided. First, it is determined whether a neighboring pixel in a previous field corresponding to the target pixel in the current field is the moving pixel. If the neighboring pixel in the previous field is the moving pixel, the target pixel is determined as the moving pixel and otherwise it is further determined whether the neighboring pixels around the target pixel in the current field are the moving pixels. If the neighboring pixels in the current field are the moving pixels, then the target pixel is determined as the moving pixel. Accordingly, the mistakenly judged static pixels can be found and modified to moving pixels, such that the accuracy of motion detection can be increased. | 07-15-2010 |
| 20100177241 | APPARATUS AND METHOD FOR MOTION ADAPTIVE DE-INTERLACING WITH CHROMA UP-SAMPLING ERROR REMOVER - An apparatus and a method for motion adaptive de-interlacing with chroma up-sampling error remover are provided. Wherein, a motion detector determines moving pixels and static pixels in a target scan line. A first CUE remover and a second CUE remover remove the CUE of the target scan line in the previous field and the CUE of the adjacent scan lines in the current field, respectively. A de-interlace unit de-interlaces the adjacent scan lines to obtain a de-interlaced second scan line. A selector selects output data of the first CUE remover or the de-interlace unit as data of the target scan line according to a result of motion detection of the motion detector. A merging unit merges the adjacent scan line output by the second CUE remover and the target scan line output by the selector to output two scan lines of an output field. | 07-15-2010 |
| 20100177199 | METHOD FOR MOTION DETECTION OF HORIZONTAL LINE - A method for motion detection of a horizontal line is provided. First, a horizontal motion area of the horizontal line is detected according to differences between corresponding target scan lines in adjacent fields. Next, the horizontal line within a horizontal motion area in a current field and in a previous field are respectively detected. Then, the horizontal motion of the horizontal line is detected if the horizontal line is detected in both the current field and the previous field. Finally, pixels of the horizontal line in the current field are set as static pixels and data of the horizontal line is calculated through de-interlacing of corresponding horizontal lines in the previous field and in a next field if the horizontal motion of the horizontal line is detected. As a result, the flickers occurred in the generated field data can be removed and the quality of vision can be improved. | 07-15-2010 |
| 20100177066 | SOURCE DRIVER AND DRIVING METHOD THEREOF - A source driver and a driving method thereof are provided. The source driver is adapted to a display panel. The source driver includes an output buffer and a regulating unit. The output buffer has an input terminal and an output terminal. The input terminal of the output buffer receives a pixel signal. The output terminal of the output buffer is coupled to the display panel for outputting an output signal. The regulating unit is coupled to the output terminal of the output buffer, for providing a charging current or a discharging current to the output terminal of the output buffer according to a polarity of the pixel signal. Thereby, a slew rate of the output signal is increased. | 07-15-2010 |
| 20100176749 | LIQUID CRYSTAL DISPLAY DEVICE WITH CLOCK SIGNAL EMBEDDED SIGNALING - A display device includes a display panel, a timing controller generating a timing controlling signal having a plurality of states, each state representing both data information and clock information, and a source driver receiving and decoding the timing controlling signal to recover the data information and the clock information for generating a clock signal and a data signal for driving the display panel. | 07-15-2010 |
| 20100176747 | OUTPUT BUFFER AND SOURCE DRIVER USING THE SAME - An output buffer and a source driver using the same are provided. The output buffer includes an input stage module, a first output stage module, a second output stage module, and a first control module. The input stage module generates a first bias signal via a first connection terminal according to a driving signal and a output signal. The first output stage module generates the output signal in response to the first bias signal via an output terminal of the output buffer. The second output stage module generates a second bias signal in response to the first bias signal via a second connection terminal, and controls a first switch in the second output stage module. The first control module selectively connects a first current source to the output terminal of the output buffer or to the second connection terminal of the second output stage module according to an indication signal. | 07-15-2010 |
| 20100171531 | OUTPUT BUFFER WITH HIGH DRIVING ABILITY - An output buffer including a first differential input stage, a primary output stage, and a secondary output stage is provided herein. The first differential input stage respectively receives a first and a second input signals via a first and a second input terminals. The primary output stage includes a first and a second output stages. The first output stage provides at least one first level voltage according to the first and the second input signals, and the second output stage controlled by the first level voltage drives an output terminal of the output buffer to a target level. The secondary output stage includes a comparator and a third output stage. The comparator compares the induced currents in the first differential input stage, and thereby generates a control voltage. The third output stage controlled by the control voltage drives the output terminal of the output buffer to the target level. | 07-08-2010 |
| 20100164958 | DISPLAY METHOD OF ON SCREEN DISPLAY (OSD) AND DISPLAY SYSTEM THEREOF - A display method of an OSD and a display system are provided herein. In the display method, a plurality of symbols are respectively compressed into a plurality of codewords according to an encoding process, and the codewords are stored in a memory module. A plurality of index values respectively corresponding to the symbols are established in a codebook and the codebook is stored in the memory module, wherein the index values are address information of storing the codewords in the memory module. The index value corresponding to a designation symbol of the symbols is searched out from the codebook according to an input command corresponding to the designation symbol, and a decoding process is performed on the codeword corresponding to the designation symbol from the memory module for displaying the designation symbol on the display. Therefore, a storage space of the memory module is reduced by compressing the symbols. | 07-01-2010 |
| 20100164926 | SOURCE DRIVER - A source driver adapted to drive a plurality of data lines on a display panel is disclosed. The source driver includes a first output buffer, a second output buffer, a multiplexer, and a first regulating unit. The first and the second output buffers respectively enhance transmission intensities of a first and a second pixel signals. The first regulating unit regulates a slew rate of the first pixel signal outputted from the first output buffer to match a slew rate of the second pixel signal outputted from the second output buffer. The multiplexer coupled to the regulating unit selectively transmits the first and the second pixel signals to one of the odd data lines and one of the even data line, or to the one of the even data lines or the one of the odd data lines, according to a control signal. | 07-01-2010 |
| 20100164925 | SOURCE DRIVER, DISPLAY DEVICE USING THE SAME AND DRIVING METHOD OF SOURCE DRIVER - A source driver, a display device and a driving method of the source driver are disclosed. The source driver adapted to a display panel includes a plurality of driving channels, wherein the display panel includes N pixel cells on each of a plurality of scan lines. The 1 | 07-01-2010 |
| 20100158320 | METHOD OF MOTION DETECTION USING CONTENT ADAPTIVE PENALTY FUNCTION - A for motion detection using a content adaptive penalty function, adaptive for determining whether a target pixel in a current field is a moving pixel or not, is provided. First, a penalty function is determined according to characteristics of a plurality of neighboring pixels of the target pixel. Next, a plurality of differences between the corresonding neighboring pixels of the target pixel in adjacent fields are calculated. The difference is then weighted by the penalty function according to the magnitude of the difference and the weighted differences are summed together. Finally, the sum of the weighted differences is compared with a sum threshold, so as to determine whether the target pixel is the moving pixel or not. | 06-24-2010 |
| 20100142843 | METHOD FOR ADAPTIVELY SELECTING FILTERS TO INTERPOLATE VIDEO DATA - A method for adaptively selecting filters to interpolate video data is provided. In the present method, when receiving video data encoded by a 4:2:2 sampling format, a plurality of filters having different weights are adaptively selected to convert the color components in the video data to a 4:4:4 sampling format based on the differences of luminance and color components among a target pixel and neighboring pixels thereof. Accordingly, the blurs occurred in an area with large color variation can be removed or reduced, such that the interpolated color components can be accepted by human eyes more easily. | 06-10-2010 |
| 20100142812 | Method of color components compression - A method of color components compression is provided. In the present method, when receiving video data encoded by a 4:4:4 sampling format, color components of each set of neighboring pixels in the video data is down-sampled and a first difference of the color components between the video data before and after down-sampling in a down-sampling mode is calculated. Then, the color components of each pixel in the video data are truncated and a second difference of the color components between the video data before and after truncation in a truncation mode is calculated. The first difference and the second difference are compared and the down-sampling mode or the truncation mode that has a smaller difference is selected to compress the video data into a 4:2:2 sampling format. | 06-10-2010 |
| 20100141324 | Mixed-Voltage Tolerant I/O Buffer and Output Buffer Circuit Thereof - An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein. | 06-10-2010 |
| 20100134683 | SIGNAL PROCESSING DEVICE AND METHOD - A signal processing device with high efficiency of teletext information processing is provided. The signal processing device is configured to receive and encode a transport stream for display, wherein the transport stream provides teletext information associated with a plurality of teletext lines and video information associated with a plurality of video lines. The video signal processing device includes a memory configured to store line enable signals and line data associated with the teletext lines and the video lines, a VBI controller coupled to the memory, configured to read the memory to obtain the line data associated with enabled teletext lines of the teletext lines, and an TV encoder coupled to the VBI controller, configured to receive and encode the line data associated with the enabled teletext lines for display. | 06-03-2010 |
| 20100134400 | LIQUID CRYSTAL DISPLAY DEVICE WITH REDUCED POWER CONSUMPTION AND DRIVING METHOD THEREOF - A liquid crystal display (LCD) device with reduced power consumption is provided with a plurality of data lines, a plurality of gate lines, and at least one multiplexer. Each multiplexer can comprise a plurality of switches respectively connected to the corresponding data lines and controlled by a plurality of clock signals and configured to receive an image signal, and selectively output the image signal to one of the data lines via the switches. During a driving period, one of the gate lines can be asserted, and the switches can be turned on simultaneously, then only the first one of the switches remains turned on to transmit the image signal to the corresponding data line, and then the first one of the switches are turned off and the other switches are sequentially turned on one at a time to transmit the image signal to the corresponding data lines. | 06-03-2010 |
| 20100117940 | TRANSREFLECTIVE DISPLAY APPARATUS AND DRIVING METHOD THEREOF - A driving method and a transreflective display apparatus are provided herein. In the driving method, a plurality of voltage-to-transparency curves are provided. An ambient light intensity of the display apparatus is detected for determining a display mode, wherein the display mode is either a transmissive mode or a reflective mode. Next, one of the voltage-to-transparency curves is selected according to the display mode and the ambient light intensity for driving the display apparatus. Therefore, by referring a proper voltage-to-transparency curve to drive the display apparatus, the display quality of the display apparatus can be enhanced. | 05-13-2010 |
| 20100109157 | CHIP STRUCTURE AND CHIP PACKAGE STRUCTURE - A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers. | 05-06-2010 |
| 20100103152 | SOURCE DRIVING CIRCUIT WITH OUTPUT BUFFER - A source driving circuit adapted to drive a display panel is provided herein. The source driving circuit includes a first output buffer and a second output buffer responsible for enhancing signals with different polarities respectively. As for the first output buffer, the first output buffer includes a first differential input stage, a first output stage and a second output stage. The first output stage includes a first level adjustment circuit and a first self-bias providing circuit. The first level adjustment circuit provides a first level voltage according to input signals received by the first differential input stage, such that the second output stage thereby provides a first charge current and a second charge current to output a first output signal based on the first level voltage. The first self-bias providing circuit provides a first biased voltage associated with one input signal to control the first level adjustment circuit to operate. | 04-29-2010 |
| 20100097117 | Mixed-voltage I/O buffer - A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current. | 04-22-2010 |
| 20100091180 | SIGNAL CONVERSION APPARATUSES AND DISPLAY SYSTEM - A signal conversion apparatus is provided. A video input interface receives a video signal encoded in a first format from a host device. An audio input interface receives an audio signal encoded in a second format from the host device. A conversion unit is coupled to the video input interface and the audio input interface, receives the video signal and the audio signal therefrom, and converts the video signal and the audio signal into an output signal encoded in a predetermined format. An output interface receives the output signal and transmits the output signal to the display device. | 04-15-2010 |
| 20100079678 | DEMODULATOR DEVICE AND DEMODULATION METHOD FOR REDUCING PCR JITTER - A demodulator device for a digital TV receiver includes a symbol-deinterleaver performing symbol-based deinterleaving, a bit-deinterleaver performing bit-based deinterleaving, a demapper performing demapping, and a Viterbi decoder performing Viterbi decoding, wherein one of the symbol-deinterleaver, the bit-deinterleaver, and the demapper includes a memory storing data that has undergone symbol-deinterleaving, and another one of the symbol-deinterleaver, the bit-deinterleaver, and the demapper or the Viterbi decoder reads the data that has undergone symbol-deinterleaving with an adaptively optimized throughput rate. | 04-01-2010 |
| 20100079431 | OUTPUT BUFFER AND SOURCE DRIVER USING THE SAME - An output buffer and a source driver for a display panel are provided. The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage. The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal. The bias module provides a bias current to the differential input stage. The output stage has a second output terminal coupled to the first input terminal for providing an output current to the second output terminal based on a signal of the first output terminal. The feedback module adjusts the bias current and the output current based on the first input signal and the second input signal. The output buffer has ability of switching the output voltage to be low level and high level in high-speed. | 04-01-2010 |
| 20100066900 | IMAGE PROCESSING METHOD - An image data processing method. The method includes fetching a plurality of image layers to be overlappingly displayed on a display area; expanding the fetched image layers to have the same size as the display area of a video frame; merging the expanded image layers in an interleaving manner; and storing the merged image layer in a memory device sequentially. | 03-18-2010 |
| 20100060840 | CHIP-ON-GLASS PANEL DEVICE - A chip-on-glass panel device includes a glass substrate having a pixel area, an integrated circuit area, and a fan out area, the fan out area located between the pixel area and the IC area, a plurality of integrated circuit devices arranged within the integrated area of the glass substrate, each of the plurality of integrated circuit devices have | 03-11-2010 |
| 20100060621 | SOURCE DRIVER DEVICE AND DISPLAY DEVICE HAVING THE SAME - A source driver device for driving a display panel includes a gamma voltage generator having a storage element and a plurality of gamma digital-to-analog converters, a data digital-to-analog converter coupled to the gamma voltage generator, and a receiver for receiving input display data from a data bus, for parsing the input display data to transmit generated display data to the data digital-to-analog converter, and for transmitting a plurality of gamma data signals to the storage element, wherein each of the plurality of gamma digital-to-analog converters receive the plurality of gamma data signals from the storage element for generating a plurality of reference voltage signals based on the corresponding gamma data signals, and wherein the data digital-to-analog converter is coupled to the receiver to receive the generated display data, according to the generated plurality of reference voltage signals generated from the gamma digital-to-analog converters, and to generate a driving voltage signal based on the generated display data for driving the display panel. | 03-11-2010 |
| 20100060557 | DATA DE-SKEW BLOCK DEVICE AND METHOD OF DE-SKEWING TRANSMITTED DATA - A source driver device includes a de-skew block device for receiving image data and clock signals, the de-skew block device has a receiver for receiving a clock signal and image data, a delay lock loop for generating a plurality of sub-clock signals, each having different delay times increasing in order, based on the clock signal, an edge detection unit for finding an edge of the data by the sub-clocks, and selecting one from the sub-clocks based on the edge as a de-skewed clock, and a data de-skew unit for sampling the image data by the de-skewed clock signal to output de-skewed image data and the de-skewed clock signal, and a plurality of channels for receiving the de-skewed image data and the de-skewed clock signal to drive an LCD panel. | 03-11-2010 |
| 20100052964 | Digital to Analog Converter and Display Driving System Thereof - A digital to analog converter of the source driver includes a gamma voltage generator and a data decoder. The gamma voltage generator receives a gamma code to generate an analog gamma voltage. The gamma voltage includes a register, a reference decoder, and a calibrator. The register stores the gamma code. The reference decoder converts the gamma code from the register into the analog gamma voltage. The calibrator, receiving a reference gamma voltage in a calibration mode, includes a comparator and a counter, in which the counter tunes the gamma code according to the control signal generated by the comparator comparing the analog gamma voltage and the reference gamma voltage. The data decoder receives digital pixel data and selects one gamma voltage as a driving voltage based on the digital pixel data. | 03-04-2010 |
| 20100052764 | LEVEL SHIFTER CONCEPT FOR FAST LEVEL TRANSIENT DESIGN - A driving circuit is provided by the invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between an operation voltage and a power supply terminal of the first buffer for controlling a power-supplying time of the first buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter. | 03-04-2010 |
| 20100052737 | SOURCE DRIVING CIRCUIT FOR PREVENTING GAMMA COUPLING - During transition, level shifters in a source driver output logic high signals to PMOS DACs and output logic low signals to NMOS DACs for shutting down current paths in the PMOS DACs and in the NMOS DACs. Therefore, during transition, the PMOS DACs and the NMOS DACs are at high-impedance stage for preventing gamma coupling effect. | 03-04-2010 |
| 20100045319 | WAFER AND TEST METHOD THEREOF - A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer. | 02-25-2010 |
| 20100040092 | RECEIVER FOR REDUCING PCR JITTER - A receiver receiving a transport stream to demodulate the transport stream into a final output stream, wherein the transport stream comprises a plurality of symbols at least one of which carrying at least one program clock reference (PCR) value, and the final output stream comprises a plurality of demodulated symbols each comprising a plurality of packets, is disclosed. The receiver can comprise a Reed-Solomon decoder configured to decode the transport stream to generate a MPEG (Motion Pictures Expert Group) packet, a MPEG memory configured to store the MPEG packet, and a descrambler configured to read the MPEG packet from the MPEG memory with a throughput rate and descramble the MPEG packet into one of the packets of the demodulated symbols of the final transport stream. The throughput rate is decreased to reduce bursts of the packets of the demodulated symbols of the final output stream. | 02-18-2010 |
| 20100025083 | FLEXIBLE CIRCUIT BOARD - A flexible circuit board uses a specific structure to alleviate mechanical stress thereof. The flexible circuit board has a flexible film, a plurality of inner leads, a plurality of outer leads, and a plurality of connection portion. Each of the connection portions a corresponding one of the inner leads with a corresponding one of the outer leads. A first width of the inner leads is greater than a second width of the outer leads. Due to rounded concave sections and rounded convex sections of the connection portions, if the flexible circuit board is bent, the mechanical stress around corners of joint portions of the connection portions with the inner leads and the outer leads could be alleviated. | 02-04-2010 |
| 20100013871 | BACKLIGHT CONTROLLER, DISPLAY DEVICE USING THE SAME AND METHOD FOR CONTROLLING BACKLIGHT MODULE - A backlight controller, a display device using the same and a method for controlling a backlight module are provided. The backlight controller includes a temporal weighting module and a dimming controlling module. The temporal weighting module calculates a weight sum of a first backlight luminance provided in a current frame and a target backlight luminance to serve as an adjusted backlight luminance. The target backlight luminance is obtained according to an image content of the current frame. The dimming controlling module increases or decreases the adjusted backlight luminance by a step value according to the target backlight luminance and generates a second backlight luminance provided in a next frame. Therefore, a backlight luminance of the backlight module not only can be smoothly adjusted to the target backlight luminance at high speed for avoiding backlight flicker, but also can be adaptive to image content for saving electric power consumption. | 01-21-2010 |
| 20100002729 | SYNCHRONIZATION DEVICES AND METHODS - An exemplary embodiment of a synchronization device is provided. The synchronization device includes a memory, a demultiplexer, a comparator, and a sampling rate converter. The synchronization device has a system time clock (STC) and generates an output data with a first sampling rate. The demultiplexer receives a bit stream and extracts a packetized elementary stream (PES) from the bit stream. The demultiplexer writes the PES into the memory. The comparator obtains a presentation time stamp (PTS) from the PES and compares the PTS and the STC. The sampling rate converter has a converting factor, samples the PES in the memory, and generates the output data according to the PES. The sampling rate converter changes the converting factor according to the compared result of the comparator. | 01-07-2010 |
| 20090309820 | GATE DRIVER AND DISPLAY PANEL UTILIZING THE SAME - A gate driver including a shift register, a level shifter, an output buffer, and a processing unit. The shift register generates a shifted signal. The level shifter generates a level signal according to a first operation voltage, a second operation voltage and the shifted signal. The output buffer provides a scan signal according to the level signal. The processing unit controls the level signal to follow the second operation voltage when the first operation voltage equals to a first preset value and the second operation voltage is higher than a second preset value less than the first preset value. | 12-17-2009 |
| 20090309169 | Structure for Preventing Leakage of a Semiconductor Device - A structure for preventing leakage of a semiconductor device is provided. The structure comprises a shielding line, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The shielding line is wider than the conductive line. | 12-17-2009 |
| 20090302483 | STACKED DIE PACKAGE - The invention provides a stacked die package. The package includes a lead frame having a plurality of the leads and a stack of dice disposed thereon, in which the upper die may be electrically connected to the leads via at least one transit area on the lower die to transfer a power signal or a ground signal. | 12-10-2009 |
| 20090300232 | DATA TRANSMISSION METHOD BETWEEN A HOST DEVICE AND A DISPLAY APPARATUS - A display apparatus is provided. The display apparatus is coupled to a host device and comprises a control module and a microprocessor. The control module sequentially receives data packets from the host device, acquires data content from each of the received data packets, collects each of the data contents, and, when data transfer has been completed, sends a control signal. The microprocessor is coupled to the control module and, in response to the control signal, acquires the collected data contents from the control module, decodes the acquired data contents to generate a decoded result and performs at least one operation corresponding to the decoded result to generate a reply information to the host device. | 12-03-2009 |
| 20090300089 | FINITE IMPULSE RESPONSE FILTER AND METHOD - An N-order finite impulse response (FIR) filter with a symmetric coefficient set is provided. An input device receives a serial of input signals according to a sampling frequency and stores the received data into the first and second memories by turns. A first calculating device reads the N successively received data from the first and second memories according to an operation frequency and generates a plurality of first calculation values, wherein each of the read data corresponds to a coefficient of the symmetric coefficient set and the first calculation value is generated by summing the read data corresponding to the same coefficient. A second calculating device generates a plurality of second calculation values, wherein the second calculation value is generated by multiplying the first calculation value and the corresponding coefficient. A third calculating device accumulates the second calculation values to generate an output signal. | 12-03-2009 |
| 20090295844 | COLOR-SEQUENTIAL DISPLAY METHOD - A display method for driving a color-sequential display of an electronic device is provided. When the electronic device is not at low power mode, a first image is displayed first by using a second color data and a first color data of the first image sequentially to drive the display. Next, a second image is displayed by using a second color data and a third color data of the second image sequentially to drive the display. When the electronic device is at low power mode, the respective luminance of the first and the second images are obtained. Then, the respective luminance of the first image and the second image are sequentially used to drive the display. | 12-03-2009 |
| 20090295762 | DISPLAY AND METHOD THEREOF FOR SIGNAL TRANSMISSION - A display and a method for signal transmission of the display are provided. The display has a source driver, a panel, and a timing controller having at least one data pin and a clock signal pin. The timing controller sends a clock signal to the source driver via the clock signal pin, and then sends a start pulse pattern to the source driver via the at least one data pin such that the source driver is notified to receive setting signals and display data signals. The source driver drives the panel according to the setting signals and the display data signals received from the timing controller via the at least one data pin. One or more of the setting signals are received by the source driver within every clock of the clock signal. | 12-03-2009 |
| 20090295754 | TOUCH PANEL - Touch panels comprising a bias line biased at a bias voltage, a select line, a readout line, a photo cell and a readout circuit. The photo cell comprises a first photo switch, a second photo switch and a storage capacitor. The first photo switch and the storage capacitor is coupled in series between the readout line and the bias line, and the first photo switch is further controlled by the select line. The second photo switch is connected between the readout line and the bias line. The readout circuit and the select line are managed by a reset mode, an exposure mode and a readout mode. The voltage variation of output terminal of the readout circuit is used in obtaining the state of the photo cell. | 12-03-2009 |
| 20090292946 | REPAIR MODULE FOR MEMORY, REPAIR DEVICE USING THE SAME AND METHOD THEREOF - A repair module for repairing one of n bit lines through m bit bus in a memory, a repair device using the same, and a method thereof are provided herein, wherein m≧n. In the repair method, a switching control signal and a selecting control signal are generated according to an index value of the one of n bit lines. A dummy line is switched to the one of n bit lines by shifting from 1 | 11-26-2009 |
| 20090289947 | SYSTEM AND METHOD FOR PROCESSING DATA SENT FROM A GRAPHIC ENGINE - An image processing system is provided comprising a memory, a graphic engine and a data processing module. The graphic engine generates a sequence of input data, wherein each of the input data has an address information pointing to a corresponding memory address of the memory. The data processing module sequentially receives the input data from the graphic engine, buffers each of the received data into a corresponding buffer according to the address information thereof, and outputs buffered data in a buffer to the memory when the buffer is full, wherein memory addresses of the outputted data are continuous. | 11-26-2009 |
| 20090284512 | COMPACT LAYOUT STRUCTURE FOR DECODER WITH PRE-DECODING AND SOURCE DRIVING CIRCUIT USING THE SAME - Provided is a decoder for receiving a digital data and outputting an analog voltage. The decoder comprising a main switch array, a first pre-decoding switch array, and a second pre-decoding switch array. The main switch array receives the digital data and outputs a voltage if the digital data is in a first range. The first pre-decoding switch array is for receiving the digital data, pre-decoding a part of the digital data, and outputting a voltage if the digital data is in a second range. The second pre-decoding switch array is for receiving the digital data, pre-decoding the part of the digital data, and outputting a voltage if the digital data is in a third range. Combination of the main switch array, the first pre-decoding switch array, and the second pre-decoding switch array is in a substantially rectangular layout structure. | 11-19-2009 |
| 20090273997 | Controlling Apparatus and Controlling Method for Controlling a Pre-Charge Activity on a SRAM Array - A controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array are provided. The controlling apparatus comprises: a detecting module, a controlling module and a pre-charge module. The detecting module is to detect whether the row address of the SRAM array in operation is changed and generate a row-changing signal according to the detection result; the controlling module is to detect an operation mode of the SRAM array and generate a disable signal according to the row-changing signal and the operation mode; and the pre-charge module is to generate a pre-charge signal according to a pseudo-pre-charge signal and the disable signal, wherein the pre-charge signal substantially controls the pre-charge activity on the SRAM cell in operation. | 11-05-2009 |
| 20090268166 | PROJECTION SYSTEM - A projection system including an illumination unit, a polarization conversion unit, a light valve, a projection lens, and a polarizing beam split (PBS) element is provided. The polarization conversion unit includes a V-shaped PBS element, a wave plate, and two reflective surfaces. The V-shaped PBS element includes a first PBS portion and a second PBS portion. The first PBS portion is adapted to be passed through by a first partial beam with a first polarization direction and reflect a second partial beam with a second polarization direction. The second PBS portion is adapted to be passed through by a third partial beam with the first polarization direction and reflect a fourth partial beam with the second polarization direction. The wave plate is disposed in the transmission paths of the first partial beam and the third partial beam. The reflective surfaces are located at opposite sides of the V-shaped PBS element. | 10-29-2009 |
| 20090267584 | TRANSIENT DETECTION CIRCUIT - A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level. | 10-29-2009 |
| 20090262954 | AUDIO SIGNAL ADJUSTING METHOD AND DEVICE UTILIZING THE SAME - An audio signal adjusting device is disclosed. The audio signal adjusting device for adjusting the amplitudes of digital audio signals received from a decoder that decodes the audio signals received from an antenna comprises a buffer, a signal abnormality detector and a fading processor. The buffer stores the digital audio signals received from the decoder. The signal abnormality detector detects the abnormality of the digital audio signals stored in the buffer and outputs a fading out enable instruction when the digital audio signals are detected as abnormal. The fading processor fades out the amplitudes of the digital audio signals stored in the buffer according to a fading out algorithm after receiving the fading out enable instruction, to output faded digital audio signals. | 10-22-2009 |
| 20090262246 | Method and apparatus for determining sound standard for input sound signal - A method for determining a sound standard for an input sound signal includes the following steps. Firstly, the input sound signal is filtered to obtain a first filtered signal corresponding to a first frequency and a second filtered signal corresponding to a second frequency. Next, the first filtered signal is frequency-demodulated to obtain a first demodulated filtered signal, and whether the input sound signal contains a FM analog component corresponding to the first frequency is determined accordingly. Next, the second filtered signal is decoded according to a digital sound standard to obtain a bit stream. Then, the bit steam is interpreted according to the digital sound standard, and whether the input sound contains a digital component corresponding to the digital sound standard is determined accordingly. Then, whether the input sound signal matches one of known sound standards is determined based on the determined results above. | 10-22-2009 |
| 20090261747 | Control system for multiple fluorescent lamps - The present invention is directed to an apparatus that drives a lighting system with multiple lamps. A phase shift mechanism is produced either by a digital method, an analog method, or a mixture of the two methods. In a digital method, phase shifts are generated by digital circuits comprising counters, a divider, an adder, and a comparator. The digital circuits analyze the signal and use the necessary information to form a series of phased driving signals. In an analog method, phase shifts are generated by analog circuits comprising ramp waveform generators, comparators, and at least one shot generator. Also, an apparatus for driving a lighting system with multiple lamps can be realized by mixing the two methods mentioned above. | 10-22-2009 |
| 20090259324 | BROADCAST DEVICES - A broadcast device is disclosed, comprising a first memory unit, a demultiplexer unit, first and second flip-flop units, and first and second playback units. The demultiplexer unit generates an audio bit stream, which comprises a plurality of data packages, according to a transport stream. The demultiplexer unit writes the data packages into the first memory unit with a writing pointer. The first flip-flop unit reads and stores the data packages from the first memory unit. The first playback unit reads the data packages from the first flip-flop unit and decompresses the data packages for generating a first digital playback signal. The second flip-flop unit reads and stores the data packages from the first memory unit. The second playback unit reads the data packages from the second flip-flop unit and samples the data packages to generate a second digital playback signal to an external receiver outside of the broadcast device. | 10-15-2009 |
| 20090251495 | Liquid crystal driving circuit - The liquid crystal driving circuit for converting pixel values into driving voltages on a plurality of channels includes a reference voltage generating circuit, a plurality of buffer amplifiers, an output selection circuit coupling, and a plurality of switch circuits. The reference voltage generating circuit generates a plurality of grayscale reference voltages. Each buffer amplifier corresponds to one of the grayscale voltages and is powered by a supply voltage. The output selection circuit couples to the channels to outputs of the buffer amplifiers selected according to the pixel values. The switch circuits coupes inputs of the selected buffer amplifiers to receive the corresponding grayscale reference voltages, and couples inputs of the unselected buffer amplifiers to receive the supply voltage. | 10-08-2009 |
| 20090251403 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel. The liquid crystal display panel comprises a first display matrix, a second display matrix, a first gate electrode group, a second gate electrode group and a data electrodes group. The first display matrix comprises first display cells arranged in N rows and M columns; the second display matrix comprises second display cells arranged in N rows and M columns. The first gate electrode group comprises first gate electrodes respectively coupled to the first display matrix and the second gate electrode group comprises second gate electrodes respectively coupled to the second display matrix. The data electrodes group comprises data electrodes respectively coupled to the first display matrix and the second display matrix, wherein an m-th data electrode is coupled to an m-th column of the first display cells and an m-th column of the second display cells. | 10-08-2009 |
| 20090244946 | DC-AC CONVERTER - A DC-AC converter includes a signal generating module, a first switch, a first capacitor, a transformer, and a trigger signal generating module. The signal generating module generates a pulse width modulation (PWM) signal according to a trigger signal. The first switch has a control terminal receiving the PWM signal, and a first terminal and a second terminal coupled to a first terminal and a second terminal of the first capacitor respectively. The transformer has a primary winding coupled to the second terminal of the first switch, and a secondary winding coupled to a load. The transformer generates a driving signal to the load according to a signal variation of the primary winding. The trigger signal generating module compares a first signal outputted from the second terminal of the first switch with a phase delay signal thereof and thereby generates the trigger signal for controlling the frequency of the PWM signal. | 10-01-2009 |
| 20090244438 | METHOD OF CONTROLLING BACKLIGHT MODULE, BACKLIGHT CONTROLLER AND DISPLAY DEVICE USING THE SAME - A method of controlling backlight module, a backlight controller and a display device using the same are provided herein. First, an image having a plurality of regions is received, wherein the image is displayed by a plurality of color backlights which are provided from the backlight module. Next, a first average of a characteristic in a specific region of the image is calculated, wherein the specific region is one of the regions. According to the first average of the characteristic and a weight function, a characteristic weight is calculated. Next, one of the color backlights provided to the specific region is adjusted according to the characteristic weight. Therefore, adjusting the color backlights according to the image content can enhance the displaying quality of the image and adaptively reduce the artifacts perceived by human eyes in different images. | 10-01-2009 |
| 20090243499 | METHODS FOR DRIVING AN OLED PANEL - A method for driving an organic light emitting display (OLED) panel having a plurality of organic light emitting diodes is provided. The organic light emitting diodes are coupled to a plurality of segment lines and a plurality of common lines in a matrix structure. The organic light emitting diodes coupled to the same common lines are divided into a plurality of groups according to colors of the OLED panel. Driving currents are provided to the organic light emitting diodes of the groups according to a plurality of pulse width modulation (PWM) manners. The PWM manners generate waveforms having pulse width corresponding to grayscale in a period, wherein each PWM manner corresponds to different colors of the OLED panel. | 10-01-2009 |
| 20090238069 | DEVICE AND METHOD FOR CONTROLLING PROGRAM STREAM FLOW - A device for controlling program stream flow is described. The device is capable of saving power during computation. The device may include a de-multiplex unit and a direct memory access controller. The de-multiplex unit, for de-multiplexing a plurality of data, may include a request module for generating a request signal. The direct memory access controller is for receiving the request signal. The direct memory access controller obtains a plurality of data from a bus and sends the plurality of data to the de-multiplex unit according to the request signal. | 09-24-2009 |
| 20090237346 | INVERTER CIRCUIT OF DRIVING A LAMP AND BACKLIGHT MODULE USING THE SAME - An inverter circuit for driving a lamp and a backlight module using the same are provided. The inverter circuit includes a signal generation module, a switching unit, a first capacitor, a transformer and a first detecting module. The signal generation module generates a pulse width modulation (PWM) signal, wherein the duty cycle of the PWM signal is controlled by a feedback signal and a sensed signal. The switching unit has a control terminal receiving the PWM signal, and has a first current terminal and a second current terminal respectively coupled to a first terminal and a second terminal of the first capacitor. The transformer generates an AC driving signal to the lamp according to a signal variation of the primary winding coupled the first current terminal of the first transistor. The first detecting module generates the sensed signal according to the flowing current of the switching unit. | 09-24-2009 |
| 20090231765 | TRANSIENT TO DIGITAL CONVERTERS - A digital converter including a first adjustment unit and a first transient detection unit. The first adjustment unit adjusts amplitude of an electrostatic discharge (ESD) pulse to generate a first adjustment signal when an ESD event occurs in a first power line and a second power line is at a complementary level. The first transient detection unit generates a first digital code according to the first adjustment signal. | 09-17-2009 |
| 20090220151 | Device for adjusting image color difference value and adjusting method thereof - A three-dimensional color difference value adjusting method for adjusting a selected region of an image is provided. The method includes the following steps. First, a plurality of color difference adjusting values corresponding to a plurality of reference brightness values are received. Next, target color difference adjusting value corresponding to brightness value of each pixel within the selected region is estimated according to the color difference adjusting values. Then, color difference value of each pixel within the selected region is adjusted according to target color difference adjusting value of each pixel within the selected region. | 09-03-2009 |
| 20090216940 | Method for accessing a first-in-first-out (FIFO) buffer and a FIFO controller therefor - A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data buffered in the FIFO buffer is more than a threshold. Second, pop the data buffered in the FIFO buffer out to access the memory when the request is granted. If the FIFO buffer is a single-port FIFO buffer, the threshold is set based on the burst length of one burst of data. If the FIFO buffer is a dual-port FIFO buffer, the threshold is set based on the speed at which the data is pushed into the FIFO buffer and the speed at which the data is popped out of the FIFO buffer. | 08-27-2009 |
| 20090213921 | CARRIER RECOVERY SYSTEM AND CARRIER RECOVERY METHOD - The invention provides carrier recovery systems and carrier recovery methods. The carrier recovery system comprises a compensation signal generator, a compensation device and a mode selector. The compensation signal generator generates a compensation signal based on a coherent demodulated signal. In a first mode, the compensate device is couple behind an equalizer; the coherent demodulated signal is generated by the compensation device which compensates the output of the equalizer with the compensation signal. In a second mode, the compensate device is coupled prior to the equalizer, compensating the output of a synchronizer with the compensation signal to generate the input of the equalizer. In the second mode, the compensation signal generator receives the output of the equalizer as the coherent demodulated signal. The mode selector switches the carrier recover system from the first mode to the second mode when an estimated frequency offset satisfies a first criterion. | 08-27-2009 |
| 20090213097 | DISPLAY DRIVER AND BUILT-IN-PHASE-CALIBRATION CIRCUIT THEREOF - A phase-calibration circuit including a pattern generator, a phase adjuster, a rotate register unit, a detector unit, and an optimization unit is disclosed. The pattern generator generates a clock pattern and a data pattern for a target circuit. The phase adjuster adjusts a phase between a first clock and a first data output from the target circuit according to a control data for outputting a second clock and a second data. The rotate register unit provides the control data to the phase adjuster. The detector unit detects phase relationship between the second clock and the second data for outputting a detection result. The optimization unit records the control data output from the rotate register unit in accordance with the detection result, and selects one of the control data as a calibration control data, and controls the rotate register unit to output the calibration control data to the phase adjuster. | 08-27-2009 |
| 20090213033 | TIMING CONTROLLER FOR REDUCING POWER CONSUMPTION AND DISPLAY DEVICE HAVING THE SAME - The invention provides a display device with reduced power consumption, comprising a host applied to generate a first image signal, a timing controller connected to the host, applied to generate a second image signal and comprised a memory for storing image data, and a panel connected to the timing controller and applied to receive the second image signal for displaying image frames. When the display device is in a power-saving mode, the host is powered down, and the timing controller generates the second image signal according to the image data stored in the memory and outputs the second image signal to the panel. | 08-27-2009 |
| 20090212864 | PREAMPLIFIER FOR RECEIVER AND METHOD THEREOF - A preamplifier used in a receiver is provided. The preamplifier comprises an input circuit and an output circuit. The input circuit receives an input differential voltage pair, pulls it down when the common voltage of the input differential voltage pair is higher than a reference voltage. The output circuit receives the input differential voltage pair outputted from the input circuit to pull high or low an output voltage accordingly. | 08-27-2009 |
| 20090208069 | Capacitive Fingerprint Sensor and the Panel Thereof - A capacitive fingerprint sensor comprises a fingerprint capacitor, an integrator, a first transistor, a second transistor and a multiplexer. The fingerprint capacitor has a capacitance that is either a valley capacitance C | 08-20-2009 |
| 20090206929 | OPERATION AMPLIFIER FOR IMPROVING SLEW RATE - An OP amplifier including an input stage and an output stage for improving a slew rate is provided. The input stage receives one of input voltages, and generates an internal voltage according to the received input voltage. The output stage receives and gains the internal voltage, and outputs an output voltage. The output stage includes a first transistor, a plurality of first capacitors and a first switching unit. The first transistor includes a first source/drain terminal coupled to a first voltage, a gate terminal controlled by the internal voltage. The output stage outputs the output voltage according to a voltage at a second source/drain terminal of the first transistor. First terminals of the first capacitors are coupled to the second source/drain terminal of the first transistor. The first switching unit selectively transmits the internal voltage to the second terminal of a corresponding one of the first capacitors. | 08-20-2009 |
| 20090206878 | LEVEL SHIFT CIRCUIT FOR A DRIVING CIRCUIT - Provided is a level shift circuit for a driving circuit. The level shift circuit includes: a cross-coupled transistor pair, for receiving a first input signal and a second input signal and for providing a first output signal and a second output signal; a first transistor, coupled to a first power supply and to the cross-coupled transistor pair, further receiving a first control signal; a second transistor, coupled to the cross-coupled transistor pair and for receiving a second control signal; and a third transistor, coupled to the cross-coupled transistor pair and for receiving the second control signal. The first control signal, the second control signal, the first output signal and the second output signal are all referenced to the first power supply, and the first input signal and the second input signal are referenced to a second power supply lower than the first power supply. | 08-20-2009 |
| 20090206851 | Capacitive Fingerprint Sensor and the Panel Thereof - A capacitive fingerprint sensor comprises a fingerprint capacitor, an integrator, a first transistor, a second transistor and a third transistor. The fingerprint capacitor has a capacitance that is either a valley capacitance C | 08-20-2009 |
| 20090206850 | Capacitive Fingerprint Sensor and the Panel Thereof - A capacitive fingerprint sensor comprises a fingerprint capacitor, a reference capacitor, a first transistor, a second transistor, a comparator and a multiplexer. The fingerprint capacitor has a capacitance that is either a valley capacitance C | 08-20-2009 |
| 20090206849 | CAPACITIVE FINGERPRINT SENSOR AND THE PANEL THEREOF - A capacitive fingerprint sensor comprises a first transistor, a second transistor, a fingerprint capacitor and a third transistor. The fingerprint capacitor has a capacitance that is either a valley capacitance C | 08-20-2009 |
| 20090206848 | CAPACITIVE FINGERPRINT SENSOR AND THE PANEL THEREOF - A capacitive fingerprint sensor comprises a fingerprint capacitor, a reference capacitor, a first transistor and a second transistor. The fingerprint capacitor C | 08-20-2009 |
| 20090201054 | DRIVING CIRCUITS IN ELECTRONIC DEVICE - In driving circuits, signal enhancing circuits are used to enhance driving ability of driving signals. Further, source follower transistors may further enhance driving ability of the driving circuits by conducting more current to loading, so that output signals of the driving circuits may transit more rapidly. In other words, the pull high ability of the driving circuits is enhanced. | 08-13-2009 |
| 20090201053 | LAYOUT STRUCTURE OF SOURCE DRIVER AND METHOD THEREOF - A layout structure of a source driver having a plurality of driving channels, and a method thereof are provided herein. The layout structure of the source driver includes a plurality of pads and a plurality of routings. The pads are used for making electric contact between the source driver and an external circuit. The routings are respectively coupled between the driving channels and the pads for transmitting the signal. Besides, the routings respectively includes a plurality of resistance units, and each of the resistance units is used for adjusting the resistance of the respective routing so as to minimize a variation of the driving ability between the pads. | 08-13-2009 |
| 20090200088 | SENSOR PIXEL AND TOUCH PANEL THEREOF - A sensor pixel and a touch panel using the same are provided herein, wherein the touch panel has m scan lines and n readout lines. The sensor pixel includes a sensing capacitor, a readout transistor, a reset transistor, a base transistor, and a photo transistor. The photo transistor included in the sensor pixel produces a photo leakage current when it is exposed to a light. The light obstruction characteristic of the photo transistor is utilized to detect the locations of the touched sensor pixels. By proper timing control, the present invention not only can be applied to the multi-finger detection, but also is easy to be implemented. | 08-13-2009 |
