HIMAX IMAGING, INC. Patent applications |
Patent application number | Title | Published |
20150206918 | IMAGE SENSOR WITH OBLIQUE PICK UP PLUG AND SEMICONDUCTOR STRUCTURE COMPRISING THE SAME - An image sensor includes a substrate, multiple pixel regions separately disposed in the substrate, and a pickup region including a doping region and a pick up plug obliquely disposed on the doping region and directly contacting the doping region. | 07-23-2015 |
20150163423 | IMAGE SENSOR AND PIXEL ARRARY - A pixel array comprises at least one long exposure pixel, short exposure pixel, and a control circuit. The long exposure pixel comprises a first photodiode to generate charges, a first image signal generating module for generating a first image sensing signal; and a first transfer switch device for passing the charges to the first image signal generating module via a first transfer control signal. The control circuit sets the first transfer control signal to be a first predetermined control voltage when the long exposure pixel is in an long exposure phase, and then sets the first transfer control signal to be a second predetermined control voltage when the short exposure pixel is in a short exposure phase. | 06-11-2015 |
20150162367 | SEMICONDUCTOR STRUCTURE FOR SUPPRESSING HOT CLUSTER AND METHOD OF FORMING SEMICONDUCTOR FOR SUPPRESSING HOT CLUSTER - A semiconductor structure for suppressing a hot cluster is disclosed. An isolation well region which has an extension tip extending toward a substrate is formed in an epitaxial layer disposed on the substrate are of a first conductive type. A first element region and a second element region are disposed in the epitaxial layer to sandwich the isolation well region. The extension tip and the substrate together suppresses a leak current which forms a hot cluster and flows from the first element region via the extension tip to the second element region. | 06-11-2015 |
20150124130 | IMAGE SENSOR - An image sensor includes a passive pixel sensor array and a readout circuit. The passive pixel sensor array has a plurality of pixel columns each having at least one column line. The readout circuit includes a ramp signal generating circuit, a ramp signal line and a comparing circuit. The ramp signal generating circuit is arranged for generating a ramp signal. The ramp signal line is arranged for receiving the ramp signal, wherein the ramp signal line intersects the column line without electrical connection so as to form a parasitic capacitor. The comparing circuit corresponds to the column lines, wherein during the operating cycle of the readout circuit, a pixel sensor of the passive pixel sensor array outputs a charge signal to the column line, and the comparing circuit is arranged for generating an output signal of the pixel sensor according to the ramp signal and the charge signal. | 05-07-2015 |
20150070588 | IMAGING PROCESSING CIRCUIT FOR GENERATING AND STORING UPDATED PIXEL SIGNAL IN STORAGE CAPACITOR BEFORE NEXT OPERATING CYCLE - An imaging processing circuit includes at least a pixel sensor and a processing unit. The pixel sensor includes a photo detector and a storage capacitor. The photo detector is arranged for generating a first pixel signal. The storage capacitor is arranged for storing a second pixel signal. The processing unit is coupled to the pixel sensor, and arranged for generating an updated second pixel signal during a current operating cycle of the imaging processing circuit according to the first pixel signal and the second pixel signal. The updated second pixel signal is stored in the storage capacitor before a next operating cycle of the imaging processing circuit. | 03-12-2015 |
20150070550 | SPATIAL BINNING METHOD FOR RE-SAMPLING BINNED IMAGE, RELATED CIRCUIT, AND COMPUTER READABLE MEDIUM - A spatial binning method for re-sampling a binned image generated by pixel binning includes at least the following steps: receiving a raw image; pixel binning the raw image to generate a binned image; and re-sampling the binned image spatially to generate a re-sampled image according to the values and positions of the pixels of the binned image. A spatial binning circuit, comprising: a binning unit for receiving a raw image to generate a binned image; and a re-sampling unit for receiving the binned image and re-sampling the pixels of the binned image according to the values and positions of the pixels of the binned image. | 03-12-2015 |
20150048466 | IMAGE SENSOR AND FABRICATING METHOD OF IMAGE SENSOR - The present invention provides an image sensor and a fabricating method of the image sensor. The image sensor comprises: a first type epitaxial layer, a photodiode region, a first type well region, a gate region of a source follower transistor, and a first type implant isolation region. The first type well region is formed within the first type epitaxial layer with a first horizontal distance to the photodiode region and a vertical distance to a surface of the first type epitaxial layer. The gate region of a source follower transistor is formed on the surface of the first type epitaxial layer and above the first type well region, and has a second horizontal distance to the photodiode region. There is a distance between the first type implant isolation region and the first type well region as an anti-blooming path. | 02-19-2015 |
20140270572 | SIGNAL PROCESSING APPARATUS AND METHOD FOR DETECTING/CORRECTING ECLIPSE PHENOMENON, AND RELATED CORRELATED DOUBLE SAMPLING APPARATUS - A correlated double sampling apparatus includes a first processing unit and a second processing unit. The first processing unit is arranged for receiving a reset signal, a data signal, and a predetermined signal; obtaining a reset level of the reset signal and a first data level of the data signal in a first operation mode; and obtaining a second data level of the data signal, and comparing the second data level with the predetermined signal to generate a detection result in a second operation mode. The second processing unit is arranged for storing the reset level and the first data level in the first operation mode, and selectively correcting an output signal according to the detection result in the second operation mode, wherein the output signal is determined according to a level difference between the reset level and the first data level. | 09-18-2014 |
20140246713 | SEMICONDUCTOR STRUCTURE, METHOD FOR FORMING THE SAME AND METHOD FOR SUPPRESSING HOT CLUSTER - A semiconductor structure for suppressing hot clusters includes a substrate of a first dopant concentration, an epitaxial layer having a second dopant concentration smaller than the first dopant concentration and directly disposed on the substrate, a dopant gradient region disposed in the epitaxial layer and having a gradient decreasing from the substrate to the epitaxial layer, a shallow trench isolation disposed between a first element region and a second element region, and a shallow trench doping region surrounding the shallow trench isolation and near the dopant gradient region to suppress a hot cluster formed by the first element region to jeopardize the second element region. | 09-04-2014 |
20140124648 | ULTRA LOW READOUT NOISE ARCHITECTURE - A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level. | 05-08-2014 |
20130122636 | METHOD FOR FORMING AN IMAGE SENSING DEVICE - A method for forming an image sensing device is disclosed. An epitaxy layer having the first conductivity type is formed on a substrate, wherein the epitaxy layer comprises a first pixel area corresponding to a first incident light, a second pixel area corresponding to a second incident light, and a third pixel area corresponding to a third incident light. A first deep well is formed in a lower portion of the epitaxy layer for reducing pixel-to-pixel talk of the image sensing device. A second deep well is formed in a lower portion of the epitaxy layer. | 05-16-2013 |
20130049153 | LIGHT PIPE ETCH CONTROL FOR CMOS FABRICATION - In accordance with at least some embodiments of the present disclosure, a process for fabricating a light pipe (LP) is described. The process may be configured to construct a semiconductor structure having an etch-stop layer above a photodiode region and a first dielectric layer above the etch-stop layer. The process may be configured to etch a LP funnel through the first dielectric layer. And the process may be further configured to stop the etching of the LP funnel upon reaching and removing of the etch-stop layer. | 02-28-2013 |
20120307115 | COLOR INTERPOLATION SYSTEM AND METHOD THEREOF - A color interpolation system is disclosed. An enhancement unit receives raw signals from an image sensor, and then processes the raw signals to output an enhanced first signal. A first interpolation unit receives and processes a raw first signal and accordingly outputs an interpolated first signal. A gain generator generates an enhancement gain according to the enhanced first signal and the interpolated first signal. | 12-06-2012 |
20120293697 | Image Sensor and Control Method for Image Sensor - An image sensor including a plurality of first sensing pixels, a plurality of second sensing pixels, and a readout circuit is disclosed. The first sensing pixels are disposed within a sensitive region. The second sensing pixels are disposed within a non-sensitive region. The readout circuit repeatedly reads the output signals of the second sensing pixels to obtain an offset. The readout circuit processes the output signals of the first sensing pixels according to the offset. | 11-22-2012 |
20120231573 | BACK SIDE ILLUMINATION IMAGE SENSOR AND A PROCESS THEREOF - A process and structure of a backside illumination (BSI) image sensor are disclosed. An n-type doped region is formed in a substrate, and a transfer gate is formed on top of the semiconductor substrate. A p-type doped region is formed in the n-type doped region either using the transfer gate as a mask or is non-self aligned formed. | 09-13-2012 |
20120188429 | Sensing Pixel Arrays and Sensing Devices Using the Same - A sensing pixel array is provided and includes a plurality of pixels disposed in an array. Each pixel operates during an exposure period and a readout period and generates a readout signal. Each pixel includes a sensing unit and a sampling unit. The sensing unit senses light to generate a sensing signal during the exposure period. The sampling unit samples the sensing signal to generate a sensing output signal which serves as the readout signal during the readout period. During the exposure period, the sampling unit acts as a memory unit for storing an input signal and outputting an accessed output signal which serves as the readout signal. | 07-26-2012 |
20120182170 | Pipelined Recycling ADC with Shared Operational Amplifier Function - A pipelined recycling analog-to-digital converter (ADC), which converts a first analog input signal into a first digital output signal, including a first conversion stage and a second conversion stage is disclosed. The first conversion stage includes a first processing unit and a second processing unit. The first and the second processing units execute a number of conversion operations. For each conversion operation, an analog value and a digital code are generated by the first or the second processing unit. The first and the second processing units share an operational amplifier, and for each conversion operation. The second conversion stage includes a comparing unit which determines a specific analog value among the analog values generated by the first and the second processing units. When the specific analog value is not located within a predetermined range, the comparing unit generates a reset pulse to reset the operational amplifier. | 07-19-2012 |
20120080766 | Image Sensing Device and Fabrication Thereof - An image sensing device is disclosed, including an epitaxy layer having the a conductivity type, including a first pixel area corresponding to a first incident light, a second pixel area corresponding to a second incident light, and a third pixel area corresponding to a third incident light, wherein the wavelength of the first incident light is longer than that of the second incident light and the wavelength of the second incident light is longer than that of the third incident light. A photodiode is disposed in an upper portion of the epitaxy layer, and a first deep well for reducing pixel-to-pixel talk of the image sensing device is disposed in a lower portion of the epitaxy layer in the second pixel area and the third pixel area, wherein at least a portion of the epitaxy layer in first pixel area does not include the first deep well. | 04-05-2012 |
20120032066 | Sensing Devices and Manufacturing Methods Therefor - A sensing device is provided. The sensing device includes a sensing pixel array and a memory unit. The sensing pixel array is formed in a substrate and includes a plurality of pixels for sensing light. The substrate has a first side and a second side opposite to the first side and receives the light through the first side for sensing the light. The memory unit is formed on the second side of the substrate for memorization. | 02-09-2012 |
20120018831 | LIGHT PIPE FABRICATION WITH IMPROVED SENSITIVITY - In accordance with at least some embodiments of the present disclosure, a process for fabricating a light pipe (LP) is described. The process may be configured to etch a first portion of a LP funnel in a dielectric layer of a semiconductor structure using a web etching process, wherein the dielectric layer is above a photodiode region. The process may also be configured to etch a second portion of the LP funnel in the dielectric layer subsequent to the etching of the first portion of the LP funnel, wherein the second portion of the LP funnel is etched below the first portion of the LP funnel using a dry etching process. | 01-26-2012 |
20110316106 | LIGHT PIPE ETCH CONTROL FOR CMOS FABRICATION - In accordance with at least some embodiments of the present disclosure, a process for fabricating a light pipe (LP) is described. The process may be configured to construct a semiconductor structure having an etch-stop layer above a photodiode region and a first dielectric layer above the etch-stop layer. The process may be configured to etch a LP funnel through the first dielectric layer. And the process may be further configured to stop the etching of the LP funnel upon reaching and removing of the etch-stop layer. | 12-29-2011 |
20110169055 | BACK SIDE ILLUMINATION IMAGE SENSOR AND A PROCESS THEREOF - A process and structure of a back side illumination (BSI) image sensor are disclosed. An n-type doped region is formed in a substrate, and a transfer gate is formed on top of the semiconductor substrate. A p-type doped region is formed in the n-type doped region either using the transfer gate as a mask or is non-self aligned formed. | 07-14-2011 |
20110164146 | Adaptive Frame Rate Control System and Method for an Image Sensor - An adaptive frame rate control system and method for an image sensor includes an amplifier which amplifies a sensor output signal of the image sensor with a gain. An automatic exposure gain (AEG) controller determines a product of exposure time and the gain (EGP) based on incident light intensity, and controls a timing controller and the amplifier, to adjust the exposure time and the gain of the image sensor such that the amplified sensor output signal may approximately approach a sensor target signal, where the change of the exposure time is preferred over the change of the gain. | 07-07-2011 |
20110141291 | MULTI-PHASE BLACK LEVEL CALIBRATION METHOD AND SYSTEM - Multi-phase black level calibration (BLC) methods and systems are generally disclosed. According to one embodiment of the present invention, an image sensor comprises a pixel sensor array, a timing generator, and a front-end processing block. The front-end processing block also includes a first summing junction, a first BLC block, and a second BLC block. According to a first timing signal from the timing generator, the first BLC block is configured to iteratively generate a first calibration signal in a first phase based on a first set of adjusted black level signals associated with a first set of black pixels, a changing accumulator step, and a predetermined condition associated with a first target black level. According to a second timing signal from the timing generator, the second BLC block is configured to generate a second calibration signal for a second summing junction to apply to an image signal associated with one or more active pixels in the frame in a second phase. | 06-16-2011 |
20110090238 | BLACK LEVEL CALIBRATION METHOD AND SYSTEM - Black level calibration methods and systems are generally disclosed. According to one embodiment of the present invention, a method of calibrating a black level signal in a frame includes performing an iteration of averaging a first set of digital values corresponding to a first set of adjusted black level signals associated with a first set of black pixels of the frame, determining whether an average value based on the first set of digital values has reached a target black level, determining a calibration offset based on a difference between the average value and the target black level and an accumulator step, converting the calibration offset to an analog signal, generating a calibration signal based on the analog signal for a second set of black pixels of the frame, and repeating the iteration for the frame until a predetermined condition is determined to have been met. | 04-21-2011 |
20110058073 | Signal Chain of an Imaging System - A signal chain of an imaging system is disclosed. The system includes three circuit stages. The first circuit stage includes a programmable gain amplifier (PGA) and a black level compensation (BLC) circuit that form a BLC loop. The second circuit stage includes an analog-to-digital converter (ADC), where a dark signal offset is added at an input of the ADC. The third circuit stage includes a digital gain circuit and a digital loop that makes a final output of the imaging system settle on a target level in the BLC mode. | 03-10-2011 |
20110032391 | Image Sensor with Peripheral Dummy Pixels - An image sensor with an active pixel array and peripheral dummy pixels is disclosed. The dummy pixels are located between (a) at least a portion of the active pixel array and (b) undesired or potentially interfering noise from a noise source. Outputs of the dummy pixels are coupled to float with respect to the active pixel array, thereby blocking the noise from being coupled into the active pixel array. | 02-10-2011 |
20110019913 | System and Method of Generating Color Correction Matrix for an Image Sensor - A system and method of generating a color correction matrix (CCM) for an image sensor are disclosed. Quantum efficiency (QE) spectra of pixels of the image sensor illuminated by a physical light source are measured. Subsequently, color values of the image sensor and color values in a predetermined color space are determined according to the QE spectra and predetermined reference data essential for deriving the color values. Finally, the CCM for the image sensor is generated by applying a fitting algorithm on the color values of the image sensor and the color values in the predetermined color space. | 01-27-2011 |
20090295965 | METHOD AND CIRCUIT FOR DRIVING ACTIVE PIXELS IN A CMOS IMAGER DEVICE - One embodiment of the present invention describes a pixel circuit that comprises at least one photodiode, a first transistor coupled between the photodiode and a floating diffusion node, a second transistor coupled between the floating diffusion node and a modifiable driving voltage signal, and a third transistor having a gate coupled to the floating diffusion node, a source coupled to a signal output, and a drain coupled to a constant voltage. Another embodiment of the present invention provides a method for driving the pixel circuit, which comprises resetting the photodiode and the floating diffusion node, exposing the photodiode to light to accumulate charges, selecting the pixel circuit by switching the driving voltage signal from a first voltage level to a second voltage level, retrieving a reference voltage from the selected pixel circuit, and retrieving an image signal from the selected pixel circuit corresponding to the accumulated charges. | 12-03-2009 |