| HEJIAN TECHNOLOGY (SUZHOU) CO., LTD. Patent applications |
| Patent application number | Title | Published |
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| 20100055912 | SEMICONDUCTOR FABRICATING PROCESS - A semiconductor fabricating process is provided. First, a substrate is provided. The substrate has thereon a stacked structure and a mask layer disposed on the stacked structure. Thereafter, an oxide layer is formed on a surface of the mask layer and a surface of at least a portion of the stacked structure. Afterwards, a first spacer is formed on a sidewall of the stacked structure. Then, a second spacer is formed on a sidewall of the first spacer. Further, a first etching process is performed to remove the oxide layer on the surface of the mask layer. Thereafter, a second etching process is performed to simultaneously remove the mask layer and the second spacer. | 03-04-2010 |
| 20090326697 | SEMICONDUCTOR MANUFACTURING AUTOMATION SYSTEM AND METHOD FOR USING THE SAME - A semiconductor manufacturing automation system for automatically manufacturing a plurality of semiconductor products by using a plurality of tools is provided. The system comprises a database, a receiver module, a data retriever and a data loading module. The database stores a plurality of manufacturing recipes with respect to the semiconductor products respectively. Each of the manufacturing recipes records at least one of the tools for manufacturing the corresponding semiconductor product and a plurality of parameters for controlling each of the tools for manufacturing the corresponding semiconductor product. The receiver module is used for receiving a request for manufacturing one of the semiconductor products. The data retriever is used for retrieving one of the recipes from the database according to the request. The data loading module is used for automatically loading the retrieved recipe to the corresponding tools. | 12-31-2009 |
| 20090068786 | FABRICATING METHOD OF IMAGE SENSOR - A method for fabricating an image sensor includes following steps. First, a substrate having semiconductor devices formed thereon is provided. Interlayer insulating films and Interlayer conductive films are formed on the substrate alternately, wherein the interlayer conductive films are electrically connected to the semiconductor devices. Next, isolated photo-diodes are formed on a topmost layer of the interlayer conductive films, wherein one electrode of the isolated photo-diodes is electrically connected to a topmost layer of the interlayer conductive films. A top insulating layer is formed on the topmost layer of the interlayer conductive films, wherein the isolated photo-diodes are covered by the top insulating layer. A top conductive layer is formed in the top insulating layer, wherein the top conductive layer is electrically connected to another electrode of the isolated photo-diodes. | 03-12-2009 |
| 20090059451 | ESD PROTECTION CIRCUIT WITH IMPROVED COUPLING CAPACITOR - In an ESD protection circuit, a MOS transistor and a coupling capacitor are formed over the same substrate. The coupling capacitor may be a MIM capacitor or a PIP capacitor. In case of MIM capacitor, the first metal layer and the second metal layer thereof are electrically coupled to the gate region and the source/drain region of the MOS transistor, respectively. In case of PIP capacitor, the gate region of the MOS transistor, an insulation layer and the second poly layer thereof define the PIP capacitor. The second poly layer of the PIP capacitor is electrically coupled to the source/drain region of the MOS transistor. | 03-05-2009 |
