GloNav Limited Patent applications |
Patent application number | Title | Published |
20090243754 | INTEGRATED CIRCUIT - In an integrated circuit having a number of circuit units on a single semiconductor chip, particularly in a system-on-chip integrated circuit including an integrated transceiver, interference between the circuit units is suppressed using on-chip resonant elements. Each resonant element has at least one on-chip capacitor and at least one on-chip conductive line constituting an inductance. The capacitance-inductance combinations are arranged to be resonant at one or more frequencies at which radio frequency energy is generated by the circuit units. The capacitive part of each series resonant combination is formed as a plurality of capacitor elements forming in an array to minimise self-inductance. Also disclosed is a filtering arrangement in which each circuit unit is individually supplied from the tap of a series resistive-capacitance combination to provide low-pass filtering. The resistance of such a combination may be configured as an FET to allow the circuit unit to be individually powered down to a low leakage state. | 10-01-2009 |
20090237153 | HIGH ORDER CONTINUOUS TIME FILTER - There is described a continuous time filter of at least a second (or higher) order, comprising one or more first order filter stages of a first type, the or each first order filter stage of the first type comprising a reactive component and an impedance dependent on the difference between the input and output voltages of the filter stage. The filter includes at least one first order filter stage of a second type, the or each second order filter of the second type comprising a reactive component and an impedance dependent on the sum of the input and output voltages of the filter stage. The filter includes a transfer function of the continuous time filter that is obtained comprising complex poles. | 09-24-2009 |
20090140435 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF PROTOTYPING A SEMICONDUCTOR CHIP - In a semiconductor integrated circuit device comprising a semiconductor chip having a number of conductor layers and a number of via layers between the conductor layers, a routing matrix is provided in a small area of the chip to act as a revision number register. The routing matrix includes a matrix block having, in each metal layer of the chip, conductor tracks, the tracks in each metal layer running in a respective direction different from the direction of the tracks in the adjacent metal layers so that the tracks of each consecutive pair of metal layers cross over each other. In each via layer between consecutive metal layers, the matrix block includes selectively placed vias interconnecting the tracks in the adjacent metal layers on each side of the respective via layer. The tracks in each metal layer comprise source tracks and output tracks, the source tracks being coupled respectively to logic level sources of opposite polarity and the output tracks providing register outputs which carry a high or low logic level depending on their individual connections in the routing matrix block to the supply lines. The arrangement is such that when a change in the primary circuits of the chip is required, a new revision number output can be generated by altering the interconnections of the conductor tracks of the routing matrix only in the respective metal layer or via layer which has been changed in the primary circuits. | 06-04-2009 |