| GLOBALFOUNDRIES SINGAPORE PTE. LTD. Patent applications |
| Patent application number | Title | Published |
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| 20120119281 | INTEGRATED CIRCUIT SYSTEM WITH BANDGAP MATERIAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess. | 05-17-2012 |
| 20120112256 | Control gate structure and method of forming a control gate structure - Semiconductor devices and methods of fabricating the devices are provided. An example device may include a substrate and a gate structure on the substrate. The gate structure includes a control gate having at least three distinct gate regions. First and second control gate regions are configured as a first field type, such as a high-gate or low-gate type. A third control gate region configured as a second field type (different from the first field type) is at least partially disposed between the first and second control gate regions. | 05-10-2012 |
| 20120100716 | Method to improve reliability (EM and TDDB) with post silylation plasma treatment process for copper damascene structures - A method for semiconductor fabrication includes etching a via and a trench in a dielectric material to yield an etched surface. The dielectric material may have an ultra-low K value (e.g., a K-value of less than or equal to 2.4). The etched surface is then processed with a gas-phase silylation process to yield a silylated surface. The silylated surface is processed with a plasma treatment process to yield a plasma treated surface. The plasma treated surface, in turn, is processed with a dilute hydrofluoric acid before a conductive metal is deposited in the via and the trench. Inclusion of the plasma treatment process reduces hollow metal defects caused by the silylation process and increases reliability of metal interconnects and improves barrier metallization. | 04-26-2012 |
| 20120098041 | SELF-ALIGNED BODY FULLY ISOLATED DEVICE - A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs. | 04-26-2012 |
| 20120086468 | Method and system for introducing physical damage into an integrated circuit device for verifying testing program and its results - According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy. | 04-12-2012 |
| 20120074537 | DIELECTRIC STACK - A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness T | 03-29-2012 |
| 20120074483 | EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor. | 03-29-2012 |
| 20120074482 | EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor. | 03-29-2012 |
| 20120070971 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING - There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions. | 03-22-2012 |
| 20120043659 | INTERCONNECTS WITH IMPROVED TDDB - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material. | 02-23-2012 |
| 20120034745 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION DIFFUSION - A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling. | 02-09-2012 |
| 20120012940 | INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF - A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width. | 01-19-2012 |
| 20120009749 | METHOD FOR FABRICATING NANO DEVICES - Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire. | 01-12-2012 |
| 20120007214 | INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor. | 01-12-2012 |
| 20120007185 | Novel method to tune narrow width effect with raised S/D structure - A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width. | 01-12-2012 |
| 20120007180 | FinFET with novel body contact for multiple Vt applications - FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications. | 01-12-2012 |
| 20120005633 | CONSISTENCY CHECK IN DEVICE DESIGN AND MANUFACTURING - A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an original artwork file format. A modified artwork file corresponding to the original artwork file is provided in a first modified artwork file format. The modified artwork file contains back end information. The method also includes checking to ensure that the original and modified artwork files are consistent. | 01-05-2012 |
| 20120001228 | METHOD TO CONTROL SOURCE/DRAIN STRESSOR PROFILES FOR STRESS ENGINEERING - An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile. | 01-05-2012 |
| 20110316166 | INTEGRATED CIRCUIT SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer. | 12-29-2011 |
| 20110316085 | INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABLE STRESS - An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O | 12-29-2011 |
| 20110266688 | PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device. | 11-03-2011 |
| 20110266628 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 11-03-2011 |
| 20110237072 | INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer. | 09-29-2011 |
| 20110223737 | IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS - Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing. | 09-15-2011 |
| 20110163357 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING - A method for fabricating a semiconductor device is presented. The method comprises providing a gate stack including a gate dielectric and gate electrode over a substrate. Stressor regions comprising stressor material incorporated into substitutional sites of the substrate are formed within the substrate on opposed sides of the gate stack. A first stressor layer having a first stress value is formed over the semiconductor device after forming the stressor regions followed by an anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the anneal is conducted at a low temperature. | 07-07-2011 |
| 20110079850 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE - A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure. | 04-07-2011 |
| 20110042743 | LDMOS Using A Combination of Enhanced Dielectric Stress Layer and Dummy Gates - First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region | 02-24-2011 |
| 20100314774 | RELIABLE INTERCONNECTS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography. | 12-16-2010 |
| 20100314763 | INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process. | 12-16-2010 |
| 20100308374 | STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD - A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate. | 12-09-2010 |
| 20100301424 | NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE - A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, R | 12-02-2010 |
| 20100267236 | METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS - A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts. | 10-21-2010 |
| 20100258910 | LATERAL JUNCTION VARACTOR WITH LARGE TUNING RANGE - Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (C | 10-14-2010 |
| 20100230777 | SELECTIVE STI STRESS RELAXATION THROUGH ION IMPLANTATION - A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed. | 09-16-2010 |
| 20100219485 | FORMATION OF RAISED SOURCE/DRAIN STUCTURES IN NFET WITH EMBEDDED SIGE IN PFET - A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains. | 09-02-2010 |
