GLOBALFOUNDRIES SINGAPORE PTE. LTD. Patent applications |
Patent application number | Title | Published |
20150349095 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH NONVOLATILE MEMORY DEVICES - Methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming a stack gate structure overlying a semiconductor substrate. The method forms a select gate material overlying the stack gate structure and the semiconductor substrate and having a planar surface overlying the stack gate structure. The method includes anisotropically etching the select gate material to define a select gate adjacent the stack gate structure, wherein the select gate is formed with a planar upper surface. | 12-03-2015 |
20150346746 | BANDGAP REFERENCE VOLTAGE GENERATOR CIRCUITS - Bandgap reference voltage generator circuits are provided that include an operational amplifier, a current mirror configured to be coupled to a supply voltage, a first branch coupled to the current mirror, a second branch coupled to the first branch, a third branch coupled to the second branch and a fourth branch. The operational amplifier includes a first input configured to receive a first voltage and a second input configured to receive a second voltage, and an output that is configured to generate an output voltage. The current mirror is configured to generate a third voltage and a first current. The first branch is configured to receive a second current that is a first portion of the first current, the second branch is configured to receive a third current that is a second portion of the first current, the third branch is configured to receive a fourth current that is a third portion of the first current, and the fourth branch is configured to receive a fifth current generated by the current mirror. The fifth current is used to generate a bandgap reference voltage. | 12-03-2015 |
20150340428 | INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING THE SAME - Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure. | 11-26-2015 |
20150333103 | VERTICAL RANDOM ACCESS MEMORY WITH SELECTORS - Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure. The selector element includes respective first and second selector diodes for the first and second memory elements of each of the one or more cell stacks. | 11-19-2015 |
20150333068 | THYRISTOR RANDOM ACCESS MEMORY - Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate. | 11-19-2015 |
20150311251 | INTEGRATED CIRCUITS WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME - A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack. | 10-29-2015 |
20150311221 | INTEGRATED CIRCUITS HAVING NICKEL SILICIDE CONTACTS AND METHODS FOR FABRICATING THE SAME - Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material. | 10-29-2015 |
20150310930 | EQUIVALENT FUSE CIRCUIT FOR A ONE-TIME PROGRAMMABLE READ-ONLY MEMORY ARRAY - Technologies are provided for measuring a programming current (PC) for a memory cell (MC) of a one-time programmable read-only memory array. The MC includes a fuse equivalent circuit (FEC) that includes a first current path (CP) having a first node, a second CP having a fuse of the memory cell and a second node, and a third CP. The PC is split into a first current, a second current and a third current that flow over the first CP, the second CP, and the third CP, respectively. A first voltage applied along the first path is divided to generate a second voltage at the first node, and an output voltage generated by an operational amplifier controls the second current to maintain a third voltage at the second node at substantially the same value as the second voltage so that the second current has a sufficiently low value and does not burn the fuse. | 10-29-2015 |
20150303117 | METHODS FOR FABRICATING INTEGRATED CIRCUTIS AND COMPONENTS THEREOF - Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for a fabricating a semiconductor device is provided. The method includes providing a partially fabricated semiconductor device and forming silicide regions outside of the first and second gates. The partially fabricated semiconductor device includes a semiconductor substrate, a first gate formed over the semiconductor substrate, and a second gate formed over the semiconductor substrate and spaced apart from the first gate. Silicide formation between the first gate and the second gate is inhibited. | 10-22-2015 |
20150303068 | CMP WAFER EDGE CONTROL OF DIELECTRIC - Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer. | 10-22-2015 |
20150294909 | SILICON-ON-INSULATOR INTEGRATED CIRCUIT DEVICES WITH BODY CONTACT STRUCTURES AND METHODS FOR FABRICATING THE SAME - Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact region of the semiconductor layer. The body contact region comprises a portion of the semiconductor layer between at least one of the plurality of first STI structures and at least one of the plurality of second STI structures. | 10-15-2015 |
20150294858 | METHODS FOR EXTREME ULTRAVIOLET MASK DEFECT MITIGATION BY MULTI-PATTERNING - Methods for extreme ultraviolet (EUV) mask defect mitigation by using multi-patterning lithography techniques. In one exemplary embodiment, a method for fabricating an integrated circuit including identifying a position of a defect in a first EUV photolithographic mask, the photolithographic mask including a desired pattern and transferring the desired pattern to a photoresist material disposed on a semiconductor substrate. Transferring the desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first EUV photolithographic mask. The method further includes, using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes the error pattern feature from the photoresist material. | 10-15-2015 |
20150279743 | ISOLATION FOR EMBEDDED DEVICES - Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric. | 10-01-2015 |
20150262885 | INTEGRATED CIRCUITS WITH STRESSED SEMICONDUCTOR-ON-INSULATOR (SOI) BODY CONTACTS AND METHODS FOR FABRICATING THE SAME - Integrated circuits with selectively stressed semiconductor-on-insulator (SOI) body contacts and methods for fabricating integrated circuits with selectively stressed SOI body contacts are provided. An exemplary method for fabricating an integrated circuit includes forming a channel region and a body contact overlying and/or in an SOI substrate. Further, the method includes selectively applying a first stress to the source/drain region in a longitudinal direction. Also, the method includes selectively applying a second stress to the body contact in a lateral direction perpendicular to the longitudinal direction. | 09-17-2015 |
20150228739 | SPLIT GATE EMBEDDED MEMORY TECHNOLOGY AND MANUFACTURING METHOD THEREOF - A device and method of forming the device using a split gate embedded memory technology are presented. The device includes two polysilicon layers, one for floating gate poly and the other for logic, HV and stack gate and split gate. An oxide-nitride-oxide process of the manufacturing method results in low reliability risk and good uniformity in the device. Moreover, embodiments of the manufacturing method have good controllability of the profile and critical dimension of select gates in production. Furthermore, there is no need to provide non-volatile memory and high-voltage protection for devices manufactured by embodiments of the manufacturing method of the present disclosure. | 08-13-2015 |
20150221761 | DEVICE WITH ISOLATION BUFFER - Devices and methods for forming a device are presented. A substrate prepared with a device region is provided. A fin is formed in the device region. The fin includes top and bottom portions. An amorphous isolation buffer is formed at least in the bottom fin portion, leaving the top fin portion crystalline. The top fin portion serves as a body of a fin type transistor. | 08-06-2015 |
20150221652 | 1T SRAM/DRAM - One-transistor volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation well disposed below the top substrate surface. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The isolation well isolates the body region from the substrate. The device includes a band engineered (BE) floating body disposed over the isolation well and within the body region. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate. | 08-06-2015 |
20150221651 | 1T SRAM/DRAM - One-transistor (1T) volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation buffer layer disposed below the top substrate surface. The isolation buffer layer is an amorphized portion of the substrate. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate. | 08-06-2015 |
20150187863 | INTEGRATED CIRCUITS INCLUDING A RESISTANCE ELEMENT AND GATE-LAST TECHNIQUES FOR FORMING THE INTEGRATED CIRCUITS - Integrated circuits with a resistance element and gate-last techniques for forming the integrated circuits are provided. An exemplary technique includes providing a semiconductor substrate that includes a shallow trench isolation (STI) structure disposed therein. A dummy gate electrode structure is patterned overlying semiconductor material of the semiconductor substrate, and a resistor structure is patterned overlying the STI structure. The dummy gate electrode structure and the resistor structure include a dummy layer overlying a metal capping layer. A gate dielectric layer underlies the metal capping layer. An interlayer dielectric layer is formed overlying the semiconductor substrate and the STI structure. End terminal recesses for the resistance element are concurrently patterned through the dummy layer of the resistor structure along with removing the dummy layer of the dummy gate electrode structure to form a gate electrode recess. Metal gate material is deposited in the end terminal recesses and a gate electrode recess. | 07-02-2015 |
20150187787 | MULTI-LEVEL MEMORY CELLS AND METHODS FOR FORMING MULTI-LEVEL MEMORY CELLS - Integrated circuits with multi-level memory cells and methods for producing the same are provided. A method for producing an integrated circuit with a multi-level memory cell includes forming a gate insulator overlying a substrate. A select gate is formed overlying the gate insulator such that one multi-level memory cell includes one select gate. A thin film storage layer with nanocrystals is formed overlying the select gate and the substrate, and a left and right control gate are formed on opposite sides of the select gate such that the thin film storage layer is between the substrate and each of the control gates. A left implant and a right implant are formed in the substrate such that the select gate, the left control gate, and the right control gate are positioned between the left and right implants. | 07-02-2015 |
20150187784 | THREE-DIMENSIONAL NON-VOLATILE MEMORY - A three-dimensional one-transistor non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a primary fin disposed on a substrate along a first direction, first and second secondary fins disposed on the substrate along a second direction, and a first gate of a first memory cell disposed on the substrate in a gate region thereof. The first gate includes a program gate, a floating gate and a control gate. | 07-02-2015 |
20150187714 | INTEGRATED CIRCUITS INCLUDING COPPER PILLAR STRUCTURES AND METHODS FOR FABRICATING THE SAME - Integrated circuits including copper pillar structures and methods for fabricating the same are disclosed. In one exemplary embodiment, an integrated circuit includes a last metal layer and a passivation layer disposed over the last metal layer, both the last metal and passivation layers being disposed over an integrated circuit active device on a semiconductor substrate. The integrated circuit further includes a copper pillar structure disposed partially within a first portion of the passivation layer and immediately over the last metal layer. The first portion of the passivation layer is defined by first and second sidewalls of the passivation layer and an upper surface of the last metal layer. The copper pillar structure includes a liner formed along the first and second sidewalls and over the upper surface of the last metal and a copper material within the liner. The copper pillar structure, including both the liner and the copper material within the liner, further extends to a height above an upper surface of the passivation layer. | 07-02-2015 |
20150187700 | RELIABLE INTERCONNECTS - Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M | 07-02-2015 |
20150187647 | THROUGH VIA CONTACTS WITH INSULATED SUBSTRATE - Device and a method of forming a device are disclosed. The method includes providing a crystalline-on-insulator (COI) substrate. The COI substrate includes at least a base substrate over a buried insulator layer. Through via (TV) contacts are formed within the substrate. The TV contact extends from a top surface of the base substrate to within the buried insulator layer. Upper interconnect levels are formed over the top surface of the base substrate. A lower redistribution (RDL) is formed over a bottom surface of the base substrate. The buried insulator layer corresponds to a first RDL dielectric layer of the lower RDL and protects the sidewalls of the TV contacts. | 07-02-2015 |
20150187641 | INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS FOR FABRICATING SAME - Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate. | 07-02-2015 |
20150186577 | SYSTEM AND METHODS FOR OPC MODEL ACCURACY MANAGEMENT AND DISPOSITION - System and methods for OPC model accuracy and disposition using quad matrix are presented. A method includes obtaining wafer data from a calibration test pattern. The method also classifies the wafer data into four quadrants of a quad matrix. The method further utilizes at least one of the four quadrants to quantify OPC model accuracy. | 07-02-2015 |
20150179734 | INTEGRATED CIRCUITS WITH A BURIED N LAYER AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS - Integrated circuits with a buried N layer and methods for fabricating such integrated circuits are provided. The method includes forming a buried N layer overlying a substrate, and forming a monocrystalline layer overlying the buried N layer. After forming the monocrystalline layer, a well tap trench is formed, where the well tap trench penetrates the electronics area and the buried N layer and extends into the substrate. A well tap is formed in the well tap trench. | 06-25-2015 |
20150179543 | THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES PROVIDING THERMOELECTRIC COOLING AND METHODS FOR COOLING SUCH INTEGRATED CIRCUIT STRUCTURES - Three-dimensional integrated circuit structures providing thermoelectric cooling and methods for cooling such integrated circuit structures are disclosed. In one exemplary embodiment, a three-dimensional integrated circuit structure includes a plurality of integrated circuit chips stacked one on top of another to form a three-dimensional chip stack, a thermoelectric cooling daisy chain comprising a plurality of vias electrically connected in series with one another formed surrounding the three-dimensional chip stack, a thermoelectric cooling plate electrically connected in series with the thermoelectric cooling daisy chain, and a heat sink physically connected with the thermoelectric cooling plate. | 06-25-2015 |
20150179535 | SEMICONDUCTOR WAFERS EMPLOYING A FIXED-COORDINATE METROLOGY SCHEME AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING THE SAME - Semiconductor wafers employing a fixed coordinate metrology scheme and methods for fabricating integrated circuits using the same are disclosed. In an exemplary embodiment, a semiconductor wafer employing a fixed-coordinate metrology scheme includes an external scribe region in the form of a first rectangular ring, the first rectangular ring defining a first interior space inward from the external scribe region and an interior scribe region in the form of a second rectangular ring, disposed within the first interior space and immediately adjacent to the external scribe region at all points along its exterior perimeter, the second rectangular ring defining a second interior space inward from the interior scribe region, the second interior space being wholly within the first interior space. The semiconductor wafer further includes a technology-specific tile region disposed within the second interior space and immediately adjacent to the interior scribe region and an electrical testable scribe line measurement (ETSLM) region disposed within the second interior space and immediately adjacent to both the technology-specific tile region and the interior scribe region. Still further, the semiconductor wafer includes a free floorplan area disposed within the second interior space and immediately adjacent to both the ETSLM region and the interior scribe region. | 06-25-2015 |
20150177319 | INTEGRATED CIRCUITS WITH COPPER HILLOCK-DETECTING STRUCTURES AND METHODS FOR DETECTING COPPER HILLOCKS USING THE SAME - Integrated circuits with copper hillock-detecting structures and methods for detecting copper hillocks using the same are disclosed. In an exemplary embodiment, an integrated circuit includes a copper hillock-detecting structure. The copper hillock-detecting structure includes a copper metallization layer and an intermediate plate structure adjacent to the copper metallization layer. The intermediate plate structure includes a conducting material plate. The intermediate plate structure further includes a plurality of vias electrically and physically connected with the conducting material plate. The copper hillock-detecting structure further includes a sensing plate adjacent to the intermediate plate and electrically and physically connected with the plurality of vias. | 06-25-2015 |
20150162436 | FINFET WITH ISOLATION - Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a device region. A fin is formed in the device region. The fin includes top and bottom portions. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed. At least one isolation buffer is formed in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor. Source/drain (S/D) regions are formed in the top portions of the fin and a gate wrapping around the fin is provided. | 06-11-2015 |
20150147872 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL POLISHING - Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process. | 05-28-2015 |
20150145060 | LOW RESISTANCE CONTACTS WITHOUT SHORTING - Devices and methods of forming a device are disclosed. A substrate prepared with at least a first transistor and a second transistor is provided. Each of the first and second transistors includes a gate disposed on the substrate between first and second contact regions in the substrate. A silicide block layer is formed on the substrate and is patterned to expose portions of the first and second contact regions. Silicide contacts are formed in the exposed first and second contact regions. The silicide contacts are displaced from sides of the gates of the first and second transistors. A contact dielectric layer is formed and contacts are formed in the contact dielectric layer. The contacts are in communication with the silicide contacts in the contact regions. | 05-28-2015 |
20150140688 | SETUP FOR MULTIPLE CROSS-SECTION SAMPLE PREPARATION - A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The multiple-sample-holder polishing setup includes a frame. The frame has a hollow center, one or more long and short rods and a recess for accommodating a polishing head. The setup includes one or more sample holders. The sample holder is to be attached to the one or more long and short rods of the frame. A paddle is affixed to each sample holder. A sample is attached to the paddle. The sample is coated with a thin epoxy layer prior to polishing thereby allowing for easy inspection for site of interests as well as quick material removal. | 05-21-2015 |
20150137060 | HIGH RECTIFYING RATIO DIODE - Devices and methods for forming a device are disclosed. The device includes a substrate and a selector diode disposed over the substrate. The diode includes first and second terminals. The first terminal is disposed between the second terminal and the substrate. The diode includes a Schottky Barrier (SB) disposed at about an interface of the first and second terminals. The SB includes a tunable SB height defined by a SB region having segregated dopants. The device includes a memory element disposed over and coupled to the selector diode. | 05-21-2015 |
20150129975 | MULTI-TIME PROGRAMMABLE DEVICE - Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region. | 05-14-2015 |
20150111469 | CMP HEAD STRUCTURE - A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing. | 04-23-2015 |
20150111467 | CMP HEAD STRUCTURE - A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out. | 04-23-2015 |
20150108654 | RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES - Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack. | 04-23-2015 |
20150108432 | HIGH ION AND LOW SUB-THRESHOLD SWING TUNNELING TRANSISTOR - Devices and manufacturing methods thereof are presented. The device includes a substrate and a fin-type transistor disposed on the substrate. The transistor includes a fin structure that protrudes from the substrate to serve as a source of the transistor. The fin structure is doped with dopants of a first polarity. The transistor also includes a gate layer formed over and around a first end of the fin structure to serve as a gate of the transistor. A drain layer is disposed over the fin structure and adjacent to the gate layer to serve as a drain of the transistor. The drain layer is doped with dopants of a second polarity opposite the first polarity. | 04-23-2015 |
20150097256 | SEMICONDUCTOR DEVICES INCLUDING AVALANCHE PHOTODETECTOR DIODES INTEGRATED ON WAVEGUIDES AND METHODS FOR FABRICATING THE SAME - Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a trench into a waveguide layer in a detector region of a semiconductor substrate. An avalanche photodetector diode is formed about the trench. Forming the avalanche photodetector diode includes forming a multiplication region in the waveguide layer laterally adjacent to the trench. An absorption region is formed at least partially disposed in the trench. | 04-09-2015 |
20150087133 | WAFER PROCESSING - Methods for forming a device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layers of the top and bottom pad stacks include an initial thickness T | 03-26-2015 |
20150087132 | WAFER PROCESSING - Semiconductor device and method for forming a semiconductor device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layer of the bottom pad stack is removed by a batch process. Trench isolation regions are formed in the substrate. | 03-26-2015 |
20150076669 | RELIABLE CONTACTS - Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component. | 03-19-2015 |
20150069522 | EFFICIENT INTEGRATION OF CMOS WITH POLY RESISTOR - Device and methods for forming a device are presented. The method includes providing a substrate. The substrate includes a resistor region defined by a resistor isolation region. A resistor gate is formed on the resistor isolation region. An implant mask with an opening exposing the resistor region is formed. Resistor well dopants are implanted to form a resistor well in the substrate. The resistor well is disposed in the substrate below the resistor isolation region. Resistor dopants are implanted into the resistor gate to define the sheet resistance of the resistor gate. Terminal dopants are implanted to form first and second resistor terminals at sides of the resistor gate. A central portion of the resistor gate sandwiched by the resistor terminals serves as a resistive portion. | 03-12-2015 |
20150028490 | INTEGRATED CIRCUITS HAVING DEVICE CONTACTS AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact. | 01-29-2015 |
20140346603 | TRANSISTOR DEVICES HAVING AN ANTI-FUSE CONFIGURATION AND METHODS OF FORMING THE SAME - Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer. | 11-27-2014 |
20140332887 | SILICON-ON-INSULATOR INTEGRATED CIRCUITS WITH LOCAL OXIDATION OF SILICON AND METHODS FOR FABRICATING THE SAME - Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same are provided. An integrated circuit includes a semiconductor substrate and a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor that includes source and drain regions located in the semiconductor substrate, a gate dielectric layer located between the source and drain regions, and a local oxide layer located in a second portion of the semiconductor substrate and extending a second depth below the upper surface of the semiconductor substrate. The first depth is greater than the second depth. Still further, the integrated circuit includes a first gate electrode that extends over the gate dielectric layer and the local oxide layer. | 11-13-2014 |
20140320174 | INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES - Integrated circuits with improved LDMOS structures are provided. An integrated circuit includes a semiconductor substrate, a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor structure. The transistor structure includes a gate dielectric positioned over a portion of a first one of the plurality of STI regions, a drain region adjacent to the first one of the plurality of STI regions and spaced apart from the gate dielectric, a first gate electrode that extends over a first portion of the gate dielectric, a second gate electrode that extends over a second portion of the gate dielectric and positioned adjacent to the first gate electrode, and a source region positioned adjacent to the first portion of the gate dielectric. | 10-30-2014 |
20140282300 | TOPOGRAPHY DRIVEN OPC AND LITHOGRAPHY FLOW - Enhancements in lithography for forming an integrated circuit are disclosed. The enhancements include a topography analysis of a design data file to obtain accumulative topography information for different mask levels. The topography information facilitates topography driven optical proximity correction and topography driven lithography. | 09-18-2014 |
20140282299 | METHOD AND APPARATUS FOR PERFORMING OPTICAL PROXIMITY AND PHOTOMASK CORRECTION - An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask. | 09-18-2014 |
20140282292 | SURFACE TOPOGRAPHY ENHANCED PATTERN (STEP) MATCHING - A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the design data file includes analyzing the design data file and patterns in the design data file are enhanced taken into consideration topography information of design layers corresponding to masks of the IC. | 09-18-2014 |
20140282286 | ETCH FAILURE PREDICTION BASED ON WAFER RESIST TOP LOSS - An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features. | 09-18-2014 |
20140268990 | STACKABLE NON-VOLATILE MEMORY - A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications. | 09-18-2014 |
20140268989 | RESISTIVE NON-VOLATILE MEMORY - A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the secondary selector selects a bit within the multi-bit cell. A plurality of storage units can be commonly coupled to a primary selector, facilitating high density applications. | 09-18-2014 |
20140268090 | CROSS TECHNOLOGY RETICLE (CTR) OR MULTI-LAYER RETICLE (MLR) CDU, REGISTRATION, AND OVERLAY TECHNIQUES - Methods for reducing reticle transmission differences and for optimizing layer placement for overlay in MTRs and CTRs are disclosed. Embodiments include providing a reticle having a prime area and a frame area surrounding the prime area; determining RT differences across the prime area; and providing RT adjustment structures on the reticle to decrease the RT differences. Other embodiments include grouping multiple layers of a semiconductor production flow, the layers for each group having an RT difference less than a predetermined value; and placing the layers on plural ordered reticles of a reticle set, each reticle having multiple image fields, by selecting, for each reticle, layers from a single group and optimizing placement of the layers for overlay. Other embodiments include selectively rotating image fields on a reticle having multiple image fields to improve overlay, or optimizing placement of DDLs on CTRs by placing each design orientation on a different reticle. | 09-18-2014 |
20140264911 | THROUGH SILICON VIAS - A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface. | 09-18-2014 |
20140264584 | LATERAL DOUBLE-DIFFUSED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate with a device region. The method also includes forming a transistor in the device region. The transistor includes a gate having first and second sides along a gate direction. The transistor also includes a first doped region adjacent to a first side of the gate, a second doped region adjacent to a second side of the gate, and a channel under the gate. The transistor further includes a channel trench in the channel of the gate, wherein the channel trench is along a trench direction which is at an angle θ other than 90° with respect to the gate direction. | 09-18-2014 |
20140264576 | INTEGRATION OF LOW RDSON LDMOS WITH HIGH SHEET RESISTANCE POLY RESISTOR - A method for forming a low Rds | 09-18-2014 |
20140264556 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate. | 09-18-2014 |
20140264554 | BACK-GATED NON-VOLATILE MEMORY CELL - A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate. | 09-18-2014 |
20140264540 | SCALABLE AND RELIABLE NON-VOLATILE MEMORY CELL - Devices and methods for forming a device are disclosed. The method includes providing a substrate and forming a memory cell pair on the substrate. Each of a memory cell of the memory cell pair includes at least one transistor having first and second gates formed between first and second terminals and a third gate disposed over the second terminal. The first gate serves as an access gate (AG), the second gate serves as a storage gate and the third gate serves as an erase gate (EG). The first cell terminal serves as a bitline terminal and the second cell terminal serves as a source line terminal. The source line terminal is a raised source line terminal and is elevated with respect to the bit line terminal and the source line terminal is common to the memory cell pair. | 09-18-2014 |
20140264484 | FLUORINE-DOPED CHANNEL SILICON-GERMANIUM LAYER - Methods for forming P-type channel metal-oxide-semiconductor field effect transistors (PMOSFETs) with improved interface roughness at the channel silicon-germanium (cSiGe) layer and the resulting devices are disclosed. Embodiments may include designating a region in a substrate as a channel region, forming a cSiGe layer above the designated channel region, and implanting fluorine directly into the cSiGe layer. Embodiments may alternatively include implanting fluorine into a region in a silicon substrate designated a channel region, forming a cSiGe layer above the designated channel region, and heating the silicon substrate and the cSiGe layer to diffuse the fluorine into the cSiGe layer. | 09-18-2014 |
20140264334 | LAYOUT FOR RETICLE AND WAFER SCANNING ELECTRON MICROSCOPE REGISTRATION OR OVERLAY MEASUREMENTS - A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively. | 09-18-2014 |
20140264244 | NONVOLATIVE MEMORY - A phase changeable memory cell is disclosed. In an embodiment of the invention, a phase changeable memory cell is formed with an ultra-small contact area to reduce the programming current. This contact area between heater electrode and phase changeable material is limited by the thickness of thin films rather than lithographic critical dimension in one dimension. As a result, the contact area is much less than the square of lithographic critical dimension for almost every technology node, which is helps in reducing current. To further reduce the current and improve the heating efficiency, heater electrode is horizontally put with its length being tunable so as to minimize the heat loss flowing through the heater to the terminal that connects to the front end switch device. In addition, above and below the heater layer, low-thermal-conductivity material (LTCM) is used to minimize heat dissipation. This results in reduced power consumption of the phase changeable memory cell with improved reliability. | 09-18-2014 |
20140264228 | FIN SELECTOR WITH GATED RRAM - A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. | 09-18-2014 |
20140252445 | METHOD OF FORMING SPLIT-GATE CELL FOR NON-VOLATIVE MEMORY DEVICES - Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates. | 09-11-2014 |
20140242805 | LASER-ENHANCED CHEMICAL ETCHING OF NANOTIPS - A method for sharpening a nanotip involving a laser-enhanced chemical etching is provided. The method includes immersing a nanotip in an etchant solution. The nanotip includes a base and an apex, the apex having a diameter smaller than a diameter of the base. The method also includes irradiating the nanotip with laser fluence to establish a temperature gradient in the nanotip along a direction from the apex to the base of the nanotip such that the apex and base are etched at different rates. | 08-28-2014 |
20140239454 | WAFER EDGE PROTECTION - A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width W | 08-28-2014 |
20140239371 | FIELD EFFECT TRANSISTOR WITH SELF-ADJUSTING THRESHOLD VOLTAGE - Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer. | 08-28-2014 |
20140234993 | STI CMP UNDER POLISH MONITORING - Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra. | 08-21-2014 |
20140210009 | HIGH VOLTAGE FINFET STRUCTURE - Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region. | 07-31-2014 |
20140203325 | INTEGRATION OF GERMANIUM PHOTO DETECTOR IN CMOS PROCESSING - A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si. | 07-24-2014 |
20140191407 | DIELECTRIC POSTS IN METAL LAYERS - A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%. | 07-10-2014 |
20140191367 | SANDWICH DAMASCENE RESISTOR - A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL. | 07-10-2014 |
20140183654 | MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS - A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO | 07-03-2014 |
20140175594 | ACTIVE PAD PATTERNS FOR GATE ALIGNMENT MARKS - Methods for forming RX pads having gate alignment marks configured to enable noise reduction between layers while resulting in little or no non-uniformity of CMP processes for the IC, and the resulting devices, are disclosed. Embodiments include: providing, on a substrate, a RX pad having a SPM with a SPM horizontal and vertical positions at horizontal and vertical midpoints, respectively, of the first RX pad; providing a second RX pad abutting the first RX pad and a first STI pad abutting the second RX pad, each having a vertical midpoint at the SPM vertical position; forming a first gate alignment mark on the second RX pad and having vertical endpoints horizontally aligned with vertical endpoints of the second RX pad; and forming a second gate alignment mark on the first STI pad and having vertical endpoints horizontally aligned with vertical endpoints of the first STI pad. | 06-26-2014 |
20140175381 | TUNNELING TRANSISTOR - Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness T | 06-26-2014 |
20140170539 | DETERMINATION OF LITHOGRAPHY TOOL PROCESS CONDITION - A method for forming an integrated circuit (IC) is presented. The method includes providing a wafer having a substrate prepared with a photoresist layer. The photoresist layer is processed by passing a radiation from an exposure source of a lithography tool through a mask having a pattern. The process parameters of the lithography tool are determined by performing a pattern matching process. The photoresist layer is developed to transfer the pattern on the mask to the photoresist layer. | 06-19-2014 |
20140167161 | FLOATING BODY CELL - Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions. | 06-19-2014 |
20140167121 | FILAMENT FREE SILICIDE FORMATION - A device and methods for forming the device are disclosed. The method includes providing a substrate. A gate having a gate electrode and sidewall spacers are formed adjacent to sidewalls of the gate. A height H | 06-19-2014 |
20140160605 | HIGH NOISE IMMUNITY WITH LATCH-UP FREE ESD CLAMP - A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals. | 06-12-2014 |
20140160604 | LATCH-UP FREE RC-BASED NMOS ESD POWER CLAMP IN HV USE - An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor. | 06-12-2014 |
20140159169 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 06-12-2014 |
20140159168 | DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS - CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity. | 06-12-2014 |
20140159114 | VERTICAL NANOWIRE BASED HETERO-STRUCTURE SPLIT GATE MEMORY - A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell. | 06-12-2014 |
20140159113 | IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS - Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing. | 06-12-2014 |
20140158970 | NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR - An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity. | 06-12-2014 |
20140138605 | COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY - An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode. | 05-22-2014 |
20140138603 | COMPACT RRAM STRUCTURE WITH CONTACT-LESS UNIT CELL - A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines. | 05-22-2014 |
20140117545 | COPPER HILLOCK PREVENTION WITH HYDROGEN PLASMA TREATMENT IN A DEDICATED CHAMBER - A copper layer is formed without copper hillocks. Embodiments includes providing a copper layer above a substrate, planarizing the copper layer, performing hydrogen (H | 05-01-2014 |
20140117301 | WRAP AROUND PHASE CHANGE MEMORY - A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element. | 05-01-2014 |
20140110855 | CD CONTROL - A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CD | 04-24-2014 |
20140110783 | HIGH GAIN DEVICE - A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions. | 04-24-2014 |
20140103449 | OXYGEN FREE RTA ON GATE FIRST HKMG STACKS - A method of fabricating a semiconductor device with improved Vt and the resulting device are disclosed. Embodiments include forming an HKMG stack on a substrate; implanting dopants in active regions of the substrate; and performing an RTA in an environment of nitrogen and no more than 30% oxygen. | 04-17-2014 |
20140084486 | RELIABLE INTERCONNECT FOR SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material. | 03-27-2014 |
20140084366 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well which encompasses the device region and a second device well disposed within the first device well. The device further includes a drift well which encompasses the second diffusion region of which edges of the drift well do not extend below the gate and is away from a channel region, and a drain well which is disposed under the second diffusion region and extends below the gate. | 03-27-2014 |
20140077148 | RRAM CELL WITH BOTTOM ELECTRODE(S) POSITIONED IN A SEMICONDUCTOR SUBSTRATE - Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device. | 03-20-2014 |
20140070310 | INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS - A high voltage trench MOS and its integration with low voltage integrated circuits. Embodiments include forming a first trench in a substrate, the first trench having a first width; forming a first oxide layer on side surfaces of the first trench; forming a second trench in the substrate, below the first trench, the second trench having a second width less than the first width; forming a second oxide layer on side and bottom surfaces of the second trench; forming spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on the side surfaces and a top surface of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region. | 03-13-2014 |
20140070159 | NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR - An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity. | 03-13-2014 |
20140061576 | FIN-TYPE MEMORY - Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells. | 03-06-2014 |
20140054696 | NOVEL LATCH-UP IMMUNITY NLDMOS - An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region. | 02-27-2014 |
20140050439 | LITHO SCANNER ALIGNMENT SIGNAL IMPROVEMENT - A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks. | 02-20-2014 |
20140049313 | LATCH-UP ROBUST PNP-TRIGGERED SCR-BASED DEVICES - An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail. | 02-20-2014 |
20140048874 | MOS WITH RECESSED LIGHTLY-DOPED DRAIN - LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches. | 02-20-2014 |
20140048867 | MULTI-TIME PROGRAMMABLE MEMORY - A device is disclosed. The device includes a substrate and a fin structure disposed on the substrate. The fin structure serves as a common body of n transistors. The transistors include separate charge storage layers and gate dielectric layers. The charge storage layers are disposed over a top surface of the fin structure and the gate dielectric layers are disposed on sidewalls of the fin structure. n=2 | 02-20-2014 |
20140042499 | STRESS ENHANCED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain is formed in the drain region. A trench is formed in an isolation region in the device region. The isolation region underlaps a portion of the gate. An etch stop (ES) stressor layer is formed over the substrate. The ES stressor layer lines the trench. | 02-13-2014 |
20140035155 | DEVICE WITH INTEGRATED POWER SUPPLY - Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts. | 02-06-2014 |
20140034897 | METHOD FOR FORMING A PCRAM WITH LOW RESET CURRENT - Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion. | 02-06-2014 |
20140030847 | BONDING METHOD USING POROSIFIED SURFACES FOR MAKING STACKED STRUCTURES - A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material. | 01-30-2014 |
20140029354 | NON-VOLATILE MEMORY CELL WITH HIGH BIT DENSITY - A non-volatile memory cell with high bit density is disclosed. Embodiments include: providing a transistor having a wordline gate structure over a substrate, first and second floating gate structures proximate opposite sides of the wordline gate structure, and first and second diffusion regions in the substrate, wherein the wordline gate structure, the first floating gate structure, and the second floating gate structure are laterally between the first and second diffusion regions; and providing a capacitor having first, second, and third control gate structures over the substrate, a third floating gate structure between the first and second control gate structures, a fourth floating gate structure between the second and third control gate structures, and third and fourth diffusion regions in the substrate, wherein the first, second, and third control gate structures are laterally between the third and fourth diffusion regions. | 01-30-2014 |
20140028381 | HIGH SPEED LOW POWER FUSE CIRCUIT - A fuse circuit having a fuse unit cell containing two fuses. In the program/write mode, only one of the fuses in the fuse unit cell will be blown. In read mode, since only one fuse is blown, the current that goes through the two fuses in the fuse unit cell will be very small. Hence, the read power consumption for the fuse circuit is also very small and its sensing speed is also very high. | 01-30-2014 |
20140022004 | FUSE SENSING CIRCUITS - A fuse sensing circuit is disclosed. Embodiments include: providing a sense input terminal; providing a sense output terminal; and providing first and second capacitors that are configured to charge and discharge based on the sense input terminal, wherein the first and second capacitors are further configured to discharge current to a fuse unit cell, and the sense output terminal is configured to indicate a fuse state of the fuse unit cell based on the discharging of the first and second capacitors. Embodiments include the indicated fuse state being based on a discharge rate difference between the discharging of the first capacitor and the discharging of the second capacitor. | 01-23-2014 |
20140021534 | INTEGRATION OF HIGH VOLTAGE TRENCH TRANSISTOR WITH LOW VOLTAGE CMOS TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device. | 01-23-2014 |
20140019927 | WAFERLESS MEASUREMENT RECIPE - Embodiments relate to a method for manufacturing and processing semiconductor devices or integrated circuits (IC) and in particular to the generation of measurement recipes in the manufacturing of the semiconductor devices or ICs. The method comprises defining a sampling plan, mapping target locations of a device contained in the sampling plan to an article/a wafer having a plurality of said devices, verifying the mapping file and processing the verification to produce a measurement recipe. In one embodiment, the measurement recipe is created without having the actual processed wafer. | 01-16-2014 |
20140002934 | LATCH-UP IMMUNE ESD PROTECTION | 01-02-2014 |
20140001538 | DIELECTRIC STACK | 01-02-2014 |
20130341675 | LATCH-UP FREE ESD PROTECTION - An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation. | 12-26-2013 |
20130341639 | DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS - CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity. | 12-26-2013 |
20130334601 | HIGH VOLTAGE TRENCH TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region. | 12-19-2013 |
20130334584 | INTEGRATION OF MEMORY, HIGH VOLTAGE AND LOGIC DEVICES - A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (T | 12-19-2013 |
20130328118 | NON-VOLATILE MEMORY USING PYRAMIDAL NANOCRYSTALS AS ELECTRON STORAGE ELEMENTS - A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices. | 12-12-2013 |
20130328111 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 12-12-2013 |
20130325395 | CO-OPTIMIZATION OF SCATTEROMETRY MARK DESIGN AND PROCESS MONITOR MARK DESIGN - An automated method for co-optimizing a scatterometry mark and a process monitoring mark is provided. Embodiments include generating a series of pattern profiles on a photoresist on a wafer; providing the series of pattern profiles, resist process parameters, and scatterometry critical dimension parameters as inputs for a scatterometry measurement; performing scatterometry measurement to generate spectra from the series of pattern profiles; and optimizing a sensitivity precision correlation for the resist process parameter. | 12-05-2013 |
20130321963 | ESD PROTECTION CIRCUIT - An ESD circuit is disclosed. The ESD circuit includes a pad and a ground and a sensing element coupled between the pad and ground for sensing an ESD current. The sensing element generates an active sense output signal when an ESD current is sensed and an inactive sense output signal when no ESD current is sensed. The ESD circuit also includes a bypass element comprising a bi-polar junction transistor. The bypass element is coupled in parallel to the sensing element between the pad and ground. The active sense output signal causes the bypass element to be activated to provide a current path between the pad and ground. | 12-05-2013 |
20130321962 | ESD-ROBUST I/O DRIVER CIRCUITS - An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source is coupled to a ground rail, and the first drain to an I/O pad; providing a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate; and coupling the second drain to the first gate, the second source to the ground rail, wherein the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail. | 12-05-2013 |
20130321961 | ESD PROTECTION DEVICE FOR CIRCUITS WITH MULTIPLE POWER DOMAINS - A ESD protection scheme is disclosed for circuits with multiple power domains. Embodiments include: coupling a first power clamp to a first power rail and a first ground rail of a first domain; coupling a second power clamp to a second power rail and a second ground rail of a second domain; providing a blocking circuit for blocking current from an ESD event; providing an I/O interface connection in the first domain for transmitting signals from the first domain to the blocking circuit; providing a core interface connection in the second domain for transmitting signals from the blocking circuit to the second domain; coupling an input connection of the blocking circuit to the I/O interface connection; and coupling an output connection of the blocking circuit to a core interface connection. | 12-05-2013 |
20130320449 | LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS - A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask. | 12-05-2013 |
20130320398 | LATCH-UP ROBUST SCR-BASED DEVICES - An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad. | 12-05-2013 |
20130308231 | ESD PROTECTION FOR HIGH VOLTAGE APPLICATIONS - An ESD module includes an ESD circuit coupled between a first source and a second source. A trigger circuit is also included in the ESD module for activating the ESD circuit to provide a low resistance current path between the first and second sources. The trigger circuit includes a reverse diode between the first source and the ESD circuit or between the second source and main ESD circuit. The trigger circuit provides a low trigger voltage to activate the ESD circuit. | 11-21-2013 |
20130307087 | METHOD FOR FORMING A SELF-ALIGNED CONTACT OPENING BY A LATERAL ETCH - A self-aligned source/drain contact formation process without spacer or cap loss is described. Embodiments include providing two gate stacks, each having spacers on opposite sides, and an interlayer dielectric (ILD) over the two gate stacks and in a space therebetween, forming a vertical contact opening within the ILD between the two gate stacks, and laterally removing ILD between the two gate stacks from the vertical contact opening toward the spacers, to form a contact hole. | 11-21-2013 |
20130307038 | FINFET WITH STRESSORS - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility. | 11-21-2013 |
20130299874 | TMAH RECESS FOR SILICON GERMANIUM IN POSITIVE CHANNEL REGION FOR CMOS DEVICE - CMOS devices are enhanced by forming a recess in the positive channel for depositing SiGe. Embodiments include providing a positive channel region and a negative channel region in a silicon substrate for a CMOS device, with an STI region therebetween; removing a native oxide from above the positive channel region to expose a silicon substrate; forming a recess in the silicon substrate in the positive channel region adjacent the STI region; and depositing SiGe in the recess in the positive channel region, where an upper surface of the SiGe is substantially level with an upper surface of the negative channel region. | 11-14-2013 |
20130299764 | LOCALIZED DEVICE - A device is disclosed. The device includes a gate disposed on a substrate in a device region, the gate having first and second sidewalls. The gate includes a gate electrode and a resistive layer disposed between the gate electrode and substrate. First doped regions of a first polarity type are disposed in the substrate adjacent to the first and second sidewalls of the gate. The gate overlaps the first doped regions by a first distance to form overlap portions. A portion of the resistive layer between the gate electrode and overlap portions form first and second storage elements of a multi-bit resistive memory cell. | 11-14-2013 |
20130292756 | METHOD AND APPARATUS FOR UTILIZING CONTACT-SIDEWALL CAPACITANCE IN A SINGLE POLY NON-VOLATILE MEMORY CELL - An approach for utilizing electrical capacitance between a plurality of contacts and sidewalls to provide voltage coupling between a floating gate (FG) and a control gate (CG) is disclosed. Embodiments include providing an FG and a CG laterally separated from each other; coupling a plurality of parallel polysilicon lines to the FG; providing a plurality of contacts between the plurality of the parallel polysilicon lines and coupling the contacts to the CG; and forming an electrical capacitance between the plurality of contacts and sidewalls of the plurality of parallel polysilicon lines to provide voltage coupling between the CG and the FG. | 11-07-2013 |
20130286520 | METHOD AND APPARATUS FOR ESD CIRCUITS - A high performance ESD protection circuit is provided. Embodiments include a circuit having an RC clamp circuit including a first NMOS transistor having a first source, drain, and gate, a current mirror circuit including first and second PMOS transistors having a second and third source, drain, and gate, respectively, and an SCR circuit including a first P+ contact. The first source is coupled to a ground rail, the first drain is coupled to the second drain, second gate, and third gate, the second and third sources are coupled to a power rail, and the third drain is coupled to the first P+ contact, wherein during an ESD event the first NMOS and PMOS transistors turn on to discharge a first current to the ground rail, and the current mirror provides a second current to the first P+ contact for turning on the SCR. | 10-31-2013 |
20130286516 | GATE DIELECTRIC PROTECTION - Protecting a gate dielectric is achieved with a gate dielectric protection circuit coupled to a transistor at risk. The protection circuit is activated to reduce the voltage across the gate dielectric (V | 10-31-2013 |
20130279052 | ESD PROTECTION DEVICE WITH A TUNABLE HOLDING VOLTAGE FOR A HIGH VOLTAGE PROGRAMMING PAD - An ESD protection device with a tunable holding voltage is disclosed. Embodiments include: providing a silicon-controlled rectifier (SCR) having a first n-type layer with a cathode connection, a first p-type layer with a first control connection, a second n-type layer with a second control connection, and a second p-type layer with an anode connection; coupling the anode connection to a power rail; coupling the cathode connection to a ground rail; providing a tunable holding voltage control unit including a first NMOS having a first gate, a first drain, and a first source, wherein during an ESD event, the first NMOS is turned off and a holding voltage of the SCR is low; coupling the first drain to the first control connection; coupling the first source to the ground rail; and coupling the first gate to a program circuit. | 10-24-2013 |
20130277810 | METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS - Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material. | 10-24-2013 |
20130277741 | LDMOS DEVICE WITH FIELD EFFECT STRUCTURE TO CONTROL BREAKDOWN VOLTAGE, AND METHODS OF MAKING SUCH A DEVICE - In one embodiment of an LDMOS device disclosed herein, the device includes a source region, a drain region and a gate electrode that are formed in and above a semiconducting substrate, wherein the gate electrode is generally laterally positioned between the source region and the drain region, a metal-1 field plate positioned above the gate electrode, and a silicide block layer that is positioned in an area between the gate electrode and the drain region. The device further includes at least one source contact that is conductively coupled to the metal-1 field plate and a conductive structure that is conductively coupled to the metal-1 field plate, wherein at least a first portion of the conductive structure extends downward toward the substrate in the area between the gate electrode and the drain region. | 10-24-2013 |
20130270501 | RRAM DEVICE WITH AN EMBEDDED SELECTOR STRUCTURE AND METHODS OF MAKING SAME - One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material. | 10-17-2013 |
20130265677 | DRIVER-BASED DISTRIBUTED MULTI-PATH ESD SCHEME - A driver-based distributed multi-path ESD scheme is disclosed. Embodiments include providing a plurality of I/O cells, wherein each of the I/O cells includes a first driver having a first source, a first drain, and a first gate; and providing a first signal to turn on the first driver in each of the I/O cells during an ESD event to form a plurality of parallel ESD paths that include turned-on first drivers. | 10-10-2013 |
20130265676 | POWER CLAMP FOR HIGH VOLTAGE INTEGRATED CIRCUITS - A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices. | 10-10-2013 |
20130256834 | BACK-SIDE MOM/MIM DEVICES - Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate. | 10-03-2013 |
20130252350 | SYSTEM AND METHOD FOR GENERATING CARE AREAS FOR DEFECT INSPECTION - A method of generating care areas is disclosed. An artwork file of a layout of a product is provided and a cell tree of the layout is formed. The cell tree includes a plurality of cells of the layout arranged in a hierarchical order. The method also includes defining care areas in the artwork file of the layout. | 09-26-2013 |
20130240821 | THREE DIMENSIONAL RRAM DEVICE, AND METHODS OF MAKING SAME - Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line. | 09-19-2013 |
20130240142 | ISOLATION BETWEEN A BAFFLE PLATE AND A FOCUS ADAPTER - A device is provided for preventing contact between a baffle plate and a focus adapter in the upper chamber of an ashing system. The device includes a housing, a baffle plate including a plurality of holes, a focus adapter between the housing and the baffle plate, a plurality of spacers aligned with the holes, and a plurality of fasteners securing the spacers between the baffle plate and the housing, wherein the spacers isolate the focus adapter from contacting the baffle plate. | 09-19-2013 |
20130235498 | CROSS-DOMAIN ESD PROTECTION SCHEME - A cross-domain ESD protection scheme is disclosed. Embodiments include coupling a first power clamp to a first power rail and a first ground rail; providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a second ground rail; providing a first PMOS transistor having a second source, a second drain, and a second gate; coupling the second source to the first power rail; and providing, via the first power clamp, a signal to turn on the first NMOS transistor during an ESD event that occurs at the first power rail. | 09-12-2013 |
20130235496 | ESD-ROBUST I/O DRIVER CIRCUITS - An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a ground rail and the first drain to an I/O pad; coupling a gate driver control circuit to the first drain and the first gate; and providing a ground potential to the first gate, via the gate driver control circuit, during an ESD event occurring from the I/O pad to the ground rail. | 09-12-2013 |
20130234253 | SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES - A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches. | 09-12-2013 |
20130222952 | ESD PROTECTION WITHOUT LATCH-UP - A device having an ESD module is disclosed. The ESD module includes an ESD circuit coupled between first and second rails and a control circuit coupled between the rails and to the ESD circuit. When the control circuit senses an ESD event, it causes the ESD circuit to create a current path between the rails to dissipate ESD current. When no ESD event is sensed, the control circuit ensures that no current path is created between the rails to prevent latch-up. | 08-29-2013 |
20130222950 | LATCH UP DETECTION - A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event. | 08-29-2013 |
20130221308 | COMPACT RRAM DEVICE AND METHODS OF MAKING SAME - Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer. | 08-29-2013 |
20130207179 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well. | 08-15-2013 |
20130190915 | EFFICIENT TRANSFER OF MATERIALS IN MANUFACTURING - Methods for manufacturing automation and a computer executed automated handling system for forming a device are presented. The method includes issuing a transfer request by a tool. The transfer request is processed by a production control system configured for tracking and controlling the flow of carriers. The processing of the transfer request includes selecting a carrier containing production material. A transport system having transport and load/unload (U/L) units in a production area to effect a transfer is controlled and the carrier is transferred by the transport system. | 07-25-2013 |
20130187280 | Crack-Arresting Structure for Through-Silicon Vias - The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above. The device also includes a conductive structure positioned at least partially within the perimeter of the crack-arresting structure, and a conductive element extending through an opening in the crack-arresting structure, wherein the conductive element is conductively coupled to the conductive structure. | 07-25-2013 |
20130187264 | LOW OHMIC CONTACTS - A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth D | 07-25-2013 |
20130187242 | CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES - A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls. | 07-25-2013 |
20130187231 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors. | 07-25-2013 |
20130187224 | INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS - A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces; a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region. | 07-25-2013 |
20130187218 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well. | 07-25-2013 |
20130187203 | FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE - Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape. | 07-25-2013 |
20130187202 | SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE - Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer. | 07-25-2013 |
20130187116 | RRAM Device With Free-Forming Conductive Filament(s), and Methods of Making Same - Disclosed herein is an RRAM device with free-forming conductive filament(s), and various methods of making such an RRAM device. In one example, a device disclosed herein includes a first electrode, a second electrode positioned above the first electrode and a variable resistance material positioned between the first and second electrodes, wherein the variable resistance material is a metal oxide with a plurality of metal nano-crystals embedded therein. | 07-25-2013 |
20130187109 | Charging Controlled RRAM Device, and Methods of Making Same - Disclosed herein is a novel charging controlled RRAM (Resistance Random Access Memory), and various methods of making such a charging controlled RRAM device. In one example, a device disclosed herein includes a first word line structure formed above a substrate, wherein the first word line structure includes a gate electrode and a nano-crystal containing layer of insulating material, a second word line structure formed above the substrate, wherein the second word line structure comprises a gate electrode and a nano-crystal containing layer of insulating material, a first implant region formed in the substrate proximate the first word line structure, wherein the first implant region defines a first bit line, and a second implant region formed in the substrate proximate the second word line structure, wherein the second implant region defines a second bit line. | 07-25-2013 |
20130184849 | EFFICIENT TRANSFER OF MATERIALS IN MANUFACTURING - Methods for automated handling for forming a device and automated handling systems for forming a device are presented. One of the methods includes providing a production area with a plurality of destinations and a transport system which includes transport and load/unload (U/L) units in the production area. The transport units include automated guided vehicles (AGVs) with a storage compartment for holding at least one carrier containing production material for forming the device and U/L units include AGVs with a robotic system for handling carriers. A transfer of a selected carrier from a first destination to a second destination is determined. A request to the transport system is issued to effect the transfer of the selected carrier, which includes using a selected U/L unit, a selected transport unit, or a combination of selected U/L and transport units. | 07-18-2013 |
20130181287 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion. | 07-18-2013 |
20130181286 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. | 07-18-2013 |
20130181260 | METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER - Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner. | 07-18-2013 |
20130161721 | EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor. | 06-27-2013 |
20130161720 | EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor. | 06-27-2013 |
20130149851 | Methods of Protecting Elevated Polysilicon Structures During Etching Processes - Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device. | 06-13-2013 |
20130119543 | THROUGH SILICON VIA FOR STACKED WAFER CONNECTIONS - Stacked wafer connections are enhanced by forming a though silicon via including a first via portion formed in an upper portion of a via hole and a second via portion in a lower portion of the via hole. Embodiments include forming a via hole in a first surface of a substrate; partially filling the via hole with a dielectric material; filling the remainder of the via hole with a first conductive material; removing a portion of a second surface of the substrate to expose the dielectric material; removing the dielectric material from the via hole; and filling a the via hole with a second conductive material electrically conductively connected to the first conductive material. | 05-16-2013 |
20130105968 | TSV Backside Processing Using Copper Damascene Interconnect Technology | 05-02-2013 |
20130099321 | METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRATED CIRCUIT DIE USING THERMAL PROXIMITY CORRECTION - A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal. | 04-25-2013 |
20130093012 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain. | 04-18-2013 |
20130087889 | DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF - A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions. | 04-11-2013 |
20130086542 | METHOD AND APPARATUS FOR PATTERN ADJUSTED TIMING VIA PATTERN MATCHING - An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic. | 04-04-2013 |
20130082318 | INTEGRATION OF eNVM, RMG, AND HKMG MODULES - A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar. | 04-04-2013 |
20130075823 | RELIABLE CONTACTS - A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias. | 03-28-2013 |
20130074016 | METHODOLOGY FOR PERFORMING POST LAYER GENERATION CHECK - There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified. | 03-21-2013 |
20130069232 | DAMASCENE PROCESS FOR ALIGNING AND BONDING THROUGH-SILICON-VIA BASED 3D INTEGRATED CIRCUIT STACKS - Through-silicon-via (TSV) based 3D integrated circuit (3D IC) stacks are aligned, bonded and electrically interconnected using a transparent alignment material in the TSVs until the wafers are bonded. Embodiments include providing a first wafer having a first device layer and at least one first TSV filled with a conductive material, providing a second wafer having a second device layer, forming at least one second TSV in the second wafer, filling each second TSV with an alignment material, thinning the second wafer until the transparent material extends all the way through the wafer, aligning the first and second wafers, bonding the first and second wafers, removing the alignment material from the second wafer, and filling each second TSV in the second wafer with a conductive material. | 03-21-2013 |
20130069144 | TRENCH TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length L | 03-21-2013 |
20130062691 | SEMICONDUCTOR DEVICE INCLUDING AN N-WELL STRUCTURE - A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer. | 03-14-2013 |
20130049142 | TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO | 02-28-2013 |
20130043565 | INTEGRATED CIRCUIT SYSTEM WITH SUB-GEOMETRY REMOVAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data. | 02-21-2013 |
20130037877 | DOUBLE GATED FLASH MEMORY - A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate. | 02-14-2013 |
20130034954 | INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY - An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas. | 02-07-2013 |
20130032869 | SPLIT-GATE FLASH MEMORY WITH IMPROVED PROGRAM EFFICIENCY - A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel. | 02-07-2013 |
20130031521 | METHOD AND APPARATUS FOR PREEMPTIVE DESIGN VERIFICATION VIA PARTIAL PATTERN MATCHING - An approach is provided for preemptive design verification via partial pattern matching. Data corresponding to one or more problematic layout patterns associated with an integrated circuit manufacturing process is received. Data corresponding to a block of intellectual property including a layout design is received. At least a boundary of the layout design is scanned against the one or more problematic layout patterns. One or more partial matches of the one or more problematic layout patterns are identified at least at the boundary. Results are generated indicating the one or more partial matches. | 01-31-2013 |
20130026565 | LOW RDSON RESISTANCE LDMOS - A device having a salicide block spacer on a second side of a gate is disclosed. The use of the salicide block spacer indirectly reduces the blocking effects during the implantation processes, thereby lowering the Rdson without compromising the breakdown voltage of the device. | 01-31-2013 |
20130026552 | SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE - A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack. | 01-31-2013 |
20130020626 | MEMORY CELL WITH DECOUPLED CHANNELS - A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel. | 01-24-2013 |
20130001793 | PACKAGE INTERCONNECTS - A method for forming a device is disclosed. A substrate having first and second major surfaces is provided. A stress buffer is formed in the substrate. A through silicon via (TSV) contact is formed between the stress buffer. The stress buffer has a depth less than a depth of the TSV contact. The stress buffer alleviates stress created by the difference in coefficient thermal expansion (CTE) between the TSV contact and the substrate. | 01-03-2013 |
20130001688 | SELF-ALIGNED BODY FULLY ISOLATED DEVICE - A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs. | 01-03-2013 |
20120319246 | IP PROTECTION - Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners. | 12-20-2012 |
20120299155 | METHOD FOR FORMING FULLY RELAXED SILICON GERMANIUM ON SILICON - Semiconductor devices are formed with a thin layer of fully strain relaxed epitaxial silicon germanium on a substrate. Embodiments include forming a silicon germanium (SiGe) epitaxial layer on a semiconductor substrate, implanting a dopant into the SiGe epitaxial layer, and annealing the implanted SiGe epitaxial layer. | 11-29-2012 |
20120297352 | METHOD AND APPARATUS FOR CREATING AND MANAGING WAIVER DESCRIPTIONS FOR DESIGN VERIFICATION - Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error. | 11-22-2012 |
20120292719 | HIGH-K METAL GATE DEVICE - A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness T | 11-22-2012 |
20120286349 | Non-Volatile Memory Device With Additional Conductive Storage Layer - In one example, the memory device includes a gate insulation layer, a first conductive storage layer positioned above the gate insulation layer and a first non-conductive charge storage layer positioned above the first conductive storage layer. The device further includes a blocking insulation layer positioned above the first non-conductive charge storage layer and a gate electrode positioned above said blocking insulation layer. | 11-15-2012 |