| GLOBAL UNICHIP CORPORATION Patent applications |
| Patent application number | Title | Published |
|---|
| 20120128059 | Method of adaptive motion estimation in search windows for video coding - The invention discloses a method of adaptive motion estimation in search windows for video coding, which uses adjacent MBs to predict the range of search window, storing MVs of adjacent MBs respectively for each reference frame, then using MVs of three adjacent MBs to delimit the scope of search window on the same reference frame. It could derive the most similar MB from the scope of search window than the current MB. | 05-24-2012 |
| 20120110525 | HYBRID ELECTRONIC DESIGN SYSTEM AND RECONFIGURABLE CONNECTION MATRIX THEREOF - A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit. | 05-03-2012 |
| 20120109616 | Method to synchronize and synthesize bus transaction traces for an un-timed virtual environment - The invention discloses to a method to synchronize and synthesize bus transaction traces for an un-timed virtual environment. The steps are the followings providing a simulation environment and an emulation environment; recording the transaction of intellectual property (IP) through the bus, collecting the plurality of continuously transferred transaction set, connecting a plurality of transaction blocks recorded from the simulation environment, and assigning a corresponding number to the transaction block; labeling a begin time mark and a transfer time mark; initializing a plurality of parameters; taking a transaction block; judging the type of the transaction block respectively; and after respectively assuring that the transaction block is the last transaction block in the simulated transaction block series, output these parameter values. | 05-03-2012 |
| 20120104581 | Semiconductor package device with a heat dissipation structure and the packaging method thereof - The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism. | 05-03-2012 |
| 20120033335 | ESD Protection Scheme for Integrated Circuit Having Multi-Power Domains - The invention provides systems and methods for ESD protection for an integrated circuit (IC) having multi-power domains. The IC comprises a first device in a first power domain having a first power line and a first ground line and a second device in a second power domain having a second power line and a second ground line. A clamp circuit having a first node and a second node is coupled to the first device and the second device to provide cross-domain protection. Alternatively, two clamp circuits are used to couple with the first device and the second device to provide cross-domain ESD protection. | 02-09-2012 |
| 20120032328 | Package structure with underfilling material and packaging method thereof - A method for packaging semiconductor device is provided, which comprises: providing a carrier substrate having a top surface and a back surface, a circuit arrangement on the top surface of the carrier substrate, and a through hole is disposed near the center of the carrier substrate and is formed passed through the carrier substrate; providing a chip having an active surface and a back surface, a plurality of pads is disposed on the periphery of the active surface and a plurality of connecting elements is disposed thereon; the active surface of chip is flipped and bonded on the circuit arrangement on the top surface of the carrier substrate, and the plurality of connecting elements is not covering the through hole; filling the underfilling material to encapsulate between the plurality of connecting elements and the top surface of the carrier substrate and to fill with the through hole; and performing a suction process to remove the air within the underfilling material between the plurality of connecting elements on the chip and the top surface of the carrier substrate, such that the underfilling material can completely encapsulate between the plurality of connecting elements on the chip and the top surface of the carrier surface. | 02-09-2012 |
| 20120025867 | Device for storing pulse latch with logic circuit - A device for storing pulse latch with logic circuit and thus having signal maintaining function is provided, wherein the device is composed of a data signal, a scan data input signal, a stored signal, a choosing data input signal, a time clock signal, a restoring signal, a first signal channel, a scan latch, a second signal channel, a pulse latch, a normal output signal, an output signal, a first OR gate, a second OR gate, a third OR gate, a AND gate and an inverter connecting to one another. The device may store the data when being switch off and restore the data when being switch on again. | 02-02-2012 |
| 20120025860 | Burn-in socket and testing fixture using the same - A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning portions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier. | 02-02-2012 |
| 20120021564 | Method for packaging semiconductor device - The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased. | 01-26-2012 |
| 20120020444 | Slicing level and sampling phase adaptation circuitry for data recovery systems - The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers. | 01-26-2012 |
| 20120020436 | Method and device for multi-channel data alignment in transmission system - A method and a device for multi-channel data alignment in a transmission system are provided, wherein the method comprises receiving a first stream data and a second stream data, determining a deleting/inserting state of the first stream data and the second stream data to generate an information of mismatch data due to a speed difference situation, generating a reverse inserting control signal or a reverse deleting control signal to completely restore the original first stream data and/or the original second stream data at a transmission end, deleting/inserting the first stream data and the second stream data simultaneously after receiving the deleting/inserting state of the first stream data and the second stream data, and outputting the corrected first stream data and the corrected second stream data without mismatching. | 01-26-2012 |
| 20120020203 | Clock and data recovery system - This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner. | 01-26-2012 |
| 20120018884 | Semiconductor package structure and forming method thereof - The present invention provides a semiconductor package structure, which includes a substrate having a top surface and a back surface, a plurality of first connecting points on the top surface and a plurality of second connecting points on the back surface; a chip having an active surface and back surface, a plurality of pads on the active surface, and the chip is attached on the top surface of the substrate; a plurality of wires is electrically connected the plurality of pads on the active surface of the chip with the plurality of first connecting points on the top surface of substrate; a first encapsulant is filled to cover portion of the plurality of wires, the chip, and the portion of top surface of the substrate; a second encapsulate is filled to cover the first encapsulant, the plurality of wires and is formed on portion of the top surface of the substrate, in which the Yang's module of the second encapsulant is different with that of the first encapsulant; and a plurality of connecting components is disposed on the back surface of the substrate and is electrically connected the plurality of second connecting points. | 01-26-2012 |
| 20120012841 | Through-silicon via testing structure - A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal. | 01-19-2012 |
| 20110307764 | Data transfer protection apparatus for flash memory controller - The invention discloses a data transfer protection apparatus for a flash memory controller, placed between BCH and NAND Flash Chip. In encode path the hardware module selects a sequence of constant values, exclusive-or the original parity with that constant value. In decode path the hardware module detects the parity period, exclusive-or the parity which is read out from NAND Flash Chip with the same constant value sequence. | 12-15-2011 |
| 20110084682 | PROGRAMMABLE CURRENT MIRROR - A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node. | 04-14-2011 |
