| Global Unichip Corp. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120102447 | System and Method for Optimizing Logic Timing - In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of logic. The system is also configured to identify a last node along one of the plurality logic path that violates the timing condition, and insert a buffer at least one node before the last node along the one of the plurality of logic paths that violates the timing condition. The buffer also has a delay optimized to fix the timing condition. | 04-26-2012 |
| 20120098592 | FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR - A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module. | 04-26-2012 |
| 20120001690 | System for Driver Amplifier - In an embodiment, a circuit includes a two-stage amplifier and a feedback component. The two stage amplifier consists of an input stage biased at a first power supply voltage, and an output stage biased at a second power supply voltage. The second power supply voltage is greater than the first power supply voltage, and the second stage is configured for high voltage operation. The feedback component is connected between the output stage to the input stage. | 01-05-2012 |
| 20110304998 | Package Substrate - In accordance with an embodiment, a substrate layout comprises a ground plane of a first power loop on a layer of a substrate, a first trace rail on the layer extending along a first periphery of the ground plane, and a first perpendicular trace coupled to the first trace rail. The ground plane is between the first trace rail and a die area, and the first perpendicular trace extends perpendicularly from the first trace rail. The first trace rail and the first perpendicular trace are components of a second power loop. | 12-15-2011 |
