| FUJITSU SEMICONDUCTOR LIMITED Patent applications |
| Patent application number | Title | Published |
|---|
| 20120129338 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - When a wiring structure is formed by a trench-first dual damascene method, a first hard mask for forming via holes and a second hard mask for forming wiring trenches are sequentially formed on an interlayer insulating film, openings are formed at the first hard mask while using the second hard mask as a mask, and thereafter, the openings are expanded in a lateral direction by an isotropic etching to form openings, via holes are formed by etching the interlayer insulating film while using the first hard mask and the second hard mask as masks, and wiring trenches communicating with the via holes are formed by etching the interlayer insulating film while using the second hard mask as a mask. | 05-24-2012 |
| 20120129335 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask. | 05-24-2012 |
| 20120127782 | STATIC RAM - A static RAM includes a plurality of word lines, a plurality of global bit line pairs, a plurality of static-type memory cells, a plurality of sense amplifiers, a plurality of local bit line pairs provided in correspondence with each global bit line pair, and a plurality of global switches, wherein the plurality of static-type memory cells is connected to the corresponding local bit line pair in response to a row selection signal, and at the time of read, the row selection signal is applied to the word line and after the corresponding local bit line pair is brought into a state corresponding to contents stored in the memory cell, application of the row selection signal is stopped and then the corresponding global switch is brought into a connection state and after changing the state of the global bit line pair, the corresponding sense amplifier is operated. | 05-24-2012 |
| 20120127776 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device has word, bit, plate lines; memory cells having access gate and ferroelectric capacitor; latch amplifier for latching stored data; and write amplifier for driving bit lines according to write data. The bit lines are precharged to a reference potential before an active period. In active period, at a first time, selected word line and plate line are driven to a high-level potential so that ferroelectric capacitor output electric charge to selected bit line, and at a second time, selected bit line is brought to reference potential regardless of write data so that first data is written to selected memory cell, and at a third time, plate line is driven to reference potential and is maintained; and in a precharge period, the write amplifier drives selected bit line to high-level potential according to write data so that second data is written to selected memory cell. | 05-24-2012 |
| 20120126907 | OSCILLATION CIRCUIT - An oscillation circuit has a first inverter connected to an external piezoelectric resonator, a first feedback resistor disposed between input/output terminals of the first inverter, first/second variable capacitive elements connected to input/output of the first inverter, a charging circuit supplying input/output terminal with a reference current to charge the capacitive element, a comparator comparing a charging voltage of input/output with a reference voltage, and a control circuit that, in a calibration operation, at a first time, causes the charging circuit to start supply the reference current to the input terminal or the output terminal, and, at a second time after the first time, generates the control signal for setting a capacitance value of the first or second variable capacitive element so that the charging voltage becomes close to the reference voltage according to a comparison result of the comparator. | 05-24-2012 |
| 20120124407 | SEMICONDUCTOR DEVICE AND RESET CONTROL METHOD IN SEMICONDUCTOR DEVICE - Reset request from external are held at a reset request holding unit having holding units connected in series; a reset switching unit performs a logical product operation of all of outputs of the holding units to set it as an asynchronous reset request, setting an output of the holding unit at a final stage of the holding units as a synchronous reset request, performing a logical product operation of the asynchronous reset request and the synchronous reset request, and outputs an operation result; the asynchronous reset request is masked in a synchronous reset mode; and a reset signal is output from a reset output unit based on the operation result at the reset switching unit. | 05-17-2012 |
| 20120120739 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 05-17-2012 |
| 20120119786 | SEMICONDUCTOR DEVICE - A stop of a detection object clock is detected by inverting a signal level of an output signal of a level output unit at a count completion time at a counter unit operated by a detection clock and of which count value is changeable, and by determining whether or not a signal level change passes through a clock detection unit operated by the detection object clock by comparing signal levels of an output signal of a level output unit and an output signal of a clock detection unit. | 05-17-2012 |
| 20120119326 | CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor includes first electrode patterns and second electrode patterns disposed alternately on a plane, each of the first electrode patterns having a linear shape and extending in a first direction from a first end to a third end with a first length, each of the second electrodes having a linear shape and extending in said first direction from a second end to a fourth end with a second length shorter than the first length, a first wiring pattern supplying a first voltage to the first electrode patterns by first via-plugs, and a second wiring pattern supplying a second voltage to the second electrode patterns by second via-plugs, wherein the first end of the first electrode pattern extends beyond the second end of the second electrode pattern and the third end of the first electrode pattern extends beyond the fourth end of said the electrode. | 05-17-2012 |
| 20120119299 | SEMICONDUCTOR DEVICE MANUFACTURE METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes: forming a first active region and a second active region in a semiconductor substrate; forming a first gate insulating film on the first active region and a second gate insulating film thinner than the first gate insulating film on the second active region by using material containing silicon oxide; forming first and second gate electrodes on the first and second gate insulating films respectively; forming an insulating film on the semiconductor substrate, and anisotropically etching the insulating film to leave first side wall insulating films on side walls of the first and second gate electrodes; removing the first side wall insulating film on the first gate electrode; and after removing the first side wall insulating film on the first gate electrode, thermally treating in an oxidizing atmosphere the semiconductor substrate to form a second side wall insulating film on the first gate electrode. | 05-17-2012 |
| 20120119292 | SEMICONDUCTOR DEVICE - A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between. | 05-17-2012 |
| 20120119267 | SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device production method includes: forming a semiconductor region including a first region, a second region connecting with the first region and having a width smaller than that of the first region, and a third region connecting with the second region and having a width smaller than that of the second region; forming a gate electrode including a first part crossing the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity into the first region and the remaining part of the second region; performing heat treatment; removing part of the side wall insulation film, and forming a silicide layer on the first region and the remaining part of the second region. | 05-17-2012 |
| 20120115291 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first MISFET having a first conduction type channel and formed on a semiconductor substrate; a second MISFET having a second conduction type channel and formed on the semiconductor substrate; a first strain film having a first sign strain that covers a region where the second MISFET is disposed; and a second strain film having a second sign strain that covers a region where the first MISFET is disposed. In the semiconductor device, an edge of the second strain film closer to the second MISFET overlaps with part of the first strain film; and the second strain film at a portion where the second strain film overlaps with the first strain film and at a portion extending from the portion, is thinner than the second strain film at a portion that covers the first MISFET. | 05-10-2012 |
| 20120115252 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film. | 05-10-2012 |
| 20120112316 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME - Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm. | 05-10-2012 |
| 20120110527 | CONNECTION VERIFICATION METHOD, RECORDING MEDIUM THEREOF, AND CONNECTION VERIFICATION APPARATUS - A connection verification method is disclosed. A computer verifies a connection between a first node and a second node by starting from the first node in a designed integrated circuit, based on connection information stored in a storage part. The computer detects whether a module connected to the second node is a predetermined module predetermined module having a logic condition therein, based on connection relationship logic information stored in the storage part. The computer conducts a connection verification starting the module to verify a connection between the module and a third node when the module is the predetermined module. | 05-03-2012 |
| 20120110307 | COMPRESSED INSTRUCTION PROCESSING DEVICE AND COMPRESSED INSTRUCTION GENERATION DEVICE - A compressed instruction processing device has: a compressed instruction expanding circuit which expands a compressed instruction code that include a difference code between an instruction code being a compression object and a reference instruction code and which outputs an expanded instruction code; an instruction buffer storing the instruction code expanded by the compressed instruction expanding circuit; and an execution section executing the instruction code expanded by the compressed instruction expanding circuit, wherein the compressed instruction expanding circuit outputs the expanded instruction code by inputting the instruction code in the instruction buffer as the reference instruction code and adding the reference instruction code and the difference code in the compressed instruction code. | 05-03-2012 |
| 20120108025 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess. | 05-03-2012 |
| 20120108022 | SEMICONDUCTOR DEVICE INCLUDING A P-CHANNEL TYPE MOS TRANSMITTER - A method of manufacturing a semiconductor device including a stacked gate type nonvolatile memory cell and a p-channel type first transistor, includes: forming a gate insulating film of the first transistor on a semiconductor substrate; forming a tunnel insulating film of the stacked gate type nonvolatile memory cell on the semiconductor substrate; forming a first conductive layer containing an n-type impurity on the tunnel insulating film and the gate insulating film; and implanting p-type impurity ions to a region of the first conductive layer for forming the first transistor to turn the region of the first conductive layer into a p-type region. | 05-03-2012 |
| 20120107965 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside. | 05-03-2012 |
| 20120107963 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film. | 05-03-2012 |
| 20120106938 | IMAGING CONTROL UNIT, IMAGING APPARATUS, AND IMAGING CONTROL METHOD - An imaging control unit includes: a detecting unit that detects a focused-status of a focus detecting range set to an image data of each frame; a setting unit that sets, at a position of a distinctive-region including a distinctive points of an object detected from an processed image data, a focus detecting range of an image data of a subsequent frame; and a control unit that performs, when the focus detecting range is not in focused-status, a focal length control to change a focal length of a imaging lens so that the focus detecting range is in focused-status. When a displacement amount from the focus detecting range set to the imaged image data to the distinctive-region detected in the processed image data based on the imaged image data is large, the control unit aborts performing the focal length control even when the focus detecting range is not in focused-status. | 05-03-2012 |
| 20120106094 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 05-03-2012 |
| 20120105157 | VARIABLE GAIN AMPLIFIER - A variable gain amplifier includes a source-grounded transistor, to a gate of which an input signal is supplied; a plurality of first cascode transistors, sources of which are connected to a drain of the source-grounded transistor; a second cascode transistor, a source of which is connected to the drain of the source-grounded transistor; a first gate-grounded transistor, a source of which is connected to drains of the plurality of first cascode transistors, and to a gate of which a constant voltage is applied; and an output load connected to a drain of the first gate-grounded transistor wherein the plurality of first cascode transistors and the second cascade transistor are put into a conducting state or a non-conducting state such that a drain current of the source-grounded transistor is constant and moreover a fraction of the drain current supplied to the plurality of first cascade transistors changes. | 05-03-2012 |
| 20120105146 | REGULATOR CIRCUIT - A first transistor coupled between a power supply line and an inductor, a second transistor coupled between a source of the first transistor and a reference voltage line, and a third transistor coupled between the source of the first transistor and a load are included, and efficiency deterioration caused by a dead time is improved by keeping a current flow through a current path of an inductor, a load, and the third transistor during the dead time by supplying a voltage which is less than a threshold voltage and approximately the threshold voltage to a gate of the third transistor as a gate voltage. | 05-03-2012 |
| 20120104606 | BALL GRID ARRAY SEMICONDUCTOR DEVICE AND ITS MANUFACTURE - A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts. | 05-03-2012 |
| 20120104477 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process. | 05-03-2012 |
| 20120099683 | DEMODULATION DEVICE - There is provided a demodulation device including: a demodulation unit demodulating an input signal to thereby output a signal of IQ coordinates; and a first noise elimination circuit eliminating a noise in the signal of the IQ coordinates that is output from the demodulation unit, in which the first noise elimination circuit includes: a first subtracter subtracting a first noise replica signal from the signal of the IQ coordinates that is output from the demodulation unit; an error information generation unit calculating error information of an output signal of the first subtracter to an ideal signal point of the IQ coordinates; a first frequency detection unit detecting a frequency of the noise based on the error information; and a first amplitude adjusting unit adjusting an amplitude of the first noise replica signal based on the error information and the frequency of the noise detected in the first frequency detection unit to output the first noise replica signal to the first subtracter. | 04-26-2012 |
| 20120099385 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITE METHOD FOR THE SAME - A nonvolatile semiconductor storage device includes an identification code generating circuit, a simultaneous write bit count calculation circuit, a write range calculation circuit, and a program pulse generating circuit. The identification code generating circuit generates an identification code to be assigned to every one of bits to be written, and the simultaneous write bit count calculation circuit calculates the number of bits to be written simultaneously, the number being equalized based on the generated identification code, within a range that does not exceed a maximum simultaneously writable bit number. The write range calculation circuit calculates a write range, based on the calculated number of bits to be written simultaneously, and the program pulse generating circuit generates a program pulse based on write data and on the generated identification code and the calculated write range. | 04-26-2012 |
| 20120098988 | IMAGE PROCESSOR, ELECTRONIC DEVICE INCLUDING IMAGE PROCESSOR, AND IMAGE PROCESSING METHOD - An image processor includes a first correction circuit that outputs a first correction value, which corresponds to a pixel value of an input image, based on a first correction characteristic. A second correction circuit outputs a second correction value, which corresponds to the pixel value of the input image, based on a second correction characteristic. A control circuit controls a ratio for mixing the first correction value and the second correction value. A mixing circuit that mixes the first correction value and the second correction value based on the ratio. A corrected pixel value, which corresponds to the pixel value of the input image, is generated in accordance with an output value of the mixing circuit. | 04-26-2012 |
| 20120098683 | ANALOG-TO-DIGITAL CONVERSION APPARATUS AND OFFSET VOLTAGE CORRECTION METHOD - An analog-to-digital conversion apparatus has a plurality of comparators configured to compare each of a plurality of different reference voltages and an input signal voltage in a parallel manner, a switch unit configured to switch the input signal voltage to a voltage corresponding to an analog input signal voltage or one of the plurality of reference voltages, an encoder configured to convert comparison results of the plurality of comparators into digital signals, and a digital assist circuit configured to control the switch unit so that the input signal voltage has a potential corresponding to the reference voltage in the comparator being the correction target among the plurality of comparators, to generate correction data for correcting the offset voltage generated in the comparator being the correction target based on the digital signal and to output it to the comparator being the correction target. | 04-26-2012 |
| 20120098091 | SEMICONDUCTOR DEVICE SUBSTRATE AND SEMICONDUCTOR DEVICE - There is provided a semiconductor device substrate including: a multi-layer wiring layer; a first capacitor pad which is provided on an uppermost layer of the multi-layer wiring layer, and which includes a first power supply pad connected to a power supply layer of the multi-layer wiring layer through a first via and a first ground pad connected to a ground layer of the multi-layer wiring layer through a second via; and a second capacitor pad which is provided on the uppermost layer of the multi-layer wiring layer, and which includes a second power supply pad connected to the first power supply pad through a first wire and a second ground pad connected to the first ground pad through a second wire. | 04-26-2012 |
| 20120098038 | SEMICONDUCTOR DEVICE - A semiconductor device includes a high-side field-effect transistor including a high-side drain electrode, a high-side gate electrode, and a high-side source electrode; and a first low-side field-effect transistor including a first low-side drain electrode, a first low-side gate electrode and a first low-side source electrode, wherein the high-side source electrode and the first low-side drain electrode are shared as a single source and drain electrode, and the high-side drain electrode, the high-side gate electrode, the source and drain electrode, the first low-side gate electrode and the first low-side source electrode are arranged in this order while being interposed by gaps, respectively. | 04-26-2012 |
| 20120095737 | POWER ESTIMATOR AND POWER ESTIMATION METHOD - In a power estimator, a power coefficient-calculating section acquires an average value of the number of signal changes per unit time in each circuit range to thereby calculate a power coefficient for each circuit range or calculate a power coefficient for each circuit range when the average value of the number of signal changes per unit time is equal to 1, a correction coefficient-calculating section calculates a ratio of an average value of the number of signal changes per unit time at signal lines included in the circuit range to an average value of the number of signal changes per unit time at observing points designated in the circuit range, as a correction coefficient, and a power value-calculating section calculates a power value for each circuit range based on the correction coefficient and the power coefficient calculated for each circuit range. | 04-19-2012 |
| 20120094398 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film. | 04-19-2012 |
| 20120091986 | SEMICONDUCTOR DEVICE AND POWER SUPPLY APPARATUS - A semiconductor device includes a first transistor including a GaN-based semiconductor stacked structure formed over a substrate, a first gate electrode having a plurality of first fingers over the semiconductor stacked structure, a plurality of first drain electrodes provided along the first fingers, and a plurality of first source electrodes provided along the first fingers; a second transistor including the semiconductor stacked structure, a second gate electrode having a plurality of second fingers over the semiconductor stacked structure, the second drain electrodes provided along the second fingers, and a plurality of second source electrodes provided along the second fingers; a drain pad provided over or under the first drain electrodes, and coupled to the first drain electrodes; a source pad provided over or under the second source electrodes, and coupled to the second source electrodes; and a common pad coupled to the first source electrodes and the second drain electrodes. | 04-19-2012 |
| 20120091981 | SWITCHING REGULATOR - A switching regulator has an output circuit having first and second transistors and a connection node thereof as an output terminal; a switching control unit generating a first and second switching pulses for alternately switching the first and second transistors according to the load; and a first comparator monitoring an output voltage, and generating a pulse stopping control signal for stopping the generation of the switching pulses when the output voltage rises, and for generating the switching pulses when the output voltage drops. And the switching control unit performs a stopping operation for stopping the switching pulse generation and a switching operation for generating the switching pulse in response to the pulse stopping control signal, and outputs, to the first comparator, a timing control signal for quickening a switching timing from the stopping operation to the switching operation as the load of the load circuit increases. | 04-19-2012 |
| 20120091534 | SEMICONDUCTOR DEVICE WITH STRAIN - A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region. | 04-19-2012 |
| 20120089386 | SIMULATION APPARATUS, COMPUTER-READABLE RECORDING MEDIUM, AND METHOD - A simulation apparatus is disclosed, including a hardware simulator and a CPU model. The hardware simulator activates one or more logical hardware models for verifying embedded software. The CPU model is one of the one or more logical hardware models which imitates a CPU which executes the embedded software, and to trigger the embedded software to operate without synchronization for each of instructions. | 04-12-2012 |
| 20120087576 | IMAGE PROCESSING DEVICE - An image processing device has a classification unit that generates a lookup table by dividing color palettes correlating RGB data with indices into a plurality of groups based on a relationship among R values, G values and B values of the RGB data; a storage unit that stores the lookup table; and a conversion unit that determines to which of the plurality of groups pixel data having the RGB data corresponds based on a relationship among R values, G values and B values of the pixel data, and searches for RGB data that is similar to the RGB data of the pixel data in the determined group, and outputs an index corresponding to the searched RGB data as pixel data. | 04-12-2012 |
| 20120087195 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode. | 04-12-2012 |
| 20120086105 | SEMICONDUCTOR DEVICE HAVING CAPACITOR CAPABLE OF REDUCING ADDITIONAL PROCESSES AND ITS MANUFACTURE METHOD - A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film. | 04-12-2012 |
| 20120084513 | CIRCUIT AND METHOD FOR DETERMINING MEMORY ACCESS, CACHE CONTROLLER, AND ELECTRONIC DEVICE - A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination. | 04-05-2012 |
| 20120083087 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A protection film is formed on a semiconductor substrate. Impurity ions are implanted into the semiconductor substrate through the protection film. The impurity is activated to form an impurity layer. The protection film is removed after forming the impurity layer. The semiconductor substrate of a surface portion of the impurity layer is removed after removing the protection film. A semiconductor layer is epitaxially grown above the semiconductor substrate after removing the semiconductor substrate of the surface portion of the impurity layer. | 04-05-2012 |
| 20120083082 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes forming a trench to be an alignment mark in a semiconductor substrate, forming a mask film exposing a region to be a device isolation region and covering a region to be a device region by aligning with the alignment mark above the semiconductor substrate with the trench formed in, anisotropically etching the semiconductor substrate with the mask film as a mask to form a device isolation trench in the region to be the device isolation region of the semiconductor substrate, and burying the device isolation trench by an insulating film to form a device isolation insulating film. In forming the trench, the trench is formed in a depth which is smaller than a depth equivalent to a thickness of the mask film. | 04-05-2012 |
| 20120083079 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region. | 04-05-2012 |
| 20120081645 | REFLECTION TYPE LIQUID CRYSTAL DISPLAY DEVICE FORMED ON SEMICONDUCTOR SUBSTRATE - Above a semiconductor substrate on which switching semiconductor elements are formed respectively corresponding to a plurality of pixels, a first and a second copper wiring layers and thereon an aluminum reflection electrode layer are arranged. Wirings and first and second light shielding layers are formed by patterning the copper wiring layers and pluralities of first and second openings are formed respectively in the first and the second light shielding layers. The first openings and the second openings are shifted in two directions not to overlap each other in a plan view. The wiring layers and the light shielding layers are formed of copper while restraining dishing. | 04-05-2012 |
| 20120081170 | DIVIDER AND MIXER CIRCUIT HAVING THE SAME - A divider has a clock generation circuit which combines a first trigger clock and a second trigger clock having a first phase difference, so as to generate a third clock having pulse edges corresponding to pulse edges of the first trigger clock and the second trigger clock; an output dividing circuit which divides the frequency of the third clock in half so as to generate a first differential output clock and a second differential output clock having a duty ratio corresponding to the first phase difference; and a phase correction circuit which detects a phase of the first output clock or the second output clock at a timing of the pulse edge of the first trigger clock or the second trigger clock, so as to generate a phase correction signal for resetting the output dividing circuit when the detected phase is not a normal phase. | 04-05-2012 |
| 20120081085 | POWER SUPPLY CONTROLLER, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING POWER SUPPLY - A comparator type power supply controller that controls an output voltage. The power supply controller includes a comparator that compares a feedback voltage, which corresponds to the output voltage, with a reference voltage, wherein the comparator instructs power supply when the feedback voltage decreases when the feedback voltage decreases from the reference voltage. An offset application circuit is coupled to the comparator. The offset application circuit controls an input offset voltage of the comparator and decreases the input offset voltage as time elapses when the feedback voltage becomes lower than the reference voltage after the power supply ends. An amplifier amplifies a voltage difference of the feedback voltage and the reference voltage. The offset application circuit increases a change speed of the input offset voltage as the voltage difference increases in accordance with an output voltage of the amplifier. | 04-05-2012 |
| 20120080759 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region. A second transistor includes a second impurity layer of the first conduction type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and being thinner than the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer, a second gate electrode formed above the second gate insulating film, and second source/drain regions of the second conduction type formed in the second epitaxial semiconductor layer and in the semiconductor substrate in the second region. | 04-05-2012 |
| 20120080754 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions. | 04-05-2012 |
| 20120077326 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In forming a ferro-electric capacitor structure of an FeRAM, a lower electrode film is formed (step S | 03-29-2012 |
| 20120077288 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film | 03-29-2012 |
| 20120076142 | PACKET COMMUNICATION DEVICE AND PACKET COMMUNICATION METHOD - A packet communication device for switching packets to be transferred in packet communication which is time-managed in constant cycles, the packet communication device includes a changing section configured to change a portion of a first packet to be transmitted in each of the constant cycles. | 03-29-2012 |
| 20120075128 | SUCCESSIVE APPROXIMATION A/D CONVERTER - A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error. | 03-29-2012 |
| 20120074926 | INTEGRATED CIRCUIT WITH POWER STATE DETERMINATION CIRCUIT - An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal. | 03-29-2012 |
| 20120074550 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a die stage; an inner lead provided near the die stage; and a bus bar provided between the die stage and the inner lead and supported by a hanging lead, wherein the hanging lead is inclined with respect to the inner lead, and a wire connection face of the bus bar is displaced with respect to a wire connection face of the inner lead in a direction of a frame thickness. | 03-29-2012 |
| 20120074478 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - As for a bypass capacitor, a first capacitor insulating film, together with a tunnel insulating film of a storage element, is formed of a first insulating film, a first electrode being a lower electrode, together with floating gate electrodes of the storage element, is formed of a doped·amorphous silicon film (a crystallized one), a second capacitor insulating film, together with a gate insulating film of transistors of 5 V in a peripheral circuit, is formed of a second insulating film, and a second electrode being an upper electrode, together with control gate electrodes of the storage element and gate electrodes of the transistors in the peripheral circuit, is formed of a polycrystalline silicon film. | 03-29-2012 |
| 20120070974 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask. | 03-22-2012 |
| 20120070969 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes steps of preparing a semiconductor substrate having a first conductive type; implanting a first impurity having the first conductive type in the semiconductor substrate to form a well region having a bottom portion; and implanting a second impurity having a second conductive type in the semiconductor substrate to form an impurity region having a top portion, the top of the impurity region being in contact with the bottom portion of the well region. Implantation of the second impurity includes a first step of implanting the second impurity and a second step of implanting the second impurity, wherein a first implantation area of the first step of implanting the second impurity being broader or narrower than a second implantation area of the second step of implanting the second impurity. | 03-22-2012 |
| 20120068746 | PHASE-LOCKED LOOP CIRCUIT AND DELAY-LOCKED LOOP CIRCUIT - A phase-locked loop circuit includes a phase comparator that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference therebetween; a charge pump that outputs a charge pump current according to the phase difference signal; a low-pass filter that includes a resistor and a capacitor and that smoothes the charge pump current and converts the smoothed current into a control voltage; a voltage-controlled oscillator that generates an oscillation signal with a frequency according to the control voltage; and a frequency divider that generates a frequency-divided signal by frequency-dividing the oscillation signal and outputs the frequency-divided signal to the phase comparator as the feedback signal, wherein the resistor in the low-pass filter is a variable resistor that is changed according to the control voltage. | 03-22-2012 |
| 20120068308 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION METHOD - A semiconductor device includes a semiconductor substrate, a heat generating device, and a heat radiating part. The heat generating device is provided on the semiconductor substrate, and the heat radiating part is provided above the heat generating device. The heat radiating part is thermally coupled with the semiconductor substrate through at least one contact part. | 03-22-2012 |
| 20120062578 | GRAPHIC PROCESSING APPARATUS AND COMPUTER-READABLE MEDIUM STORING GRAPHIC PROCESSING PROGRAM - A graphic processing apparatus includes a chunk assignment unit which assigns a block in which a maximum N number of polygons are located, out of a plurality of polygons drawn in a frame buffer which is divided into a plurality of blocks, to a maximum M number of chunk buffers; a chunk generation unit which generates pixel data of a polygon located in a block assigned to the chunk buffer, out of the N number of polygons, and writes the pixel data to the chunk buffer; and a chunk writing unit which writes the pixel data written in the chunk buffer to the frame buffer, wherein a processing phase, including processing by the chunk assignment unit, processing by the chunk generation unit, and processing by the chunk writing unit, is repeatedly executed for the plurality of polygons. | 03-15-2012 |
| 20120061847 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed. | 03-15-2012 |
| 20120060136 | Design supporting method, design supporting device, computer product, and semiconductor integrated circuit - A method executed by a computer and for designing a semiconductor integrated circuit, includes detecting, from layout data of a semiconductor integrated circuit, a clock path that propagates the clock signal and of which clock buffers are single-gate inverting clock buffers; selecting sequentially data holding elements connected to the detected clock path; identifying an input clock buffer of each selected data holding element; determining whether the identified clock buffer outputs the clock signal according to non-inverting logic or inverting logic, based on the number of gates from the clock source to the clock buffer; replacing, based on a determination result, the data holding element with a first data holding element that takes in data in synchronization with a rising edge of the clock signal or with a second data holding element that takes in data in synchronization with a falling edge of the clock signal; and outputting a replacement result. | 03-08-2012 |
| 20120058610 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess. | 03-08-2012 |
| 20120057420 | SEMICONDUCTOR MEMORY AND METHOD FOR TESTING THE SAME - A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command in response to a control signal from the outside. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads. | 03-08-2012 |
| 20120056610 | SWITCHING REGULATOR - A switching regulator: first switching element and second switching element; a logic unit which outputs to the load the output voltage converted from the input voltage to the constant voltage, by causing the first switching element and the second switching element to perform a switching operation; an error amplifier which outputs first signal indicating an error between the output voltage and the first reference voltage; first comparator which inputs the first signal and second signal indicating an output voltage that is proportional to load current flowing in the load, and outputs to the logic unit control signal causing the logic unit to perform the switching operation based on the first signal and the second signal; and a correction unit which is connected to an input side of the error amplifier, and corrects an input voltage of the error amplifier to reduce the input voltage to a certain value or lower. | 03-08-2012 |
| 20120056322 | SEMICONDUCTOR DEVICE WITH PADS OF ENHANCED MOISTURE BLOCKING ABILITY - A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film. | 03-08-2012 |
| 20120056300 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME - Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm. | 03-08-2012 |
| 20120045878 | MANUFACTURE OF SEMICONDUCTOR DEVICE WITH STRESS STRUCTURE - A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers. | 02-23-2012 |
| 20120045875 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask. | 02-23-2012 |
| 20120044003 | SKEW ADJUSTMENT CIRCUIT AND SKEW ADJUSTMENT METHOD - A skew adjustment circuit, provided in an integrated circuit device having a plurality of signal lines transmitting a plurality of signals respectively, and a plurality of buffer circuits to which a plurality of signals transmitted through the signal lines are respectively input, has: a plurality of delay circuits, respectively provided in stages preceding the buffer circuits; a monitoring circuit monitoring changes in the signals of the plurality of signal lines; and a delay adjustment circuit, which decides delay amounts for the plurality of delay circuits based on a monitoring result output of the monitoring circuit, and sets the delay amounts in the plurality of delay circuits. The monitoring circuit detects, as the monitoring result, a number of signal changes in the signal lines in which a signal change occurs in a monitoring period, and the delay adjustment circuit decides the delay amounts based on the number of signal changes. | 02-23-2012 |
| 20120043613 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes. | 02-23-2012 |
| 20120042380 | SECURE MODULE AND INFORMATION PROCESSING APPARATUS - A secure module includes a generating unit that executes generation processing of generating a scanning program that causes scan processing, which generates unique code for a program under test, to be executed at a connected device and further executes update processing of randomly updating contents of the scanning program; a storage device storing therein the unique code for the program under test; and an authenticating unit that if the scanning program is executed by the connected device and executed with respect to the program under test stored at a designated storage area in the connected device, authenticates validity of the program under test stored at the designated storage area, based on the unique code stored in the storage device and execution results of the scanning program executed at the connected device. | 02-16-2012 |
| 20120040502 | MANUFACTURE OF SEMICONDUCTOR DEVICE WITH STRESS STRUCTURE - A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers. | 02-16-2012 |
| 20120039426 | CLOCK DATA RECOVERY CIRCUIT AND CLOCK DATA RECOVERY METHOD - A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data. | 02-16-2012 |
| 20120038794 | IMAGE PROCESSING APPARATUS, IMAGING APPARATUS AND IMAGE PROCESSING METHOD - An image processing apparatus includes: a computing unit which determines a first difference value between brightness of a first image data and brightness of a second image data in an overlap area of the first image data including a first brightness characteristic with the second image data having a peripheral area at the center of the first image data and including a second brightness characteristic; and a generating unit which generates a brightness correction parameter for the first image data corresponding to the first difference value. | 02-16-2012 |
| 20120038386 | LATCH CIRCUIT - A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals. | 02-16-2012 |
| 20120038011 | MAGNETIC TUNNELING JUNCTION DEVICE AND ITS MANUFACTURING METHOD - A magnetic pinned layer is formed over a substrate. An insulating film is formed over the magnetic pinned layer. A recess is formed in and through the insulating film. A tunneling insulating film is formed over a bottom of the recess. A first magnetic free layer is formed over the bottom of the recess via the tunneling insulating film. A second magnetic free layer is formed over the insulating film and made of a same material as the first magnetic free layer. A non-magnetic film is formed on sidewalls of the recess, extending from the first magnetic free layer to the second magnetic free layer and made of oxide of the material of the first magnetic free layer. An upper electrode is disposed over the first magnetic free layer, non-magnetic film and second magnetic free layer, and electrically connected to the first magnetic free layer and second magnetic free layer. | 02-16-2012 |
| 20120038004 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first insulating film is formed above a semiconductor substrate with a device isolation insulating film defining a device region, a gate electrode and source/drain region formed. The first insulating film is etched, leaving the first insulating film in a recess formed in an edge of the device isolation insulating film. A second insulating film applying a stress to the semiconductor substrate is formed after etching the first insulating film. | 02-16-2012 |
| 20120038001 | P-CHANNEL MOS TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions. | 02-16-2012 |
| 20120038000 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a first stopper film and a second stopper film over a first stress film; etching, with a first mask covering a first region and with the first stopper film, the second stopper film in a second region while side-etching the second stopper film in a part of the first region near the second region; forming a second stress film whose etching characteristic is different from the second stopper film; etching, with a second mask covering the second region and having an end face located over the second stopper film and with the second stopper film, the second stress film so that a part of the second stress film overlaps a part of the first stress film and a part of the second stopper film; and forming a contact hole down to the gate interconnect. | 02-16-2012 |
| 20120036490 | INFORMATION PROCESSING DEVICE AND DESIGN SUPPORTING METHOD - An information processing device comprises, a physical property value generation unit to generate a plurality of physical property values for changing signal propagation time of a target path including a plurality of circuit elements within a predetermined fluctuation range, an element delay calculation unit to calculate delay time of each of signals passing through the circuit element in accordance with each of the generated physical property values and a propagation time calculation unit to calculate the signal propagation time of the target path on the basis of the delay time of the signals. | 02-09-2012 |
| 20120034751 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region. | 02-09-2012 |
| 20120034712 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including a ferroelectric capacitor formed over a semiconductor substrate, wherein the ferroelectric capacitor including a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, and the upper electrode including a first conductive film formed of a first conductive noble metal oxide, and a second conductive film formed of a metal nitride compound formed on the first conductive film. | 02-09-2012 |
| 20120032300 | METHOD OF MANUFACTURING A FERROELECTRIC CAPACITOR AND A FERROELECTRIC CAPACITOR - A lower electrode film is formed above a substrate. A ferroelectric film is formed above the lower electrode film. An amorphous intermediate film of a perovskite-type conductive oxide is formed above the ferroelectric film. A first upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the intermediate film. The intermediate film is crystallized by carrying out a first heat treatment in an atmosphere containing an oxidizing gas after the formation of the first upper electrode film. After the first heat treatment, a second upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the first upper electrode film, at a temperature lower than the growth temperature for the first upper electrode film. | 02-09-2012 |
| 20120032299 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method. | 02-09-2012 |
| 20120032281 | SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device production method includes: forming an insulating film on a semiconductor substrate, forming a concave portion in the insulating film, forming a gate insulating film at bottom of the concave portion, the bottom being on the semiconductor substrate; covering an inner wall surface of the concave portion and a top face of the insulating film with a first gate electrode film that is made of an electrically conductive material containing a first metal; covering the first gate electrode film with a covering film of a material having a second melting point higher than a first melting point of the electrically conductive material, leaving part of the side face of the concave portion uncovered; and performing heat treatment following the covering film formation to allow the first gate electrode film to reflow. | 02-09-2012 |
| 20120032272 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, SRAM, AND METHOD FOR PRODUCING Dt-MOS TRANSISTOR - A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well. | 02-09-2012 |
| 20120030527 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. | 02-02-2012 |
| 20120028374 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A ferroelectric capacitor provided with a ferroelectric film ( | 02-02-2012 |
| 20120025797 | CONTROL CIRCUIT FOR POWER SUPPLY - A control circuit for controlling a power supply including a first switch and a second switch coupled in series between a first potential and a second potential. The control circuit includes a detection circuit that detects a magnitude relation of a voltage value at a node between the first and second switches and a reference value during a period in which the first switch and the second switch are inactivated. The detection circuit generates a control signal corresponding to the magnitude relation. A regulation circuit regulates a switching timing of the second switch in response to the control signal to decrease a difference between the voltage value at the node and the reference value. | 02-02-2012 |
| 20120025290 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole. | 02-02-2012 |
| 20120021593 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes implanting indium into a first region of a semiconductor substrate; forming a first gate insulation film having a first film thickness in the first region and a second region different from the first region after the implanting; removing the first gate insulation film from the first region; applying heat treatment to the semiconductor substrate after the forming; and forming a second gate insulation film having a second film thickness on the first region after the applying. In the method, a temperature falling rate of the heat treatment in the applying is 20° C. per second or higher. | 01-26-2012 |
| 20120019186 | METHOD OF DETECTING AN OPERATING CONDITION OF AN ELECTRIC STEPPER MOTOR - An electrical stepper motor comprises a magnetical rotor and at least two electromagnetical driving coils for causing rotation of the rotator. A method of detecting an operating condition of the as e.g. a stall state of the electrical stepper motor comprises the steps of connecting one contact pin (P, M) of at least one of the electromagnetical driving coils via a high-impedance resistor (R | 01-26-2012 |
| 20120016619 | DELAY FAULT TEST QUALITY CALCULATION APPARATUS, DELAY FAULT TEST QUALITY CALCULATION METHOD, AND DELAY FAULT TEST PATTERN GENERATION APPARATUS - A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit. | 01-19-2012 |
| 20120009752 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface. | 01-12-2012 |
| 20120009750 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer. | 01-12-2012 |
| 20120007147 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor film having a heterojunction structure, for example a semiconductor film including a SiGe layer and a Si layer formed on the SiGe layer, impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer becomes higher than that in the upper, Si layer by exploiting the fact that there is a difference between the SiGe layer and the Si layer in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film | 01-12-2012 |
| 20120005883 | METHOD OF ATTACHING ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT ATTACHING TOOL - An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket. | 01-12-2012 |
| 20120005875 | METHOD OF SEMICONDUCTOR DEVICE PROTECTION - A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device. | 01-12-2012 |
| 20120005636 | METHOD FOR MANUFACTURING A PHOTOMASK - A method for manufacturing a photomask based on design data includes the steps of forming a figure element group including a figure element in a layout pattern on the photomask and a figure element affecting the figure element due to the optical proximity effect, adding identical identification data to a data group indicating an identical figure element group, estimating an influence of the optical proximity effect on the figure element group, generating correction data indicating a corrected figure element in which the influence of the optical proximity effect is compensated for at the time of exposure, creating figure data by associating data having the identical identification data with correction data having the identical identification data, and forming a mask pattern on the photomask using figure data. Thus, the computation time for correction of the layout can be reduced, thereby reducing the production time of the photomask. | 01-05-2012 |
| 20120001664 | CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME - A clock divider circuit has a plurality of dividers for which dividing ratios are settable, a preset register group that stores the dividing ratios set for the plurality of dividers, and a selector that selects a single preset register within the preset register group, and imparts the dividing ratios stored in the selected preset register to the plurality of dividers. | 01-05-2012 |
| 20120001344 | SEMICONDUCTOR DEVICE MANUFACTURE METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; etching the insulating film to form a dummy groove having a first depth, a wiring groove having a second depth deeper than the first depth, and a via hole to be disposed on a bottom of the wiring groove; depositing a conductive material in the dummy groove, wiring groove and via hole and above the insulating film; and polishing and removing the conductive material above the insulating film. | 01-05-2012 |
| 20120001265 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WHICH A PLURALITY OF TYPES OF TRANSISTORS ARE MOUNTED - A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping. | 01-05-2012 |
| 20110320987 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, DATA GENERATING APPARATUS, DATA GENERATING METHOD AND RECORDING MEDIUM READABLE BY COMPUTER RECORDED WITH DATA GENERATING PROGRAM - A semiconductor manufacturing method comprising, a data generating process including, acquiring a simulation light pattern that simulates a shape of a light exposure pattern formed on a substrate on the basis of design data of a semiconductor device, acquiring a simulation electron beam exposure pattern that simulates a shape of an electron beam exposure pattern formed by an electron beam exposure on the substrate on the basis of the design data, extracting difference information representing a shape difference portion between the simulation light pattern and the simulation electron beam exposure pattern, acquiring changed design data for modifying shape by changing the design data in accordance with the difference information, conducting the electron beam exposure on the substrate by use of the changed design data for modifying the shape. | 12-29-2011 |
| 20110320658 | INFORMATION PROCESSING SYSTEM - An interrupt control circuit asserts a remap signal in response to an interrupt request from a low-speed slave to a processor, and reads information stored in an information register of the low-speed slave. The interrupt control circuit writes the read information into a buffer exclusively for interrupt processing. A switch circuit supplies a read access request which is a request from the processor to the information register to the low-speed slave during negation of the remap signal, and supplies the read access request to the buffer via the interrupt control circuit in order to read the information from the buffer during assertion of the remap signal. By accessing to the buffer exclusively for the interrupt processing instead of the information register in response to the read access request from the processor, the interrupt processing time may be shortened. | 12-29-2011 |
| 20110320160 | INTEGRATED CIRCUIT, SIMULATION APPARATUS AND SIMULATION METHOD - The disclosed device performs a control of generating a test pattern for the delay test of LSI. The input pattern control circuit counts a cycle number of an input pattern supplied to a test object circuit, and stops supply of the input pattern to the test object circuit when the cycle number of the input pattern coincides with a certain count number. The scan control circuit receives a control signal from the input pattern control circuit, and supplies a scan shift signal to the test object circuit to shift a scan chain in the test object circuit. | 12-29-2011 |
| 20110317507 | SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY - A semiconductor memory includes memory cells; word lines coupled to the memory cells; plate lines coupled to the memory cells; a selector that selects a first address signal in a first period and select a second address ,signal in a second period; a decode circuit that sequentially decodes the first and the second address signals selected by the selector, sequentially generates decode address signals based on the decoded first and second address signals, and sequentially activates the generated decode address signals; and a driver circuit that drives the word lines in accordance with the decode address signals activated based on the first address signal and drives the plate lines in accordance with the decode address signals activated based on the second address signal. | 12-29-2011 |
| 20110317467 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a memory element including a stack structure stacking an insulator film and a metal film or a metal compound film; and a transistor including a gate structure having an identical stack structure as that of the memory element. | 12-29-2011 |
| 20110316981 | PROCESSOR - A processor includes: an imaging control unit which causes an imaging unit for capturing an image with changing a focused object distance, to change the focused object distance with a first change width in the case of a first focused object distance, and to change the focused object distance with a second change width that is smaller than the first change width in the case of a second focused object distance that is shorter than the first focused object distance; and an image processing unit which extracts focused object image data from captured image data for each of the focused object distances, and generates image data by shifting the extracted object image data by parallax amounts corresponding to the respective focused object distances, and by synthesizing the extracted object image data. | 12-29-2011 |
| 20110316616 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR CONTROLLING POWER SUPPLY - A semiconductor integrated circuit includes a plurality of circuit regions, at least one power source switch that switches between two states of supplying power or not supplying power to at least one of the plurality of circuit regions, a power source control circuit that controls the at least one power source switch, a clamp scan chain having a plurality of flip-flops to which an output from the at least one circuit region to another region is input, and a clamp data control circuit that sets the plurality of flip-flops of the clamp scan chain to a predetermined output state. | 12-29-2011 |
| 20110316515 | OSCILLATION CIRCUIT - An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency. | 12-29-2011 |
| 20110316131 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 12-29-2011 |
| 20110316087 | MOS TRANSISTOR, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode. The accumulated stress is the tensile stress if the conductivity type is an n-type, and is a compressive stress if the conductivity type is a p-type. | 12-29-2011 |
| 20110314434 | COMPUTER PRODUCT, APPARATUS, AND METHOD FOR SUPPORTING DESIGN - A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction. | 12-22-2011 |
| 20110314433 | COMPUTER PRODUCT, APPARATUS, AND METHOD FOR SUPPORTING DESIGN - A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction. | 12-22-2011 |
| 20110314308 | INTEGRATED CIRCUIT DEVICE AND CONTROL METHOD FOR ELECTROSTATIC PROTECTION CIRCUIT THEREOF - The integrated circuit device includes: an electrostatic protection circuit that is provided between first and second power supply lines coupled to external terminals respectively, and forms a current pathway between the first and second power supply lines during a given period in response to an increase in a voltage between the first and second power supply lines; and a power supply generating circuit that performs power supply control based on a voltage of the first power supply line and generates a control signal in accordance with a switching timing of the power supply control. And, the electrostatic protection circuit includes an adjustment circuit for shortening the given period in response to the control signal. | 12-22-2011 |
| 20110314197 | DATA PROCESSING SYSTEM - Each of a plurality of master devices outputs a speed grade signal indicating a data transfer speed with a data transfer request. An arbiter arbitrates transfer requests and speed grade signals from the plurality of master devices. A clock enable generation circuit generates a clock enable signal with a varying ratio of a valid level according to the speed grade signal arbitrated by the arbiter. A slave device operates upon receiving a clock signal when the clock enable signal is at the valid level, and transfers data according to the transfer request arbitrated by the arbiter. Accordingly, the frequency of the clock signal which causes the slave device to operate may be changed for each transfer request, and a fine control of the power of the slave device may be easily performed. As a result, power consumption of the data processing system may be finely controlled. | 12-22-2011 |
| 20110312191 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming an insulation film containing silicon, oxygen and carbon over a semiconductor substrate by chemical vapor deposition; making UV cure on the insulation film being heated at a temperature of 350° C. or below after the forming the insulation film; and making helium plasma processing on the insulation film after the UV cure. | 12-22-2011 |
| 20110312186 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop | 12-22-2011 |
| 20110312154 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive pattern is formed over the isolation insulating film, and an insulating film is formed over the isolation insulating film, the conductive pattern and the side face of the conductive pattern, and the side face of the conductive pattern comprises a notch. | 12-22-2011 |
| 20110309862 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit including: a first data hold circuit configured to hold an input signal from a first input terminal; a second data hold circuit configured to hold the input signal from the first input terminal and an input signal from a second input terminal; a gate circuit configured to input an output signal of the first data hold circuit and an output signal of the second data hold circuit and to output a signal corresponding to the output signals of the first and second data hold circuits when the output signals of the first and second data hold circuits are the same as each other; and a third data hold circuit configured to hold the output signal of either the gate circuit or the second data hold circuit, and outputs the output signal to an output terminal | 12-22-2011 |
| 20110309861 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor included in a latch circuit, a second transistor that is included in the latch circuit and is formed in a well in which the first transistor is formed, the second transistor having a conduction type identical to that of the first transistor, and a well contact that is provided between the first transistor and the second transistor and connects a power supply to the well. | 12-22-2011 |
| 20110307713 | PROCESSOR AND PROCESSOR SYSTEM - In a processor including a CPU core executing instruction codes and a cache memory part having plural ways, encryption counter data encrypting and decrypting data input/output for the core in a common key encryption system are stored at one way among the plural ways, an XOR operation is performed between the encryption counter data and the input/output data, and the common key encryption process generating the encryption counter data is not executed every time when the data is encrypted or decrypted, to thereby enable high-speed memory access without sacrificing security. | 12-15-2011 |
| 20110307637 | DATA TRANSFER DEVICE AND DATA TRANSFER METHOD - A data transfer device includes a data buffer, an odd number flag, and a control unit. The data buffer holds an even number of data blocks from a data transfer controller. The odd number flag is set when the number of data blocks to be transferred to a receiving device is odd. The control unit transfers an even number of data blocks to the receiving device for each data transfer cycle with respect to the receiving device, and transfers one data block to the receiving device in a last transfer cycle when the odd number flag is set. Thus, also when the data transfer controller which transfers data in a unit of an even number of data blocks is used, not only an even number of data blocks but an odd number of data blocks may be transferred to the receiving device. | 12-15-2011 |
| 20110304007 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam. | 12-15-2011 |
| 20110303248 | Cleaning apparatus of semiconductor substrate and method of manufacturing semiconductor device - After a liquid chemical treatment is finished, in parallel with a washing away treatment and/or a drying treatment, by spraying from a nozzle for a cleaning liquid supplied by a cleaning line to an outer surface of a nozzle for a liquid chemical, crystals and the like of components of the liquid chemical adhered on the outer surface of the nozzle are removed. In the cleaning treatment, a spraying time of the cleaning liquid is five seconds to ten seconds. In addition, the components of the cleaning liquid is not specifically limited, however, since ammonium phosphate tends to be solved in purified water, if a liquid chemical containing ammonium phosphate is used, it is preferable to use purified water as the cleaning liquid. Depending on the components and the like of the liquid chemical, a solution that can solve the crystals and the like may be used in stead. | 12-15-2011 |
| 20110302456 | SEMICONDUCTOR INTEGRATED CIRCUIT, OPERATING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND DEBUG SYSTEM - A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information, A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced. | 12-08-2011 |
| 20110299585 | RECEIVING DEVICE AND RECEIVING METHOD - To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient. | 12-08-2011 |
| 20110299583 | RECEIVING DEVICE AND RECEIVING METHOD - To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient. | 12-08-2011 |
| 20110298532 | INTEGRATED CIRCUIT, INTEGRATED CIRCUIT DESIGN DEVICE AND INTEGRATED CIRCUIT DESIGN METHOD - The disclosed integrated circuit includes a first and a second power supply wirings, a flip-flop circuit, and a switch element. The first and the second power supply wirings are connected to the common power supplies. The flip-flop circuit is required to hold the stored data even when the voltage supply from the power supplies to the integrated circuit is stopped. The flip-flop circuit is connected to the first power supply wiring. The switch element is a transistor, for example, and switches whether or not the voltage is supplied from the power supplies. The switch element is provided on the second power supply wiring. | 12-08-2011 |
| 20110298091 | SEMICONDUCTOR DEVICE HAVING CAPACITORS - A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 μm | 12-08-2011 |
| 20110294261 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode. | 12-01-2011 |
| 20110291204 | SEMICONDUCTOR DEVICE HAVING STI WITH NITRIDE LINER AND UV LIGHT SHIELDING FILM - A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of a silicon nitride layer formed on the first liner layer; an element isolation region of an insulator formed on the second liner layer; a p-channel MOS transistor formed in and on one of the active regions; a contact etch stopper layer of a silicon nitride layer not having a ultraviolet shielding ability, formed above the silicon substrate, and covering the p-channel MOS transistor; and a light shielding film of a silicon nitride layer having the ultraviolet shielding ability and formed above the contact etch stopper layer. | 12-01-2011 |
| 20110289298 | SEMICONDUCTOR CIRCUIT AND DESIGNING APPARATUS - A semiconductor circuit includes a memory which stores data; a processing device which executes a program, writes argument data of a function of the program into the memory referring to an address stored in a stack pointer, when a value of a program counter, which indicates an address of the program under execution, reaches a hardware accelerator starting address, and outputs the address stored in the stack pointer; and a hardware accelerator which receives the address of the stack pointer from the processing device, when a value of the program counter of the processing device reaches the hardware accelerator starting address, reads the argument data of the function from the memory referring to the address stored in the stack pointer, and executes the function implemented in hardware using the argument data. | 11-24-2011 |
| 20110287594 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A polysilicon film to be a resistor element is formed on a resistor element formation region of a semiconductor substrate while a polysilicon gate and high concentration impurity regions are formed on a transistor formation region. Thereafter, an insulating film is formed on the entire surface of the semiconductor substrate. Then, a photoresist film is formed to cover the transistor formation region, and a conductive impurity is ion-implanted into the polysilicon film. Next, the photoresist film is removed by asking. | 11-24-2011 |
| 20110286277 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors. | 11-24-2011 |
| 20110286257 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors. | 11-24-2011 |
| 20110280072 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder. | 11-17-2011 |
| 20110279167 | INPUT/OUTPUT CIRCUIT AND SYSTEM - An input/output circuit has a first load having one end coupled to a first standard voltage line, a first MOS transistor having a drain electrode coupled to another end of the first load, a second load having one end coupled to the first standard voltage line, a second MOS transistor having a drain electrode coupled to another end of the second load, a third MOS transistor having a source electrode each of which is coupled to source electrodes of the first and second MOS transistors, a first constant-current source coupled between the source electrode of the first MOS transistor and a second standard voltage line, and a second constant-current source coupled between the source electrode of the second MOS transistor and the second standard voltage line. The circuit size is reduced by transmitting a differential signal or a single-ended signal using a single input/output circuit. | 11-17-2011 |
| 20110278723 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals. | 11-17-2011 |
| 20110278715 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point. | 11-17-2011 |
| 20110278708 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a die stage on which a semiconductor element is mounted, a plurality of connection terminals radially arranged around the die stage, and a plurality of wire connection portions which are each provided at a leading end portion on the die stage side of one of the plurality of connection terminals. Moreover, a fixing tape is attached to back surface sides of the wire connection portions and fixes the plurality of wire connection portions all together. Adjacent two of the wire connection portions are staggered in a longitudinal direction of the corresponding connection terminals, and a portion of the connection terminal running along the wire connection portion of the adjacent connection terminal is formed to be narrower and thinner than the wire connection portion. | 11-17-2011 |
| 20110278659 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first area; removing the oxidation film over the first device region, forming a first gate insulating film over the first device region, removing the oxidation film over the second device region, forming a second gate insulating film over the second device region, forming a first gate electrode over the first gate insulating film, forming a second gate electrode over the second gate insulating film, forming first source and drain regions in the first device region at both sides of the first gate electrode, and forming second source and drain regions in the second device region at both sides of the second gate electrode. | 11-17-2011 |
| 20110275225 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a transistor over a semiconductor substrate; forming a first silicon nitride film covering the transistor over the semiconductor substrate; supplying a NH | 11-10-2011 |
| 20110273156 | POWER REGULATOR, CONTROL CIRCUIT, AND METHOD FOR CONTROLLING POWER REGULATOR - A power regulator includes an output terminal, which outputs an output voltage, and a converter unit including a switch circuit, which is supplied with an input voltage, and a coil, which is coupled between the switch circuit and the output terminal. A control circuit compares a feedback voltage, which is in accordance with the output voltage, and a reference voltage and controls the switch circuit in response to a switching timing that is in accordance with the comparison result. The control circuit includes a voltage adding circuit, which adds a ramp voltage to the feedback voltage or the reference voltage, and a timing adjustment circuit, which is coupled to the voltage adding circuit to delay a timing for adding the ramp voltage with the voltage adding circuit from a switching timing of the switch circuit. | 11-10-2011 |
| 20110272770 | METHOD FOR MANUFACTURING MAGNETIC STORAGE DEVICE, AND MAGNETIC STORAGE DEVICE - A lower conductive film is formed over a substrate. A first insulating film is formed in the lower conductive film. An opening which reaches the lower conductive film is formed in the first insulating film. An MTJ multilayer film having a magnetization free layer, a tunnel barrier layer and a magnetization fixed layer is deposited over the lower conductive film in the opening and over the first insulating film. An upper electrode is formed over the MTJ multilayer film. By removing the portion of the MTJ multilayer film deposited over the first insulating film, an MTJ device composed of the portion of the MTJ multilayer film which has remained in the opening is formed. A lower electrode composed of the lower conductive film is formed under the MTJ device by removing at least a part of the first insulating film, and a part of the lower conductive film. | 11-10-2011 |
| 20110272742 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFCTURING SAME - A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer. | 11-10-2011 |
| 20110270427 | DIGITAL/ANALOG CONVERTOR AND DIGITAL AUDIO PROCESSING CIRCUIT ADOPTING THE SAME - A digital analog convertor has a modulator which modulates a digital signal to generate a pulse signal having a pulse density corresponding to a digital value of the digital signal; a first RZ conversion circuit which RZ-converts the pulse signal based on a first clock signal to generate a first RZ pulse signal; a first integration circuit which integrates the first RZ pulse signal to output a first analog signal; a second RZ conversion circuit which RZ-converts a first level signal having a first level of the pulse signal based on the first clock signal to generate a second RZ pulse signal; a second integration circuit which integrates the second RZ pulse signal to output a second analog signal; and a clock duty control circuit which controls a duty ratio of the first clock signal so that the second analog signal approaches a given reference level. | 11-03-2011 |
| 20110258517 | DATA WRITING METHOD AND SYSTEM - A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased. | 10-20-2011 |
| 20110255347 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell. | 10-20-2011 |
| 20110254574 | PROBER, TESTING APPARATUS, AND METHOD OF INSPECTING SEMICONDUCTOR CHIP - A prober includes a probe card provided with a support board and a probe attached to the support board, a stage on which a measurement wafer is mounted, a camera provided over the probe card to observe an electrode pad of a first semiconductor chip formed on the measurement wafer, and a stage moving unit for moving the position of the stage relative to the probe card. | 10-20-2011 |
| 20110254106 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a gate insulation film formed over a semiconductor substrate; a cap film formed over the gate insulation film; a silicon oxide film formed over the cap film; a metal gate electrode formed over the silicon oxide film; and source/drain diffused layers formed in the semiconductor substrate on both sides of the metal gate electrode. | 10-20-2011 |
| 20110254074 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode. | 10-20-2011 |
| 20110252391 | INTEGRATED CIRCUIT MANUFACTURING METHOD, DESIGN METHOD AND PROGRAM - An integrated circuit manufacturing method comprising: calculating a threshold value from a value of a parameter which characterizes at least a part of a design pattern shape of a transistor on the target path; calculating a difference between the calculated threshold value and a target threshold value; calculating a change quantity of a gate length corresponding to the difference between the threshold value and the target threshold value according to the functional relation between the threshold value of the transistor and the gate length, which is determined based on the empirical value or the experimental value; reducing, by the change quantity, the gate length of the transistor on the target path; and manufacturing an integrated circuit on the basis of design information of the circuit including the transistor of which the gate length is changed. | 10-13-2011 |
| 20110250748 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, comprising, forming a first gate electrode in a first region of a semiconductor substrate and forming a second gate electrode in a second region of the semiconductor substrate, forming a first sidewall along a lateral wall of the first gate electrode and forming a second sidewall along a lateral wall of the second gate electrode, forming an oxide film to cover the semiconductor substrate, the first gate electrode, the second gate electrode, the first sidewall and the second sidewall, forming a resist above the oxide film to cover the first region, removing the oxide film in the second region by etching the oxide film with the resist serving as a mask, removing the resist, and executing a plasma process by using a gas containing chlorine with respect to the semiconductor substrate and the oxide film in the first region. | 10-13-2011 |
| 20110246747 | RECONFIGURABLE CIRCUIT USING VALID SIGNALS AND METHOD OF OPERATING RECONFIGURABLE CIRCUIT - A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed. | 10-06-2011 |
| 20110244677 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A method of manufacturing a semiconductor device includes: forming a first conductive film on a substrate; forming an insulating film to cover the conductive film; etching the insulating film to form an opening portion to expose at least a portion of the first conductive film in the insulating film; irradiating the opening portion with ultraviolet rays in a reduction gas atmosphere; forming a barrier metal film in the opening portion; and forming a second conductive film on the barrier metal film. | 10-06-2011 |
| 20110244650 | SEMICONDUCTOR DEVICE WITH STI AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area. | 10-06-2011 |
| 20110243216 | COMMUNICATION APPARATUS AND CONTROL METHOD THEREOF - A communication apparatus which receives output voltage of a direct current voltage converter, the communication apparatus includes: a modulating/demodulating circuit which demodulates a reception signal from a high-frequency transmitting/receiving circuit, modulates a transmission signal, and outputs the transmission signal to the high-frequency transmitting/receiving circuit; a communication control circuit which inputs reception data and outputs transmission data to and from the modulating/demodulating circuit and performs communication control in accordance with an reception period and a transmission period; and a direct current voltage converter control circuit which switches a direct current voltage converter, which outputs an output voltage to the communication apparatus, to pulse width modulation control in the reception period and transmission period, and switches the direct current voltage converter to pulse frequency modulation control in at least a partial period excluding the reception period and the transmission period. | 10-06-2011 |
| 20110242896 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor device includes a booster circuit and a detector. The booster circuit is configured to boost an input voltage and output an output voltage, and the detector is configured to output the output voltage, which is output from the booster circuit, and control the booster circuit to generate a plurality of different voltages in accordance with an operating mode. | 10-06-2011 |
| 20110241753 | MIXER CIRCUIT AND METHOD FOR ADJUSTING COMMON VOLTAGE OF MIXER CIRCUIT - A mixer circuit includes: a mixer circuit including a first transistor pair to output a first differential input signal and a second transistor pair to output a second differential input signal by inversing the first differential signal; a local signal supply circuit to supply a pair of local signals to gates of the first transistor pair and the second transistor pair; an operational amplifier including an input pair coupled to an output pair of the mixer circuit and an output pair coupled to the input pair via feedback resistors, the operational amplifier to amplify the first differential input signal and output a differential output signal; a common mode feedback circuit to control a center voltage of the differential output signal so that the center voltage maintains a common voltage; and a common voltage generator circuit to generate the common voltage according to an amplitude of the local signal. | 10-06-2011 |
| 20110241632 | POWER SOURCE APPARATUS, CONTROL CIRCUIT, AND METHOD OF CONTROLLING POWER SOURCE APPARATUS - A power source apparatus includes: a switch circuit to receive an input voltage; a control circuit to switch the switch circuit from a second state to a first state at a timing corresponding to a comparison result between a feedback voltage generated based on a first voltage corresponding to an output voltage and a reference voltage generated based on a standard voltage set in accordance with the output voltage; and a voltage generation circuit to add a compensation voltage generated by voltage-converting a time period in which the switch circuit switches from the second state to the first state to one of the first voltage and the standard voltage, to generate the feedback voltage, to add a slope voltage which changes at a slope to one of the first voltage and the standard voltage, and to generate the reference voltage. | 10-06-2011 |
| 20110241211 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening. | 10-06-2011 |
| 20110239095 | Receiving device and receiving method - To provide a receiving device and a receiving method which achieve iterative decoding regarding concatenated codes containing a convolutional code while suppressing increase in circuit scale, a decoder and an error correcting part iteratively perform decoding and error correction corresponding to a convolutional code on soft-decision inputs corresponding to the received signal sequence. Depending on whether a decoding result matches error corrected decoded data obtained in previous processing or not, penalties are calculated corresponding to branches transiting with the respective decoded results, and a branch metric is calculated by reflecting the calculated penalties as to decrease likelihood ratio of each of the branches to which the penalties are to be added. The obtained branch metric is input to a decoder, thereby reflecting the penalty corresponding to the decoding result. | 09-29-2011 |
| 20110238896 | DATA-PROCESSING METHOD, PROGRAM, AND SYSTEM - A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and adding a first identifier of the first data to the second sector by a memory control circuit when transferring data in the first sector to the second sector, the plurality of sectors including the first sector and the second sector. | 09-29-2011 |
| 20110234433 | A/D CONVERTER - An A/D converter includes a capacitive DAC configured to perform conversion of high-order bits by receiving a differential signal, a resistive DAC configured to perform conversion of low-order bits, a resistive correction DAC configured to operate to correct the capacitive DAC, and a comparator. The capacitive DAC includes a positive-side capacitive DAC and a negative-side capacitive DAC operating in a complementary fashion, and the comparator, which includes a plurality of differential circuits, is configured to compare output potentials of the positive-side capacitive DAC and the negative-side capacitive DAC. The positive-side capacitive DAC and the negative-side capacitive DAC include first capacitive elements each formed from interconnect layers excluding an uppermost interconnect layer, and the comparator includes second capacitive elements each provided between adjacent ones of the differential circuits and formed from interconnect layers including the uppermost interconnect layer. | 09-29-2011 |
| 20110234275 | PLL CIRCUIT - In the PLL circuit including a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator, the loop band after the locking can be expanded in such a manner that, when the phase difference between a reference clock signal and a feedback clock signal is larger than a threshold value, an output current corresponding to the phase difference is outputted by reducing the change of the output current per unit amount of the phase difference, and that, when the phase difference is at most the threshold value, the output current corresponding to the phase difference is outputted by increasing the change of the output current per unit amount of the phase difference. | 09-29-2011 |
| 20110233738 | SEMICONDUCTOR DEVICE AND LEAD FRAME - A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad. | 09-29-2011 |
| 20110233735 | SEMICONDUCTOR WAFER AND ITS MANUFACTURE METHOD, AND SEMICONDUCTOR CHIP - A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer. | 09-29-2011 |
| 20110233687 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device manufacturing method includes forming a channel dope layer having a first electric conductive-type inside of a semiconductor substrate, the channel dope layer being formed in a region except for a drain impurity region where dopant impurities for forming a low-concentration drain region are introduced, and the channel dope layer being separated from the drain impurity region; forming a gate electrode on the semiconductor substrate via a gate insulating film; and forming a low-concentration source region inside of the semiconductor substrate on a first side of the gate electrode, and forming a low-concentration drain region in the drain impurity region of the semiconductor substrate on a second side of the gate electrode, by introducing second electric conductive dopant impurities inside of the semiconductor substrate with the gate electrode as a mask. | 09-29-2011 |
| 20110231173 | SIMULATION METHOD, SIMULATION DEVICE, PROGRAM, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - Disclosed is a simulation method for simulating an operation of a device. The simulation method includes specifying, by a computer, a boundary between a non-defective status and a defective status of a product in design space with a design parameter as an origin. The boundary is specified according to a search using a search indicator defined based on an operating state different from an operating state of a determination indicator that determines the non-defective status and the defective status of the operation. | 09-22-2011 |
| 20110227636 | REFERENCE VOLTAGE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A reference voltage circuit includes a first amplifier configured to output a reference voltage, a second amplifier coupled to the first amplifier, an offset adjustment voltage generation circuit, a first load device and a first pn junction device, and second and third load devices and a second pn junction device. The offset adjustment voltage generation circuit is configured to generate a voltage which is input to the third and fourth input terminals of the second amplifier, and reduce an offset voltage between the first and second input terminals of the first amplifier through the second amplifier. The first input terminal is coupled to a coupling node of the first load device and the first pn junction device, and the second input terminal is coupled to a coupling node of the second load device and the third load device. | 09-22-2011 |
| 20110227604 | RECEIVING CIRCUIT AND METHODS FOR CONTROLLING AND TESTING THE SAME - A receiving circuit includes: a terminating resistor to set a terminating level of a transmission line for transmitting a reception signal including a signal having a first level indicating a preamble; a detection circuit to detect whether a level of the transmission line is the first level or a second level; and an adjustment circuit to adjust a resistance of the terminating resistor, the adjustment circuit adjusting the resistance of the terminating resistor to a value such that the detection circuit detects the level of the transmission line as the second level when a data request is output to a transmitting side. | 09-22-2011 |
| 20110227599 | SEMICONDUCTOR DEVICE TEST METHOD AND SEMICONDUCTOR DEVICE - A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks. | 09-22-2011 |
| 20110227127 | ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT AND SEMICONDUCTOR DEVICE - An electro-static discharge protection circuit includes: a PNPN junction, a P-type side of the PNPN junction being coupled to a terminal, an N-type side of the PNPN junction being coupled to ground; and a P-type metal oxide semiconductor transistor, a source and a gate of the P-type metal oxide semiconductor transistor being coupled to an N-type side of a PN junction whose P-type side coupled to the ground, and a drain of the P-type metal oxide semiconductor transistor being coupled to the terminal. | 09-22-2011 |
| 20110225395 | DATA PROCESSING SYSTEM AND CONTROL METHOD THEREOF - In a data processing system which includes a processor performing a processing in correspondence with a fetched instruction and a DRC capable of dynamically reconfiguring a circuit configuration in correspondence with configuration data, when the processor fetches the instruction, a configuration data decoder identifies whether or not the instruction is a configuration data instruction. When the instruction is the configuration data instruction, the configuration data is read from the configuration data memory in which the configuration data is housed and supplied to the DRC based on address information included in the configuration data instruction, thereby to enable the configuration data to be supplied to the DRC at a timing the same as a timing at which the instruction is fetched, so that the configuration data can be supplied at a high speed. | 09-15-2011 |
| 20110222351 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprises a second transistor including second gate insulation films and drives the control gate line and the source line with a boost voltage higher than the first driving voltage. | 09-15-2011 |
| 20110221466 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE - According to the following disclosure, disclosed is a semiconductor device including: an internal circuit configured to receive and output a signal current; a current mirror unit outputting a copied current corresponding to the signal current; and a test pad from which the copied current is taken out. | 09-15-2011 |
| 20110221000 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region. | 09-15-2011 |
| 20110219276 | APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUITS, AND A NON-TRANSITORY COMPUTER-READABLE MEDIUM HAVING A SEMICONDUCTOR INTEGRATED CIRCUIT TESTING PROGRAM - An apparatus for testing a semiconductor integrated circuit includes a pattern data generating unit configured to generate test pattern data for testing a write operation in a memory of the semiconductor integrated circuit; and a write unit configured to write the test pattern data into a storage area of the semiconductor integrated circuit. | 09-08-2011 |
| 20110217847 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit. | 09-08-2011 |
| 20110217792 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An FeRAM is produced by a method including the steps of forming a lower electrode layer ( | 09-08-2011 |
| 20110216863 | RECEIVING APPARATUS AND METHOD FOR SETTING GAIN - A receiving apparatus includes: a clock-data recovery circuit to generate a clock based on receive data and a setting circuit to set a gain of a filtering process to filter a phase difference between the receive data and the clock. | 09-08-2011 |
| 20110212551 | CONTACTOR, TEST DEVICE FOR SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A contactor includes a contactor base material including a first material and a conductor film including a second material. The conductor film is formed only on a contact surface with an electrode of a semiconductor apparatus at a tip of the contactor film. | 09-01-2011 |
| 20110210424 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Ferroelectric capacitors ( | 09-01-2011 |
| 20110210383 | IMAGING DEVICE - First diffusion region constituting a photodiode in each pixel stores carriers generated according to incident light. Second diffusion region is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the peripheral part of the first diffusion region, crystal defects tend to occur by a process of forming an isolation region and a gate electrode, so that dark current noise tends to occur. The second diffusion region functioning as a protection layer prevents crystal defects in a manufacturing process. The second diffusion region isn't formed on a center of the surface of the first diffusion region where crystal defects don't tend to occur. In the first diffusion region where the second diffusion region isn't formed, the thickness of a depletion layer increases, which improves light detection sensitivity. This improves detection sensitivity of the photodiode without increasing the dark current noise. | 09-01-2011 |
| 20110209006 | MICROCOMPUTER - When a CPU executes a failure detection program, the CPU causes a program counter expected value register to store an expected value of an address which is stored in a program counter after a detection time passes from the start of execution of the failure detection program, and causes a detection time counter to start counting of the detection time. When the detection time counter finishes counting of the detection time, the first comparator outputs as a failure detection result a result of comparison between the address stored in the program counter and the expected value stored in the program counter expected value register. | 08-25-2011 |
| 20110207053 | EXPOSURE METHOD AND METHOD OF MAKING A SEMICONDUCTOR DEVICE - An exposure method includes generating a reticle exposure pattern based on a target pattern, performing a lithography simulation based on the reticle exposure pattern to generate a simulation pattern that simulates a resist pattern formed by reticle exposure, generating differential data between the target pattern and the simulation pattern, generating a first electron-beam exposure pattern based on the differential data, generating a reticle based on the reticle exposure pattern, performing an optical exposure process with respect to a resist by use of the reticle, and performing an electron-beam exposure process with respect to the resist based on the first electron-beam exposure pattern. | 08-25-2011 |
| 20110205808 | SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the source lines coupled to a row of the memory cells including a program memory cell to a high level voltage, and sets at least one of the remaining source lines coupled to a row of a non-program memory cells to be higher than a low level voltage of the selection gate lines and to be lower than the high level voltage of an unselection bit line. Thereby, a leak current lowering a voltage of the source lines at the time of program operation can be blocked off, and a program operation time may be shortened. | 08-25-2011 |
| 20110204945 | CALIBRATION - A method of calibrating a module whose operation is dependent upon a module clock signal, the method comprising: over each calibration period of a plurality of such periods, obtaining a measure of the frequency of an observed signal, the observed signal being the module clock signal or a clock signal generated based upon the module clock signal; influencing operation of the module in dependence upon the obtained measures so as to calibrate the module; and for each said calibration period, taking account of a position in time of the end of that calibration period relative to a particular feature of the observed signal and delaying the start of the following calibration period relative to a subsequent said particular feature of the observed signal in dependence upon that position. | 08-25-2011 |
| 20110204479 | SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming a second ferroelectric film on the first ferroelectric film by a sputtering method; forming a second conductive film on the second ferroelectric film; and forming a capacitor provided with a lower electrode, a capacitor dielectric film and an upper electrode by patterning the first conductive film, the first and second ferroelectric films and the second conductive film. | 08-25-2011 |
| 20110203916 | MAGNETRON-SPUTTERING FILM-FORMING APPARATUS AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE - A magnetron-sputtering film-forming apparatus includes: a vacuum film-forming chamber ( | 08-25-2011 |
| 20110202895 | VERIFICATION COMPUTER PRODUCT, METHOD, AND APPARATUS - A recording medium stores a verification program that causes a computer to execute detecting from a model circuit, a first circuit representing junction of a source region and a substrate region and including a junction resistance and a junction capacitance, a second circuit parallel to the first circuit, representing junction of a drain region and the substrate region, and including a junction resistance and a junction capacitance equivalent to the junction resistance and capacitance of the first circuit, and a connection resistance connecting the circuits and a substrate electrode; calculating, using the junction resistances and connection resistance, a first coefficient indicating impact of the junction resistances and connection resistance on amplitude variation; calculating, using the junction capacitances and connection resistance, a second coefficient indicating impact of the junction capacitances and connection resistance on phase variation; correcting the junction capacitances using a sum of the coefficients; and outputting a correction result. | 08-18-2011 |
| 20110198724 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode. | 08-18-2011 |
| 20110198707 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500 ° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers. | 08-18-2011 |
| 20110188610 | SIGNAL PROCESSING DEVICE, METHOD AND RECEIVING DEVICE - A signal processing device includes: a first correlator that sequentially multiplies a first receive signal including a pattern in a receive signal and a first reference pattern signal including a complex conjugate of a first partial signal of the first receive signal at a sampling timing to generate a first correlation voltage; a second correlator that sequentially multiplies the first receive signal and a second reference pattern signal including a complex conjugate of a second partial signal, which is behind the first partial signal, at a sampling timing to generate a second correlation voltage; and a phase difference generation circuit that generates a first phase difference between the first partial signal and the second partial signal based on a first correlation peak voltage obtained when the first correlation voltage has a peak value and a second correlation peak voltage obtained when the second correlation voltage has a peak value. | 08-04-2011 |
| 20110185152 | RECONFIGURABLE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction. | 07-28-2011 |
