| FTL Systems, Inc. Patent applications |
| Patent application number | Title | Published |
|---|
| 20100232811 | Highly Tunable, Low Jitter Optical Clock Generation - An apparatus is disclosed for the optical generation of clock signals with tunable frequency and low jitter. A laser source serves as both the carrier used to transmit the clock signal for use by other optical, electronic or hybrid circuit elements and the original modulation time base. A fraction of the original laser source undergoes one or more stages of frequency division before being recombined as a modulation signal with the remaining laser beam. Transmission of the resulting signal via single mode fiber and dividers retains the low jitter properties of the modulated signal. By starting with a clock signal of optical frequency then dividing downward in frequency, comparatively high frequency clocks may be generated, notably in the GigaHertz and TeraHertz frequency ranges. | 09-16-2010 |
| 20100023308 | METHOD FOR ACCELERATING SIMULATION PERFORMANCE AND INCREASING SIMULATION ACCURACY OF MODELS USING DYNAMIC SELECTION AND REPLACEMENT OF EXECUTABLE EMBODIMENTS WITH TEMPORALLY OPTIMAL FUNCTIONAL DETAIL AND SIMPLIFICATION - A method for increasing simulation speed is achieved by implementing a sequence of executable embodiments of digital, analog, mixed-signal or full-wave components are substituted during the process. The substituted embodiments represent more optimal instruction sequences, reconfigurable logic configurations or combinations thereof which may only be a valid representation of the model being simulated, subject to specific operating conditions. | 01-28-2010 |
| 20080250360 | METHOD FOR GENERATING COMPILER, SIMULATION, SYNTHESIS AND TEST SUITE FROM A COMMON PROCESSOR SPECIFICATION - A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target a FPGA, ASIC, system-on-a-chip or custom logic. It analyzes behavior of the embedded binaries running on processing units and implementations augmented by additional physical technology and parameters, yielding a more detailed prediction of the resulting hardware/software system behavior when realized through manufacturing. | 10-09-2008 |
