| FREESCALE SEMICONDUCTOR, INC Patent applications |
| Patent application number | Title | Published |
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| 20120036398 | MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING - A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations. | 02-09-2012 |
| 20120033772 | SYNCHRONISER CIRCUIT AND METHOD - A synchronizer circuit and method for transferring data between mutually asynchronous source and destination clock domains. An input synchronizer cell clocked at an input clock frequency receives input data from the source domain and produces a corresponding intermediate signal. A frequency divider produces a divided clock signal whose frequency is equal to the input clock frequency divided by an integer. An output synchronizer module comprises first and second cascaded synchronizer cells clocked at the divided clock frequency, receives the intermediate signal and produces a corresponding output signal for the destination clock domain. | 02-09-2012 |
| 20120032719 | ELECTRONIC CIRCUIT AND METHOD FOR OPERATING A MODULE IN A FUNCTIONAL MODE AND IN AN IDLE MODE - A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transistor that is coupled in parallel to at least one high-threshold transistor; wherein each hybrid circuit is arranged to maintain information or a control signal when provided with the supply voltage of the idle level; and wherein high-threshold transistors of each hybrid circuit are arranged to maintain information or a control signal when provided with a supply voltage of a level that is higher than the idle level. | 02-09-2012 |
| 20120032167 | SEMICONDUCTOR PACKAGE AND METHOD OF TESTING SAME - A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to the wire layout pattern. An encapsulation material covers at least the integrated circuit and the solder mask layer. One or more crack seal rings are disposed on the solder mask surface. The crack seal rings are copper traces with terminals that allow current to be applied to the traces. A broken trace (open circuit condition) is indicative of a crack in the package. Thus, electrical testing is performed to detect physical defects. | 02-09-2012 |
| 20120030381 | RECHARGEABLE DEVICE AND METHOD FOR DETERMINING UNIVERSAL SERIAL BUS PORT TYPE - A method for detecting a type of a port connected to a USB connector and a rechargeable device with a USB connector, a USB controller and a power management module. The power management module selectively powers up the USB controller depending on the type of port connected to the USB connector. A hardware detector is connected to the USB connector for determining the port type. If the port type is for recharging only then the power management module does not enable power to the USB controller. | 02-02-2012 |
| 20120027159 | SYSTEM AND METHOD FOR SETTING COUNTER THRESHOLD VALUE - A system and method for configuring threshold values for fixed time delay counters of a System on a Chip (SoC) uses a reference clock signal and one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal. A frequency sub-range of the reference clock signal is determined using the frequency sub-range control signals and the determined frequency sub-range is used to select a counter threshold value. The selected counter threshold value is provided to a counter and the counter then is updated at each cycle of the reference clock signal for a predetermined count based on the counter threshold value. | 02-02-2012 |
| 20120026716 | PACKAGE ASSEMBLY AND METHOD OF TUNING A NATURAL RESONANT FREQUENCY OF A PACKAGE - A package assembly comprises an electronic device; a package body; at least a first plurality of leads having a first geometrical shape and a second plurality of leads having a second geometrical shape, protruding from the package body; each of the first plurality of leads being located in corners of the package body; or the first and the second plurality of leads arranged in at least a first row and a second row located in parallel to the first row; each of the rows comprising at least two leads; the first row being transformable into the second row by mirroring the first row along a symmetry plane of the package body; each of the first plurality of leads having the first geometrical shape different from the second geometrical shape. | 02-02-2012 |
| 20120021586 | METHODS FOR FORMING VARACTOR DIODES - Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q. | 01-26-2012 |
| 20120020560 | METHOD AND SYSTEM ARRANGED FOR FILTERING AN IMAGE - A method and a system, the system includes: a memory unit, an image region definer, a spectral analyzer, a determination module, and an image processor. The spectral analyzer is arranged to divide a frequency spectrum of each image region into at least three image region frequency range components (IRFRCs); and calculate an energy level for each IRFRC. The comparator configured to compare the energy level of each IRFRC to at least one frequency region threshold to provide a comparison result for each IRFRC; wherein each frequency region threshold is calculated based on an intensity parameter of an image section and based on an energy parameter of at least one reference image section; a determination module arranged to determine a processing operation for each IRFRC, based on a comparison result associated with the IRFRC and based on a configurable decision rule. | 01-26-2012 |
| 20120018858 | METHOD OF ASSEMBLING INTEGRATED CIRCUIT DEVICE - A method of assembling an integrated circuit (IC) device includes the steps of providing a lead frame or substrate panel, attaching a semiconductor die to the lead frame or substrate panel and electrically coupling the die to the lead frame or substrate panel. The method further includes encapsulating the die with a first encapsulant, and the encapsulating the first encapsulant with a second encapsulant where the second encapsulant includes a material that provides electromagnetic shielding. | 01-26-2012 |
| 20120015616 | ADAPTIVE IIP2 CALIBRATION - A radio frequency transceiver ( | 01-19-2012 |
| 20120013449 | RADIO FREQUENCY REMOTE CONTROLLER DEVICE, INTEGRATED CIRCUIT AND METHOD FOR SELECTING AT LEAST ONE DEVICE TO BE CONTROLLED - A radio frequency (RF) remote controller device comprises radio frequency (RF) circuitry operably coupled to an antenna arrangement and arranged to transmit and receive RF signals to and from controllable devices. The RF remote controller device further comprises signal process logic operably coupled to the RF circuitry and to a user interface. The antenna arrangement is arranged to comprise a directivity characteristic. The signal processing logic upon receipt of a command input from the user interface, is arranged to: determine at least one link quality value that is at least partly dependent upon the directivity characteristic for the at least one controllable device; and select the controllable device for remote controlling based on the determined at least one link quality value. | 01-19-2012 |
| 20120013365 | LOW VOLTAGE DETECTOR - A low voltage detector ( | 01-19-2012 |
| 20120008641 | RECEIVING NODE IN A PACKET COMMUNICATIONS SYSTEM AND METHOD FOR MANAGING A BUFFER IN A RECEIVING NODE IN A PACKET COMMUNICATIONS SYSTEM - A receiving node for receiving data packets in a packet communications system comprises a buffer for storing data packets received at the receiving node and for releasing the stored data packets to an application element of the receiving node. A buffer window defines a time period in which data packets are received at the buffer. A position of the buffer window is moved in time periodically, and a stored data packet is released when it is at an end of the buffer window. The receiving node further comprises a packet delay determining element for determining, for each received data packet, a delay of a received data packet by determining the difference between an estimated time of arrival of a data packet at the receiving node and an actual time of arrival of the data packet at the receiving node, a delay processing element for determining an average of the determined delays of a plurality of data packets and for determining when a change in the determined average is greater than a first threshold, and a buffer window adjusting element for adjusting at a first rate a position of the buffer window by a first amount dependent on the determined average of the determined delays and for switching to adjust a position of the buffer window at a second rate by a second amount dependent on the determined average when a change in the determined average is greater than the first threshold. The second rate is greater than the first rate. | 01-12-2012 |
| 20120008438 | EFFICIENT WORD LINES, BIT LINE AND PRECHARGE TRACKING IN SELF-TIMED MEMORY DEVICE - A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line. | 01-12-2012 |
| 20120007829 | METHOD AND SYSTEM FOR TOUCH SENSOR INTERFACE FAULT DETECTION - A touch sensor interface includes one or more touch detection electrodes whose capacitance increases when touched. A processor converts the increase in capacitance into a change in a counter value. A detector compares the change in the counter value with one or more count thresholds to detect faults in the touch sensor interface. | 01-12-2012 |
| 20120007725 | METHOD AND APPARATUS FOR SELECTING AT LEAST ONE DEVICE TO BE WIRELESSLY CONTROLLED - A method for selecting at least one device to be controlled by a radio frequency (RF) controller device is described. The method comprising arranging a plurality of controllable devices into a plurality of groups; determining at least one link quality value for at least one device associated with the plurality of groups; calculating a proximity factor for the plurality of groups of controllable devices based at least partly on the determined at least one link quality value; comparing proximity factors for the plurality of groups of and selecting the group of controllable devices comprising a favourable proximity factor to be controlled by the RF controller device. | 01-12-2012 |
| 20120007155 | SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS - A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region. | 01-12-2012 |
| 20120007031 | PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR - A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure. | 01-12-2012 |
| 20110316592 | REFRESH OPERATION DURING LOW POWER MODE CONFIGURATION - A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation. | 12-29-2011 |
| 20110316511 | METHOD AND APPARATUS FOR DC-TO-DC CONVERSION - A direct current-to-direct current (‘DC-DC’) converter generates a pulse-width modulated (‘PWM’) control signal, and generates an output voltage from an input voltage as a function of a duty cycle of the PWM control signal. A feed-forward module controls both the duty cycle and a repetition rate of the PWM control signal as regressive functions of the input voltage so as to tend to compensate for variation in the input voltage. | 12-29-2011 |
| 20110316130 | THIN SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a thin semiconductor package includes providing a lead frame with a removable substrate that has an attaching surface attached to a first surface of the lead frame. The lead frame is formed from an electrically conductive sheet and has leads that extend inwardly from a lead frame boundary towards a central region of the lead frame. A semiconductor die is mounted on the removable substrate at the central region. The semiconductor die has a connection pad surface with die pads on it, and the connection pad surface is attached to the attaching surface of the removable substrate. The lead frame and die are encapsulated with a first encapsulant so that the lead frame is sandwiched between the first encapsulant and the removable substrate. The removable substrate is removed from the lead frame to expose the first surface of the lead frame and then the die pads are electrically connected to respective ones of the leads. The die and lead frame then are encapsulated with a second encapsulant so that the lead frame and die are sandwiched between the first and second encapsulants. Part of the first encapsulant is then removed to reduce the thickness of the package and expose the leads. | 12-29-2011 |
| 20110312175 | METHODS FOR FORMING ANTIFUSES WITH CURVED BREAKDOWN REGIONS - Methods are disclosed for forming an antifuse that includes first and second conductive regions having spaced-apart curved portions, with a first dielectric region therebetween, forming in combination with the curved portions a curved breakdown region adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region is desirably provided adjacent the breakdown region to inhibit heat loss from the breakdown region during programming. Lower programming voltages and currents are observed compared to antifuses using substantially planar dielectric regions. In a further embodiment, a resistive region is inserted in one lead of the antifuse with either planar or curved breakdown regions to improve post-programming sense reliability. | 12-22-2011 |
| 20110311017 | CLOCK GLITCH DETECTION - A circuit comprises a clock tree for distributing a clock signal. A first counter is arranged at a first point in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter is arranged at a second point in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator compares the first current count and the second current count. The first point and the second point are not the same, or the second delay is longer than the first delay. | 12-22-2011 |
| 20110309419 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A RESISTOR-CAPACITOR FILTER - A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor. | 12-22-2011 |
| 20110299638 | LOGARITHMIC DETECTOR AND METHOD OF PRE-CHARGING AN AVERAGE FILTER ON A LOGARITHMIC DETECTOR - The detector comprises a plurality of detection stages connected to a summator for providing a summation signal as a logarithmic representation of the input signal to a first input of a data slicer and an input of an average filter having an output connected to a second input of the data slicer. The data slicer has a data slicer output for providing an extracted digital data signal in dependence on a comparison of the summation signal and an output signal of the average filter. The average filter receives a first pre-charge voltage and a second pre-charge voltage depending on an output signal of a carrier detector circuit detecting a carrier signal of the input signal. | 12-08-2011 |
| 20110299337 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-08-2011 |
| 20110298506 | INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE - An integrated circuit comprises frequency generation circuitry for controlling a frequency source for use in an automotive radar system. The frequency generation circuitry comprises low-path modulation circuitry arranged to generate a first, low-path control signal for providing lower frequency modulation of the frequency source, the low-path modulation circuitry comprising a Phase Locked Loop (PLL) arranged to generate the low-path control signal for controlling the frequency source and a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control module operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of at least a first, lower frequency pattern control signal. The frequency generation circuitry further comprises high-path modulation circuitry arranged to generate a second, high-path control signal for providing higher frequency modulation of the frequency source. | 12-08-2011 |
| 20110297935 | SEMICONDUCTOR DEVICE WITH APPRAISAL CIRCUITRY - A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value. | 12-08-2011 |
| 20110296366 | METHOD OF MAKING ROUTABLE LAYOUT PATTERN USING CONGESTION TABLE - A method for generating a standard cell layout pattern for standard cell placement in an integrated circuit uses a congestion map. First, congestion zones are identified in a congestion map generated by an Electronic Design Automation (EDA) application. Next, routing tracks data corresponding to bounding boxes belonging to the congestion zones are used to calculate values of average vertical and horizontal congestion. Subsequently, a value of modified standard cell density is calculated based on the values of average vertical and horizontal congestion, and an unmodified standard cell density. The dimensions of a layout pattern unit are calculated using the value of the modified standard cell density and the width of standard cells. Various layout pattern units then are placed adjacent to one another to form a standard cell layout pattern. | 12-01-2011 |
| 20110296265 | SYSTEM FOR TESTING INTEGRATED CIRCUIT WITH ASYNCHRONOUS CLOCK DOMAINS - A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal provided externally through one package pin of the integrated circuit. The clock gate control unit provides clock gate control signals to the clock gating cells. The clock gating cells generate time-staggered clock signals based on the clock gate control signals. | 12-01-2011 |
| 20110296221 | METHOD AND SYSTEM FOR INTEGRATED CIRCUIT POWER SUPPLY MANAGEMENT - A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block. | 12-01-2011 |
| 20110295586 | CLOCK SIMULATION DEVICE AND METHODS THEREOF - A pulse width of a simulated external system clock is set by determining a least common multiple of the frequency of selected internal clock signals relative to the frequency of the external system clock. The pulse width can be further adjusted based on the frequency of simulated external clocks. By setting the pulse width of the simulated external system clock based on the least common multiple value, the time required to complete the simulation can be reduced while ensuring proper operation of the simulated clock signals during the simulation. | 12-01-2011 |
| 20110293019 | Video processing system, computer program product and method for decoding an encoded video stream - Video processing system, computer program product and method for decoding an encoded video stream, the method includes: receiving an encoded video stream that comprises a plurality of encoded video frames, each encoded video frame comprises multiple encoded frame portions; and repeating, for each encoded frame portion: providing, to an entropy decoder, different quality level representations of the encoded frame portion and context information generated during an entropy decoding process of different quality level representations of another encoded frame portion; entropy decoding, by the entropy decoder, the different quality level representations of the frame portion based on the context information; wherein the entropy decoding comprises updating the context information; wherein the entropy decoding is selected from a group consisting of context based adaptive binary arithmetic coding (CABAC) and context based variable length coding (CBVLC); and storing the context information. | 12-01-2011 |
| 20110293009 | Video processing system, computer program product and method for managing a transfer of information between a memory unit and a decoder - Video processing system, computer program product and method for managing an exchange of information between a memory unit and a decoder, the method includes: (a) retrieving, from the memory unit, a first non-zero data structure that comprises only non-zero first transform coefficient groups; wherein first transform coefficient groups are associated with a first quality level; (b) retrieving, from the memory unit, second layer information; (c) processing, by the video decoder, the second layer information and the first non-zero data structure to provide second transform coefficient groups; (c) generating, by the video decoder, a second non-zero data structure that comprises only non-zero second transform coefficient groups; wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; (d) generating second non-zero indicators that are indicative of non-zero transform coefficient groups, wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; and (e) writing to the memory unit the second non-zero indicators. | 12-01-2011 |
| 20110292292 | METHOD AND APPARATUS FOR DISPLAYING VIDEO DATA - A method of displaying consecutively first and second asynchronous video data streams on a display device, where there is a transition from the first video data stream to the second video data stream. The transition includes interrupting updating the display on the video display device during a prolonged vertical blanking interval in response to assertion of a vertical blanking pulse in the first video stream until subsequent de-assertion of a vertical blanking pulse in the second video stream, and displaying the second video data stream starting with a frame following the subsequent de-assertion of the vertical blanking pulse in the second video stream. | 12-01-2011 |
| 20110291740 | METHOD FOR SUPPLYING AN OUTPUT SUPPLY VOLTAGE TO A POWER GATED CIRCUIT AND AN INTEGRATED CIRCUIT - An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator. | 12-01-2011 |
| 20110291724 | DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier. | 12-01-2011 |
| 20110291604 | STEPPER MOTOR CONTROLLER AND METHOD FOR CONTROLLING SAME - A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation circuitry. The individual driver pulse width modulation circuitry has individual driver pulse width modulation outputs and modulation control inputs coupled to the respective control outputs. The controller has a group of individual drivers, where each one has an individual driver input coupled to a respective one of the individual driver pulse width modulation outputs, and an individual driver output coupled to an individual driver terminal of the controller. The stepper motor controller has common driver pulse width modulation circuitry having a common driver pulse width modulation output. There is also a common driver having a common driver input coupled to the common driver pulse width modulation output and a common driver output coupled to a common driver terminal of the controller. When there is one or more stepper motor field coils connected between respective driver terminals and the common driver terminal, individual pulse width modulated driver currents are supplied to the stepper motor field coils from the individual driver terminals and a common pulse width modulated driver current is supplied to the stepper motor field coils from the common driver terminal. | 12-01-2011 |
| 20110291278 | SEMICONDUCTOR DEVICES WITH LOW RESISTANCE BACK-SIDE COUPLING - Electronic elements with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes, preferably dielectric lined, in front sides of substrates, filling the trenches or pipes with a conductor having a coefficient of expansion not too different from that of the substrate but of higher conductivity, forming an epitaxial SC layer over the front side of the substrate in Ohmic contact with the conductor the trenches or pipes, forming various semiconductor (SC) devices in the epi-layer, back grinding the substrate to expose bottoms of the conductor filled trenches or pipes, and providing a back-side conductor contacting the conductor in the trenches or pipes. For silicon SCs, tungsten is a suitable conductor for filling the trenches or pipes to minimize substrate stress. Series ON-resistance of the elements due to the substrate resistance is substantially reduced. | 12-01-2011 |
| 20110285575 | INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE - An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal. | 11-24-2011 |
| 20110279658 | METHOD FOR SYNCHRONIZING REMOTE DEVICE - A method for synchronizing a function on a remote device with a function on a primary device includes selectively broadcasting, from a radio frequency (RF) transmitter of the primary device, data broadcast on channels at different times relative to a fixed period strobe signal of the primary device. Only the channels that have a noise level below a specified threshold level selectively broadcast the data and each of the channels have an associated fixed time frame offset relative to the fixed period strobe signal. Each of the channels is broadcast after their associated fixed time frame offset expires. An RF receiver of the remote device receives the data on one of the channels. The data on each of the channels is received at different times, depending on its associated fixed time frame offset, which results in the data on each received channel having an associated received time reference relative to a strobe signal of the remote device. The remote device strobe signal is synchronized to determine a received time reference and the fixed time frame offset. The remote device function is cyclically performed, which results in the remote device function being synchronized with the primary device function. The method may be used to synchronize a 3D video signal broadcast from a transmitter to sets of 3D glasses. | 11-17-2011 |
| 20110279126 | Electrostatic occupant detection system - An electrostatic occupant detection system includes an electrostatic sensor and an electronic control unit. The electronic control unit is switchable between an occupant determination state in which the electronic control unit outputs a sine wave having a constant amplitude and a diagnosis state in which the electronic control unit maintains a voltage of the electrostatic sensor at a constant level. The electronic control unit gradually changes at least one of an amplitude and a frequency of the sine wave either when the electronic control unit switches from the occupant determination state to the diagnosis state and/or when the electronic control unit switches from the diagnosis state to the occupant determination state. | 11-17-2011 |
| 20110278598 | SEMICONDUCTOR STRUCTURE, AN INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE - A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal. The structure further includes a vertical Schottky diode, including: an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and a anode layer in the stack of layers. | 11-17-2011 |
| 20110272823 | THROUGH SUBSTRATE VIAS - Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5. | 11-10-2011 |
| 20110271083 | MICROPROCESSOR ARCHITECTURE AND METHOD OF INSTRUCTION DECODING - A microprocessor architecture comprises an instruction decoding network for decoding in a first mode partially suppressed opcodes of a sequence of instructions, the opcodes comprising a first part containing parameters being invariant for each opcode of the sequence and a second part comprising a flag indicating an end of the sequence, the first part being suppressed for all opcodes of the sequence except a first opcode of the sequence. Further, a method of instruction decoding in a microprocessor architecture comprising an instruction decoding network for decoding in a first mode partially suppressed opcodes of a sequence of instructions, and in a second mode uncompressed instructions comprises decoding an opcode of an instruction in the second mode when the instruction is not compressible; and decoding an opcode of an instruction in the first mode when the instruction is compressible. | 11-03-2011 |
| 20110267728 | OVERCURRENT PROTECTION CIRCUIT, INTEGRATED CIRCUIT, APPARATUS AND COMPUTER PROGRAM PRODUCT - An over-current protection circuit, including a current input for receiving a input current and a current output electrically connectable to a load, for outputting an output current proportional to the input current. A switch connects the current input to the current output. The switch has at least two switch states including an open state in which a current flow from the current input to the current output is interrupted and a closed state in which the current flow is enabled. The switch includes a switch control input for controlling the switch state. The circuit has a sensor for sensing a load current applied to the load and a controller connected to the sensor for controlling the switch to be in the open state when the sensed load current has exceeded a current threshold during a predetermined period of time, the predetermined period of time being dependent on an amount with which said sensed load current exceeds the threshold. | 11-03-2011 |
| 20110267147 | OSCILLATOR CIRCUIT - An oscillator circuit comprises a push-push oscillator and a differential output, comprising a first and a second output circuit. The push-push oscillator has a first and a second branch. Each of the first and second branch comprises an own voltage divider branch of a common bridge circuit. Each of the first and second voltage divider branches comprises an own pair of micro-strip lines connected in series. Each of the first and second voltage divider branches has an own tap. Both taps are connected to each other by at least one of a first capacity and a micro-strip line. The differential output comprises a first and a second output terminal. The first output terminal is connected via the first output circuit to a first node. The second output terminal is connected via the second output circuit to a second node. Each of the first and second nodes of the push-push oscillator is a common node of both of the first and the second branches. | 11-03-2011 |
| 20110266687 | ELECTRONIC ELEMENTS AND DEVICES WITH TRENCH UNDER BOND PAD FEATURE - Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material. | 11-03-2011 |
| 20110266663 | LEAD FRAME BASED SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterized in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface. | 11-03-2011 |
| 20110263077 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES INCLUDING SAW SINGULATION - A method of assembling semiconductor devices for surface mounting includes forming an array of lead frames in which supporting frame structures of adjacent lead frames include an intermediate common bar connecting on both its sides with sets of leads of the respective adjacent lead frames. The semiconductor devices are singulated by sawing through the leads on each side of the common bars without sawing the common bars longitudinally. The material sawn off from the common bars in a first direction is removed by washing it away before sawing off the intermediate common bars that run in an orthogonal direction. The supporting frame structures include bars surrounding the array and singulation includes sawing beside the surrounding bars to saw them off before sawing off the intermediate common bars. | 10-27-2011 |
| 20110261949 | Techniques for Implementing Adaptation Control of an Echo Canceller to Facilitate Detection of In-Band Signals - A technique for detecting in-band signaling tones in a communication system includes performing a first adaptation of an adaptive filter of an echo canceller in response to detection of a far-end harmonic signal. In this case, the adaptive filter provides an echo estimation signal. The technique also includes subtracting the echo estimation signal from a near-end signal that includes one or more in-band signaling tones to provide an error signal. The technique further includes detecting, using a tone detector, the one or more in-band signaling tones in the error signal. | 10-27-2011 |
| 20110261948 | Techniques for Updating Filter Coefficients of an Adaptive Filter - A technique for updating filter coefficients of an adaptive filter includes filtering a signal with an adaptive filter, whose filter coefficients are grouped into filter blocks. In this case a number of the filter blocks is less than or equal to a number of the filter coefficients. During each update period, the filter coefficients for less than all of the filter blocks are updated based on a network echo path impulse response. | 10-27-2011 |
| 20110261903 | WIRELESS COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD OF POWER CONTROL OF A POWER AMPLIFIER THEREFOR - A wireless communication unit comprises a transmitter having a forward path comprising a power amplifier, PA, and a feedback path operably coupled to the power amplifier, wherein the feedback path comprises a coupler arranged to feed back a portion of a signal to be transmitted and a controller logic module arranged to control a power control value of the power amplifier, such that the forward path and feedback path form a closed loop power control. The controller logic module is arranged to determine a gain variation in the transmitter and provide attenuation to a transmit signal passing therethrough on a transmit slot by transmit slot basis and instruct a power backoff where necessary. | 10-27-2011 |
| 20110261500 | BACK END OF LINE METAL-TO-METAL CAPACITOR STRUCTURES AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures. The first metal layer provides an intralayer electrical interconnection among the second plurality of vertical conductive structures, wherein each vertically-aligned region has a vertical conductive structure of the second plurality of vertical conductive structures disposed therein. | 10-27-2011 |
| 20110258588 | INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE AND METHOD THEREFOR - A method implemented at a computer aided design tool includes preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances. Preferentially placing the fill regions includes preferentially placing the fill regions adjacent to transistors of a first conductivity type as compared to placing the fill regions adjacent to transistors of a second conductivity type that is opposite the first conductivity type. | 10-20-2011 |
| 20110258462 | METHOD, SYSTEM AND INTEGRATED CIRCUIT FOR ENABLING ACCESS TO A MEMORY ELEMENT - A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory. | 10-20-2011 |
| 20110255357 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) REFRESH - A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate. | 10-20-2011 |
| 20110250721 | STACKED AND SHIELDED PACKAGES WITH INTERCONNECTS - Embodiments include methods for forming a stacked die package with a first die, first active circuitry on an upper surface of the first die, and a first conductive pattern on the first active circuitry. The stacked die package further includes a second die stacked over the first die, where the first die is wider than the second die in a cross-section of the stacked die package, and second active circuitry is present on an upper surface of the second die. The stacked die package further includes a mold compound disposed on the first die, where the mold compound encapsulates the second die. Electrical connections are formed from the top surface of the mold compound to the first conductive pattern and the second active circuitry, and a conductive pattern on the top surface of the mold compound provides a continuous electrical connection between upper ends of the electrical connections. | 10-13-2011 |
| 20110249869 | SYSTEM AND METHOD FOR EFFICIENT IMAGE FEATURE EXTRACTION - A system for efficient image feature extraction comprises a buffer for storing a slice of at least n lines of gradient direction pixel values of a directional gradient image. The buffer has an input for receiving the first plurality n of lines and an output for providing a second plurality m of columns of gradient direction pixel values of the slice to an input of a score network, which comprises comparators for comparing the gradient direction pixel values of the second plurality of columns with corresponding reference values of a reference directional gradient pattern of a shape and adders for providing partial scores depending on output values of the comparators to score network outputs which are coupled to corresponding inputs of an accumulation network having an output for providing a final score depending on the partial scores. | 10-13-2011 |
| 20110248779 | AMPLIFIER CIRCUITRY, INTEGRATED CIRCUIT AND COMMUNICATION UNIT - Amplifier circuitry comprising a class-D amplifier for amplifying an audio input signal. The amplifier circuitry comprises sigma-delta modulation logic arranged to receive the audio input signal and to generate a modulated signal representative of the audio input signal, and an output stage arranged to generate an output signal for the amplifier circuitry. The amplifier circuitry further comprises finite impulse response, filter logic operably coupled between the modulation logic and the output stage, and having at least one zero in its transfer function arranged to substantially pass signal components within the modulated signal occurring at frequencies less than the at least one zero and to attenuate signal components within the modulated signal at frequencies greater than the at least one zero. | 10-13-2011 |
| 20110248660 | CIRCUIT AND METHOD FOR SPEED MONITORING OF AN ELECTRIC MOTOR - A circuit for speed monitoring of an electric motor comprises a circuit for generating a time-frame signal, a circuit for receiving a first signal from a chopper driver circuit designed to drive the electric motor, a circuit for detecting chopper pulses in the first signal, a pulse counter, and a circuit for at least one of outputting and evaluating a state of the pulse counter, after the inactive state of the time-frame has been indicated. The time-frame signal indicates when a time-frame of predefined length changes from an inactive state to an active state and indicates when the time-frame changes back from the active state to the inactive state. The pulse counter is designed to count the detected chopper pulses while the active state is indicated by the circuit for generating the time-frame signal. | 10-13-2011 |
| 20110248659 | DETERMINING INITIAL ROTOR POSITION OF AN ALTERNATING CURRENT MOTOR - Determination of an estimated initial angular position of the rotor of an AC motor includes application of voltages corresponding to a high frequency reference signal vector to the stator windings of the motor and production of an estimated initial angular position of the rotor as a function of the resulting q-axis stator current component iq_HF, adjustment of transformation of signal vectors from stationary to rotating coordinates and vice versa using the estimated angular position, and production of an adjusted estimated angular position of the rotor as a function of the q-axis stator current component as adjusted. Determination of an initial estimated angular position of the rotor and production of an adjusted initial estimated angular position of the rotor is performed with the rotor at standstill and before initially applying voltage corresponding to the drive signal vector to the stator windings, and production of an initial value of a drive signal vector command in stationary coordinates uses the adjusted estimated angular position. Determination of an estimated angular position of the rotor after application of stator current may use a different method, such as a physical relative position sensor. | 10-13-2011 |
| 20110248393 | LEAD FRAME FOR SEMICONDUCTOR DEVICE - A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame. | 10-13-2011 |
| 20110248390 | LEAD FRAME FOR SEMICONDUCTOR PACKAGE - A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die. The lead frame includes a die support area for receiving and supporting the IC die and a plurality of leads surrounding the die support area. A plurality of interconnect receiving portions is formed in the die support area. The interconnect receiving portions are for providing electrical interconnection to first bumps on a bottom surface of the IC die. The leads are for providing electrical interconnection to second bumps on a surface of the IC die, the second bumps surrounding the first bumps. | 10-13-2011 |
| 20110246958 | METHOD FOR REDUCING SURFACE AREA OF PAD LIMITED SEMICONDUCTOR DIE LAYOUT - A method for reducing a surface area of a pad limited semiconductor die layout includes choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die. Next, the method performs selecting, from the outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to an external connection pad. The method then performs repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row. After he repositioning there is performed a step of adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row. The method then provides for repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on every one of the outer die pad rows, has been selected by the selecting step. | 10-06-2011 |
| 20110246205 | METHOD FOR DETECTING AUDIO SIGNAL TRANSIENT AND TIME-SCALE MODIFICATION BASED ON SAME - A method for detecting a transient in an audio signal that has been broken up into frames includes obtaining a time domain feature of the frames and comparing the domain feature with a predetermined value. If the time domain feature is greater than the predetermined value, the frames are taken as transient and if the time domain feature is less than the predetermined value, the frames are taken as non-transient. The method has a low computational intensity and is thus very suitable for devices with limited processing resources. | 10-06-2011 |
| 20110244637 | MOLD AND SUBSTRATE FOR USE WITH MOLD | 10-06-2011 |
| 20110241713 | TEST STRUCTURE ACTIVATED BY PROBE NEEDLE - A test structure ( | 10-06-2011 |
| 20110241187 | LEAD FRAME WITH RECESSED DIE BOND AREA - A lead frame having a recessed die bond area. The lead frame has top and bottom surfaces and a first lead frame thickness defined as the distance between the top and bottom surfaces. The lead frame has a die bond area surface located within a reduced die bond area. A second thickness is defined as the distance between the die bond area surface and the bottom surface. The second lead frame thickness is less than the first lead frame thickness such that a semiconductor die disposed and attached to the die bond area surface has a reduced overall package thickness. A side wall formed between the die bond area surface and the top surface contains the adhesive material used to attach the die, which reduces adhesive bleeding and prevents wire bonding contamination. | 10-06-2011 |
| 20110241181 | SEMICONDUCTOR DEVICE WITH A CONTROLLED CAVITY AND METHOD OF FORMATION - A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening. | 10-06-2011 |
| 20110241159 | HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE - A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts. | 10-06-2011 |
| 20110241092 | ELECTRONIC DEVICE WITH CAPCITIVELY COUPLED FLOATING BURIED LAYER - Transistors ( | 10-06-2011 |
| 20110241083 | SEMICONDUCTOR DEVICE AND METHOD - Transistors ( | 10-06-2011 |
| 20110238941 | SCHEDULING MEMORY ACCESS REQUESTS USING PREDICTED MEMORY TIMING AND STATE INFORMATION - A data processing system employs an improved arbitration process in selecting pending memory access requests received from the one or more processor cores for servicing by the memory. The arbitration process uses memory timing and state information pertaining both to memory access requests already submitted to the memory for servicing and to the pending memory access requests which have not yet been selected for servicing by the memory. The memory timing and state information may be predicted memory timing and state information; that is, the component of the data processing system that implements the improved scheduling algorithm may not be able to determine the exact point in time at which a memory controller initiates a memory access for a corresponding memory access request and thus the component maintains information that estimates or otherwise predicts the particular state of the memory at any given time. | 09-29-2011 |
| 20110238934 | ASYNCHRONOUSLY SCHEDULING MEMORY ACCESS REQUESTS - A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput. | 09-29-2011 |
| 20110233693 | ELECTROMECHANICAL TRANSDUCER DEVICE AND METHOD OF FORMING A ELECTROMECHANICAL TRANSDUCER DEVICE - A micro or nano electromechanical transducer device formed on a semiconductor substrate comprises a movable structure which is arranged to be movable in response to actuation of an actuating structure. The movable structure comprises a mechanical structure comprising at least one mechanical layer having a first thermal response characteristic and a first mechanical stress response characteristic, at least one layer of the actuating structure, the at least one layer having a second thermal response characteristic different to the first thermal response characteristic and a second mechanical stress response characteristic different to the first mechanical stress response characteristic, a first compensation layer having a third thermal response characteristic and a third mechanical stress characteristic, and a second compensation layer having a fourth thermal response characteristic and a fourth mechanical stress response characteristic. The first and second compensation layers are arranged to compensate a thermal effect produced by the different first and second thermal response characteristics of the mechanical structure and the at least one layer of the actuating structure such that movement of the movable structure is substantially independent of variations in temperature and to adjust a stress effect produced by the different first and second stress response characteristics of the mechanical structure and the at least one layer of the actuating structure such that the movable structure is deflected a predetermined amount relative to the substrate when the electromechanical transducer device is in an inactive state. | 09-29-2011 |
| 20110230014 | METHOD OF PROVIDING AN ELECTRONIC DEVICE INCLUDING DIES, A DIELECTRIC LAYER, AND AN ENCAPSULATING LAYER - A method of packaging an electronic device includes providing a patterned dielectric layer with an area sized to receive a first die, and another area sized to receive a second die, placing the first and second dies within the first and second areas, encapsulating the dies with an encapsulating material that has a different composition from the dielectric layer, forming a first signal line between the dies, forming a second signal line to the first die, and forming an additional signal line to the first die. The dielectric layer is disposed between the first signal line and the encapsulating material, the electronic device transmits a signal in an approximate range of 1 GHz to 100 GHz along the second signal line, and a signal that does not exceed approximately 900 MHz along the additional signal line. | 09-22-2011 |
| 20110228839 | DIGITAL ADAPTIVE CHANNEL EQUALIZER - A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit. | 09-22-2011 |
| 20110227229 | SEMICONDUCTOR WAFER PROCESSING - A method of processing a semiconductor wafer is provided which comprises treating a metallisation layer provided on a backside of the wafer to form a plurality of channels therein, such that at least some of the channels along substantially the length thereof extend through the thickness of the metallisation layer to the backside of the wafer, thereby exposing the material of the backside of the wafer. When the semiconductor wafer is separated into dies, each die is provided with a plurality of channels, which extend to an edge of the die. On attaching the die to a die attach flag by solder, the solder does not stick to the exposed material of the backside of the die, and channels are thereby formed in the solder. This allows venting of gases formed in the solder, and decreases void formation in the solder. | 09-22-2011 |
| 20110227148 | POWER MOS TRANSISTOR DEVICE AND SWITCH APPARATUS COMPRISING THE SAME - A transistor power switch device comprising an array of vertical transistor elements for carrying current between the first and second faces of a semiconductor body and a vertical avalanche diode electrically in parallel with the array of vertical transistors. The array of transistor elements includes at the first face an array of source regions of a first semiconductor type, at least one p region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the p region, and a conductive layer contacting the source regions and insulated from the control electrode. The vertical avalanche diode is configured to conduct breakdown current between the first and second faces in the off state of the device and having a first current carrying diode region of the second semiconductor type in contact with the first face and with the conductive layer and a second semiconductor region of the first semiconductor type electrically connected with the second face. | 09-22-2011 |
| 20110227146 | POWER MOS TRANSISTOR DEVICE - A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces, is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer. | 09-22-2011 |
| 20110227135 | SCHOTTKY DIODES - Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device. | 09-22-2011 |
| 20110223956 | ALLOCATION OF COMMUNICATION CHANNELS - A method of allocating a plurality of communication channels of a network, for a plurality of network stations of the network. The method comprises generating a common transmission message for the plurality of network stations and transmitting the generated transmission message to the plurality of network stations. The message comprises channel allocation information allowing an allocation of channels by the network stations, the information relating to each of the plurality of network stations. A network managing station for communicating with the plurality of network stations, there being a plurality of communication channels available for use by the plurality of network stations. The network managing station comprises a processor, arranged to generate the common transmission message for the plurality of network stations and a transmitter arranged to transmit the generated transmission to said plurality of networks. A network station, capable of communicating over one or more of a plurality of communication channels, the network station comprising: a receiver, arranged to receive the common transmission message and a processor, arranged to determine a channel for use by the network station based on the received channel allocation information. | 09-15-2011 |
| 20110222712 | AUDIO OUTPUT DRIVER FOR REDUCING ELECTROMAGNETIC INTERFERENCE AND IMPROVING AUDIO CHANNEL PERFORMANCE - An audio output circuit includes an on-chip left channel amplifier module, an on-chip center channel amplifier module, and an on-chip right channel amplifier module. A left channel IC pin is operably coupled to an output of the on-chip left channel amplifier module. A right channel IC pin is operably coupled to an output of the on-chip right channel amplifier module. A center channel IC pin is operably coupled to an output of the on-chip center channel amplifier module. A center channel feedback IC pin is operably coupled to an input of the on-chip center channel amplifier module to provide a feedback loop. A left jack connection is operably coupled to the left channel IC pin. A right jack connection is operably coupled to the right channel IC pin. A jack return connection coupled to the center feedback IC pin. An inductor has a first node coupled to the jack return connection and a second node coupled to the center channel IC pin. | 09-15-2011 |
| 20110221469 | LOGIC BUILT-IN SELF-TEST SYSTEM AND METHOD FOR APPLYING A LOGIC BUILT-IN SELF-TEST TO A DEVICE UNDER TEST - A logic built-in self test (LBIST) system comprises a device under test having a first plurality of first bistable multivibrator circuits an LBIST controller, and a second plurality of second bistable multivibrator circuits. Each second bistable multivibrator circuit is coupled to a corresponding first bistable multivibrator circuit to swap a second state value kept by the second bistable multivibrator circuit with a first state value kept by the corresponding first bistable multivibrator circuit depending on a first control signal from the LBIST controller and the second bistable multivibrator circuits are coupled to form one or more scan chains when receiving a second control signal from the LBIST controller. | 09-15-2011 |
| 20110221042 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A wafer structure ( | 09-15-2011 |
| 20110220975 | METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE - A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack. | 09-15-2011 |
| 20110217814 | METHOD FOR SINGULATING ELECTRONIC COMPONENTS FROM A SUBSTRATE - Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate. | 09-08-2011 |
| 20110215849 | CHARGE PUMP FOR PHASE LOCKED LOOP - A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal ( | 09-08-2011 |
| 20110215844 | FREQUENCY MULTIPLIER CIRCUIT - A frequency multiplier circuit, comprising a first stage including a first differential pair of amplifier elements having respective current conduction paths connected in parallel between first and second nodes and respective control terminals connected to receive input signals of opposite polarity at an input frequency in the radio frequency range, the first and second nodes being connected to respective bias voltage supply terminals through first and second impedances respectively so that current flowing differentially in the current conduction paths of the first differential pair of amplifier elements produces a voltage difference across the first and second nodes at a frequency which contains a harmonic of the input frequency, and a second stage including a second differential pair of amplifier elements coupled at the harmonic of the input frequency with the first and second nodes to amplify differentially the voltage difference and produce an output signal at the harmonic of the input frequency. Radio frequency connections apply the voltage difference across the first and second nodes at the frequency of the harmonic to the second differential pair of amplifier elements and block direct current, and separate direct current connections connect respectively the first differential pair of amplifier elements and the second differential pair of amplifier elements across the bias voltage supply terminals. | 09-08-2011 |
| 20110215842 | PROGRAMMABLE DIGITAL CLOCK SIGNAL FREQUENCY DIVIDER MODULE AND MODULAR DIVIDER CIRCUIT - A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output. | 09-08-2011 |
| 20110214129 | MANAGEMENT OF MULTIPLE RESOURCE PROVIDERS - A device receives a request for an amount of a resource. It determines for each resource provider in a set of resource providers a current load, a requested load corresponding to the requested amount of the resource, and an additional load corresponding to an expected state of an application. It determines for each of the resource providers an expected total load on the basis of the current load, the requested load, and the additional load. It subsequently selects from the set of resource providers a preferred resource provider on the basis of the expected total loads. The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device. | 09-01-2011 |
| 20110213992 | METHOD OF WAKING PROCESSOR FROM SLEEP MODE - A method and apparatus for storing and classifying packets transmitted over a network to a processor in a low power mode. The processor receives and classifies the packets as interesting or not interesting. Uninteresting packets are discarded while interesting packets are stored in memory. For the first interesting packet received, a receive timer is activated and for every interesting packet received a counter is incremented. A transmit timer is activated when the processor enters the low power mode. When either the receive timer expires, the transmit timer expires or the counter reaches a threshold value then a wake-up interrupt is asserted. | 09-01-2011 |
| 20110212341 | LEAD FRAME SHEET - A lead frame sheet made of an electrically conductive material has lead frames integrally formed on it. Spacing members also are formed from the sheet. A first one of the spacing members is proximal to a first longitudinal edge of the sheet and a second one of the spacing members is proximal to a second longitudinal edge of the sheet. The spacing members extend from an underside surface of the sheet and, in use, space the underside surface from a planar support such as a surface of a heating block. | 09-01-2011 |
| 20110211382 | HIGH DENSITY AND LOW VARIABILITY READ ONLY MEMORY - A read-only memory for storing two data values using a single transistor includes a word line, a pair of bit lines, a select line, and a transistor to store data corresponding to each bit lines in the pair of bit lines. The gate terminal of the transistor is connected to the word line, a first diffusion terminal of the transistor is connected to one of the first bit line and the select line based on the first data value and a second diffusion terminal of the transistor is connected to one of the second bit line and the select line based on the second data value. | 09-01-2011 |
| 20110210755 | OBJECT DETECTION DEVICE WITH VARIABLE SENSITIVITY ELECTRIC FIELD MEASUREMENT CIRCUIT - Three or more electrodes are arranged on either a window frame or window glass of an automobile. An electric field measurement unit measures the capacitance between various combinations of the electrodes to detect whether an object is located between the window frame and window glass. | 09-01-2011 |
| 20110210709 | MULTIMODE VOLTAGE REGULATOR AND METHOD FOR PROVIDING A MULTIMODE VOLTAGE REGULATOR OUTPUT VOLTAGE AND AN OUTPUT CURRENT TO A LOAD - A multimode voltage regulator comprises an output for providing a regulator output voltage Vdd and an output current to a load and a low power reference voltage source having a reference voltage output providing the regulator output voltage Vdd, when in a first low power mode the output current is not greater than a threshold value. It may comprise a buffer amplifier having an output providing the regulator output voltage Vdd, when the output current is greater than the threshold value and a first bias voltage input being connected in a second low power mode to the reference voltage output when the output current is greater than the threshold value for less than a predefined time. And it may comprise a mode controller for automatically determining the output current and automatically switching from first low power mode to second low power mode. | 09-01-2011 |
| 20110210395 | TRANSISTORS WITH IMMERSED CONTACTS - Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. | 09-01-2011 |
| 20110208467 | CALIBRATION STANDARDS AND METHODS OF THEIR FABRICATION AND USE - An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer conductive structure positioned to one side of the inner conductive structure, and a second outer conductive structure positioned to an opposite side of the inner conductive structure. The inner and outer conductive structures are aligned in parallel with each other along offset principal axes of the inner and outer conductive structures. The conductive end structure is electrically connected between an end of the first outer conductive structure and an end of the second outer conductive structure, and the conductive end structure is spatially separated from an end of the inner conductive structure at the surface of the substrate. | 08-25-2011 |
| 20110205105 | INTEGRATED CIRCUIT, COMMUNICATION UNIT AND METHOD FOR PHASE COMPENSATION - A communication unit comprises a controller and a radio frequency signal path having a plurality of delay elements operably coupled to a series of respective amplifier stages, wherein the controller is arranged to individually enable the respective amplifier stages. In response thereto a number of the plurality of delay elements are selectively inserted into or by-passed from the radio frequency signal path thereby adjusting a phase shift applied to signals provided through the radio frequency signal path. | 08-25-2011 |
| 20110204498 | LEAD FRAME AND SEMICONDUCTOR PACKAGE MANUFACTURED THEREWITH - A lead frame for a semiconductor package has a flag to which a semiconductor die is mounted. Tie bars are coupled to the flag. There is a first set of leads and each first set lead in the first set of leads has a first set lead parallel length and a first set lead tapered length. The first set lead parallel length of each first set lead has a constant width and edges that are parallel to edges of all other first set lead parallel lengths. A free end region of the first set lead tapered length of each first set lead provides a first set lead bond target region. There is a second set of leads disposed between a first one of the tie bars and the first set of leads. Each second set lead, in the second set of leads, has a second set lead parallel length and a second set lead tapered length. The second set lead parallel length of each second set lead has a constant width and edges that are parallel to edges of all other second set lead parallel lengths in the second set of leads and also parallel to the edges of first set lead parallel lengths. At least one second set lead has an extension length extending inwardly from the second set lead tapered length, the extension length has a constant width and provides a second set lead bond target region. Wire bond leads electrically couple both the first set lead bond target region and second set lead bond target region to respective die external electrical connection pads on a surface of the die and a package body encloses the die. | 08-25-2011 |
| 20110201296 | MIXER CIRCUITS FOR SECOND ORDER INTERCEPT POINT CALIBRATION - A balanced mixer circuit ( | 08-18-2011 |
| 20110201288 | DEVICE INCLUDING AN ANTENNA AND METHOD OF USING AN ANTENNA - An integrated package is disclosed that includes a conductive structure that can be selectively configured to include a radiating element of a planar antenna or to include a radio-frequency shielding structure. Examples of a planar antenna include PIFA antennas, patch antennas, and the like. The planar antenna can be selectively configured to different tuning profiles, and operate as a diversity antenna by alternating its tuning profile configuration amongst different tuning profiles. | 08-18-2011 |
| 20110201284 | DC OFFSET CALIBRATION IN A DIRECT CONVERSION RECEIVER - A direct conversion receiver ( | 08-18-2011 |
| 20110199159 | METHOD AND APPARATUS FOR GENERATING A CLOCK SIGNAL - An integrated circuit comprising oscillator circuitry is arranged to generate a clock signal for functional logic module of the integrated circuit. The oscillator circuitry comprises a plurality of propagation paths, and is arranged to apply a transition signal to inputs of the plurality of propagation paths, and to cause the output clock signal to transition based on a propagation of the transition signal through a determined set of the propagation paths. | 08-18-2011 |
| 20110199139 | FLIP-FLOP CIRCUIT WITH INTERNAL LEVEL SHIFTER - A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal. | 08-18-2011 |
| 20110195556 | POWER MOSFET WITH A GATE STRUCTURE OF DIFFERENT MATERIAL - A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage. | 08-11-2011 |
| 20110193648 | PULSE WIDTH MODULATION WITH EFFECTIVE HIGH DUTY RESOLUTION - A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The PWM signal generator receives an N-bit value representing a duty to be implemented and sets values X and Y to the M least significant bits and the N-M most significant bits, respectively, of the N-bit value. The value M can be determined based on the value N and a maximum implementable frequency of a clock signal used to time the generation of each PWM cycle. The PWM signal generator generates a cycle window of 2 | 08-11-2011 |
| 20110193605 | DUTY TRANSITION CONTROL IN PULSE WIDTH MODULATION SIGNALING - A pulse width modulation (PWM) signal generator generates a PWM signal with an adjustable PWM duty based on a programmable or otherwise adjustable value. In response to a change or update to this value, the PWM signal generator initiates a duty transition process that generates a series of groups of PWM cycles that gradually transition from the original duty to the new duty. Each group includes a corresponding set of a predetermined number of PWM cycles that is repeated one or more times over a predetermined duration for the group. Each set has a certain proportion of PWM cycles having the new duty to PWM cycles having the original duty, whereby the proportion increases for each successive group of the series. This gradual transition in the PWM signal from the original duty to the new duty effectively provides an effective higher duty resolution for the PWM signal generator during the duty transition. | 08-11-2011 |
| 20110193237 | METHOD FOR MAKING SEMICONDUCTOR PACKAGE - A method for assembling a semiconductor package includes a rapid cooling step after post mold curing of an encapsulation material. The rapid cooling step includes blowing chilled, compressed air over the package for about two minutes. The rapid cooling step does not require any clamping pressure be simultaneously applied to the package. The rapid cooling step reduces a temperature of the encapsulation material from a curing temperature to the cooled temperature within a maximum period of less than five minutes. By using rapid cooling, as opposed to cooling the package under a clamping pressure with ambient air, package warpage due to CTE mismatches is prevented. | 08-11-2011 |
| 20110193207 | LEAD FRAME FOR SEMICONDUCTOR DIE - A lead frame for providing electrical interconnection to a semiconductor die has a generally rectangular flag area having first and second major surfaces and four sides. The flag area is sized and shaped to receive a semiconductor die on one of the first and second major surfaces. A first row of leads is located adjacent to a first one of the four sides of the flag area and a second row of leads is located adjacent to a second one of the four sides of the flag area, where the second one of the four sides is adjacent to the first one of the four sides. The remaining two sides do not have any adjacent leads. | 08-11-2011 |
| 20110191401 | CIRCUIT AND METHOD FOR CHOLESKY BASED DATA PROCESSING - A method for Cholesky based processing of data includes receiving a first matrix that equals a product of a first lower triangular matrix and a first upper triangular matrix, where the first upper triangular matrix is a complex conjugate transpose of the first lower triangular matrix, and applying, by a processing unit that has a set of P processors, a loopless Cholesky factorization process on each equally sized block of multiple equally sized blocks of the first matrix to provide the first lower triangular matrix. Each equally sized block has E elements, where E is a integer multiple of P. | 08-04-2011 |
| 20110189823 | METHOD OF MAKING SEMICONDUCTOR PACKAGE WITH IMPROVED STANDOFF - A no-lead type semiconductor package is formed by attaching a die to a top surface of a flag of a lead frame and then taping a bottom surface of the flag and leads of the lead frame. Die bonding pads are connected to the leads with wires and then the assembly is put in a mold chase and encapsulated with a plastic material. The mold chase has protrusions between the flag and the leads of a lead frame, and between the leads themselves, which causes indentations to be formed between the leads and between the flag and the leads. The method is particularly useful for making quad flat no lead (QFN) devices and power-QFN type devices. | 08-04-2011 |
| 20110187396 | QUIESCENT CURRENT (IDDQ) INDICATION AND TESTING APPARATUS AND METHODS - An embodiment of an electronic device includes a logic circuit, a switching element, and a quiescent current (IDDQ) evaluation circuit. The logic circuit is coupled to a first ground node. The switching element is coupled between the first ground node and a second ground node. The switching element is configurable in an electrically non-conductive state when the electronic device is in an IDDQ evaluation state, and in an electrically conductive state when the electronic device is not in the IDDQ evaluation state. When the electronic device is in the IDDQ evaluation state, the IDDQ evaluation circuit is configured to provide a first output signal when an IDDQ indicating voltage across the first and second ground nodes exceeds a reference voltage. Other embodiments include methods for producing an indication of IDDQ in an electronic device and methods for fabricating an electronic device with the capability of producing an IDDQ indication. | 08-04-2011 |
| 20110185119 | PARITY GENERATOR FOR REDUNDANT ARRAY OF INDEPENDENT DISCS TYPE MEMORY - In a Redundant Array of Independent Discs (RAID) type memory, dual parities P and Q are generated by a dual XOR engine that performs a plain XOR operation for parity P and a weighted XOR operation for parity Q. The plain and weighted XOR operations may be performed in a single pass. | 07-28-2011 |
| 20110185102 | BUS BRIDGE AND METHOD FOR INTERFACING OUT-OF-ORDER BUS AND MULTIPLE ORDERED BUSES - A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses. A managing circuit, coupled to the shared memory unit and to the multiple ordered bus interfaces, is used to determine a readiness of each transaction request based on a dependency resolution attribute and a data readiness attribute associated with the transaction request, and for managing a dequeueing of ready transaction requests to the ordered bus interfaces based on an availability of the ordered bus interfaces. | 07-28-2011 |
| 20110183584 | METHOD AND APPARATUS FOR CONDITIONING A CMP PAD - The present invention relates to a method and apparatus for conditioning a polishing pad used in chemical mechanical polishing in which a consistent pressing force can be provided between an abrasive conditioning member and the polishing pad. Specifically, a moveable weight member is provided that can be selectively moved along a length of a support arm in the conditioning apparatus. The position of the weight member relative to the position at which the abrasive conditioning member is mounted alters the resultant pressing force in view of the change in moment created. In a particular example, the positioning of the weight member can be automatically controlled using a drive mechanism controlled by a control unit, such as a computer. In a more particular example, the positioning of the weight member can be dynamically controlled if the control unit receives an external feedback upon which its control of the weight member position is based, such as a detected value of the pressing force exerted by the abrasive conditioning member. Finally, if the apparatus is appropriately arranged to permit the weight member to travel to an opposite side of the location at which the support arm is mounted from the abrasive conditioning member, then a “negative pressing force” can be generated, such that effective pressing forces less than the resting weight of the pad conditioning apparatus can be realized. | 07-28-2011 |
| 20110182335 | CALIBRATION SIGNAL GENERATOR - A calibration signal generator for use in a balancing circuit calibration device in a radio receiver, the calibration signal generator comprising: a means of amplifying a clocking signal from a clocking signal generator to provide a first calibration signal; a means of generating a second calibration signal from the clocking signal, the first and second calibration signals being transmissible to a one or more mixing circuits in the balancing circuit calibration device; and a means synchronising the operation of other circuit elements in the balancing circuit calibration device with the clocking signal; characterised in that the clocking signal generator is present in the radio receiver and used therein for other functions. | 07-28-2011 |
| 20110181488 | ELECTRONIC DEVICE MODULE WITH INTEGRATED ANTENNA STRUCTURE, AND RELATED MANUFACTURING METHOD - An electronic device module as described herein includes an electronic device package having device contacts. The electronic device package is fixed within encapsulating material, along with an electrically conductive ground layer. The ground layer has a device opening in which the electronic device package resides, and the ground layer also has an antenna opening spaced apart from the device opening. The device contacts and one side of the ground layer correspond to a first surface, and a patch antenna element overlies the first surface. The antenna element is coupled to the electronic device package, and a projection of the patch antenna element onto the first surface resides within the antenna opening. Also provided are methods for manufacturing such an electronic device module. | 07-28-2011 |
| 20110181331 | INTEGRATED CIRCUIT WITH LEAKAGE REDUCTION IN STATIC NETS - A method for reducing leakage current of a delay line on a static net is provided. The static net provides a signal communication path between a data output of a first flip-flop and a data input of a second flip-flop via the delay line. The delay line is designed using standard cells but the standard cells are selected based on leakage power consumption in order to reduce the leakage power consumption of the delay line. | 07-28-2011 |
| 20110181264 | CONTROLLER FOR BUCK AND BOOST CONVERTER - A PWM controller for adjusting an output voltage of a buck and boost converter includes a first saw wave generator, which generates a first saw wave in accordance with the level of the output voltage. A first comparator coupled to the first saw wave generator compares the first saw wave with a first reference voltage and generates a first pulse. A peak hold circuit coupled to the first saw wave generator holds a peak value of the first saw wave. A second saw wave generator coupled to the peak hold circuit generates a second saw wave having a lower limit value that is the peak value of the first saw wave. A second comparator coupled to the second saw wave generator compares the second saw wave with the first reference voltage and generates a second pulse. | 07-28-2011 |
| 20110180917 | MICROELECTRONIC ASSEMBLY WITH AN EMBEDDED WAVEGUIDE ADAPTER AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate ( | 07-28-2011 |
| 20110180883 | METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE - A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions. | 07-28-2011 |
| 20110180876 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device comprises a switching element. The switching element comprises a first channel terminal, a second channel terminal and a switching terminal. One of the first and second channel terminals provides a reference terminal and the switching element is arranged such that an impedance of the switching element between the first channel terminal and second channel terminal is dependant upon a voltage across the switching terminal and the reference terminal. The semiconductor device further comprises a first resistance element operably coupled between the first channel terminal and the switching terminal and a second resistance element operably coupled between the switching terminal and the second channel terminal of the semiconductor device. When a negative current is encountered at the first channel terminal, the negative current causes both a voltage drop across the switching terminal and the first channel terminal and a voltage drop across the second channel terminal and the switching terminal. | 07-28-2011 |
| 20110179325 | SYSTEM FOR BOUNDARY SCAN REGISTER CHAIN COMPRESSION - A system for testing input/output pads of an integrated circuit includes boundary scan register chains, a test control unit and a test data processing unit. Input test data is provided to the test control unit, which then provides the test data to the test data processing unit. The test data processing unit processes the test data to obtain processed test data. Thereafter, the processed data is loaded in each of the boundary scan register chains in parallel. The processed test data is propagated sequentially through the plurality of boundary scan register chains to obtain output test data. The output test data is used to detect faults present in the input/output pads of the integrated circuit. | 07-21-2011 |
| 20110176646 | METHOD AND SYSTEM FOR DETERMINING BIT STREAM ZONE STATISTICS - An input bit stream is received and zone statistics such as zones count, zones center bit positions, and zones lengths are determined, where a zone is a set of non-transitioning bits in the input bit stream. Beginning and ending bit positions for each zone are determined simultaneously, and each beginning bit position is associated with an ending bit position. Zone statistics are calculated using the determined beginning and appropriate ending bit positions. | 07-21-2011 |
| 20110176244 | ESD PROTECTION DEVICE AND METHOD - An electrostatic discharge (ESD) protection clamp ( | 07-21-2011 |
| 20110176243 | STACKED ESD PROTECTION - A stacked electrostatic discharge (ESD) protection clamp ( | 07-21-2011 |
| 20110175758 | SYSTEM AND METHOD FOR REMOVING GLITCHES FROM A BIT STREAM - A bit stream is received and each bit corresponding to the bit stream is over-sampled to generate a first set of data samples. Each data sample from the first set of data samples is compared with a corresponding immediate previous data sample to generate a second set of data samples. The second set of data samples is compared with bit masks, and accordingly, some of the data samples in the first set of data samples are identified for replacement. Further, a substitute data sample is selected from the first set of data samples based on a predefined criterion and some of the data samples in the first set of data samples are replaced with the substitute data sample. | 07-21-2011 |
| 20110175680 | WIRELESS COMMUNICATION DEVICE AND SEMICONDUCTOR PACKAGE DEVICE HAVING A POWER AMPLIFIER THEREFOR - A semiconductor package device comprises a first amplifier block, at least one further amplifier block operably coupled in parallel with the first amplifier block between a common input and a common output, and at least one stabilisation network operably coupled between a node of the first amplifier block and a corresponding node of the at least one further amplifier block. The at least one stabilisation network comprises an inductance operably coupled between the corresponding nodes of the first and at least one further amplifier blocks, and a capacitance operably coupling a mid-point of the inductance to a ground plane. | 07-21-2011 |
| 20110175643 | METHOD AND APPARATUS FOR HANDLING AN OUTPUT MISMATCH - A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyse internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronise the first and at least one further signal processing logic module. | 07-21-2011 |
| 20110175592 | BUS DRIVER FOR AVOIDING AN OVERVOLTAGE - An electrical circuit for manipulating at least one of a voltage and a current on a bus wire comprises a first switch having a first gate, a first source, and a first potential reduction unit. The first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is caused by a shutting-off of a first control voltage. | 07-21-2011 |
| 20110175212 | DUAL DIE SEMICONDUCTOR PACKAGE - A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die. The electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections. Also, at least part of a base surface of the lead frame flag directly under the second semiconductor die is left exposed by the package body and provides a heat sink. | 07-21-2011 |
| 20110175199 | ZENER DIODE WITH REDUCED SUBSTRATE CURRENT - A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region. | 07-21-2011 |
| 20110175198 | ESD PROTECTION WITH INCREASED CURRENT CAPABILITY - A stackable electrostatic discharge (ESD) protection clamp ( | 07-21-2011 |
| 20110175190 | DEEP WELL STRUCTURES WITH SINGLE DEPTH SHALLOW TRENCH ISOLATION REGIONS - A semiconductor device structure includes a first type region and a second type region defined in a substrate, the first type region and second type region separated by one or more inter-well shallow trench isolation (STI) structures. At least one of the first type region and the second type region has one or more intra-well STI structures formed therein for isolating semiconductor devices formed within a same polarity well. The inter-well STI structures are formed at a substantially same depth with respect to the intra-well STI structures. A main well region is formed such that a bottom of the main well region is disposed above a bottom of the inter-well and intra-well STI features. One or more deep well regions couple the main well regions otherwise isolated by the intra-well STI structures, wherein the deep well regions are spaced away from the inter-well STI structures. | 07-21-2011 |
| 20110174074 | FRAMED TRANSDUCER DEVICE - A MEMS device ( | 07-21-2011 |
| 20110173373 | NON-VOLATILE MEMORY DEVICE AND METHOD THEREFOR - A method of storing information at a non-volatile memory includes storing a first status bit at a sector header of the memory prior to erasing a sector at the memory. A second status bit is stored after erasing of the sector. Because the erasure of the sector is interleaved with the storage of the status bits, a brownout or other corrupting event during erasure of the record will likely result in a failure to store the second status bit. Therefore, the first and second status bits can be compared to determine if the data was properly erased at the non-volatile memory. Further, multiple status bits can be employed to indicate the status of other memory sectors, so that a difference in the status bits for a particular sector can indicate a brownout or other corrupting event. | 07-14-2011 |
| 20110173312 | DATA PROCESSING - A data processing apparatus is provided that includes a processing unit for processing data, including receiving data packets from a sender and sending acknowledgements to the sender, the processing unit having a first and second mode of operation for processing data, in which the second mode of operation requires more power than the first mode, and the processing unit switches between the first and second modes of operation based on a processing load; a metric module for determining a metric indicative of the processing load; an acknowledgement module for sending one acknowledgement in respect of n received data packets; and an acknowledgement configuration module for setting n to be a value m greater than a first predetermined value if the metric lies in a predetermined range that includes a value that the metric assumes when the processing unit switches between the first mode of operation and the second mode of operation, and to the first predetermined value otherwise. | 07-14-2011 |
| 20110170644 | METHOD FOR CLOCK AND DATA RECOVERY - An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phases corresponding to the one or more sets of non-transitioning phases are identified and then a final center phase that accurately represents the bits belonging to the input bit stream is selected. The data samples corresponding to the final center phase are extracted, thereby recovering the clock signal and data bits from the input bit stream. | 07-14-2011 |
| 20110169575 | AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT THEREFOR - An amplifier circuit on a single die comprises a low voltage amplifier with a first common mode voltage and having an input and an output. A power amplifier has a second common mode voltage whose input is operably coupled to an output of the low voltage amplifier. The first common mode voltage and second common mode voltage are unequal. A compensation circuit is operably coupled to an input of the power amplifier and arranged to inject a DC-current or apply a common mode voltage into the power amplifier that is representative of a difference between the first common mode voltage and the second common mode voltage. | 07-14-2011 |
| 20110169553 | TEMPERATURE COMPENSATED CURRENT REFERENCE CIRCUIT - A temperature compensated current reference circuit has a differential amplifier and a first feedback transistor with a gate coupled to the differential amplifier output. The first feedback transistor couples a supply voltage line to an inverting input of the differential amplifier. There is also a second feedback transistor with a gate coupled to the differential amplifier output, which couples the supply voltage line to a non-inverting input of the differential amplifier. A first temperature dependent conductor couples the inverting input to ground. A primary reference resistor and a second temperature dependent conductor are connected in series and couple the non-inverting input to ground. An output current control transistor has a gate and one other electrode coupled together and a third electrode coupled to the supply voltage line. A secondary reference resistor and a conductivity change sensing transistor are connected in series and couple the gate of the output current control transistor to ground. The conductivity change sensing transistor has a gate coupled to the second one of the two differential inputs. There is a temperature compensation current reference output circuit that has a current reference transistor, an input coupled to the differential amplifier output and another input is coupled to the gate of the output current control transistor. | 07-14-2011 |
| 20110169528 | CLOCK BUFFER CIRCUIT - A clock buffer for a clock network that reduces leakage current and lowers power consumption. The clock buffer includes a first CMOS transistor, a second CMOS transistor, and a leakage current prevention circuit connected to the first and second CMOS transistors. The leakage current prevention circuit includes a first PMOS transistor, which is connected between the source of a PMOS transistor of the first CMOS transistor and a power supply line, and a second PMOS transistor, which is connected between the source of a PMOS transistor of the second CMOS transistor and the power supply line. The first and second PMOS transistors are deactivated in response to an enable signal generated when a circuit block does not require the clock signal. The first and the second PMOS transistors have predefined widths and lengths such that the addition of these transistors in series with the CMOS transistors does not increase the propagation delay of the clock buffer circuit. Deactivating the first and second PMOS transistors disconnects the CMOS transistors from the power supply line, which prevents current leakage. | 07-14-2011 |
| 20110169096 | BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS - An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor. | 07-14-2011 |
| 20110169078 | SWITCH MODE CONVERTER EMPLOYING DUAL GATE MOS TRANSISTOR - A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions. | 07-14-2011 |
| 20110167396 | DESIGN PLACEMENT METHOD AND DEVICE THEREFOR - An instantiation of a standard cell is placed at a location of a device design. The standard cell includes a designation identifying a sensitive feature of the standard cell. An instantiation of a filler cell is placed at a selective location of the device design based on the designation. | 07-07-2011 |
| 20110167310 | SCAN BASED TEST ARCHITECTURE AND METHOD - An integrated circuit architecture including architecture for a scan based test, where the integrated circuit includes N scan chain sets including one or more scan chains and an input register bank. The input register bank includes an input for serially receiving an N-bit input vector synchronous with a first clock signal, and N-outputs configured to substantially simultaneously provide the N-bits of the received input vector as N separate output bits. The N separate output bits are used to provide test bits for simultaneously shifting into the respective inputs of the scan chain set synchronous with a second clock signal. | 07-07-2011 |
| 20110167185 | METHOD AND APPARATUS FOR TRANSMITTING DATA - A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized. | 07-07-2011 |
| 20110165729 | METHOD OF PACKAGING SEMICONDUCTOR DEVICE - Quad Flat No-Lead packaged devices are manufactured using two singulation operations with two different saw blades of varying widths with the first singulation operation using a wider saw blade than the second singulation operation. Between singulation operations, the exposed portions of the leads are plated with a solderable metal. By performing the second singulation operation within the first cut made by the first singulation, at least half of the exposed metal of the leads remains plated. Thus, better solder joints may be formed, which allows for simpler visual inspection. | 07-07-2011 |
| 20110164626 | METHOD FOR ADJUSTING TIME SLOTS IN A COMMUNICATION NETWORK - A communication network for providing media arbitration via a communications protocol using consecutive communication slots in a communication network. The communication network comprises a plurality of communication nodes, each node arranged for communicating frames of data with the other nodes during a dynamic segment comprising dynamic communication slots with respective communication slot numbers. Each of the plurality of communication nodes includes a time base comprising consecutive timeslots, associated with the dynamic communication slots, each timeslot comprises a transmission action point located such that transmission of each frame of data starts and ends at a transmission action point; a communication slot number controller, for adjusting a communication slot number if no communication is ongoing at the end of a time slot and to suspend adjusting the communication slot number if communication is ongoing at the end of a time slot, and a minislot counter for counting minislots while the incrementation of the communication slot counter is suspended, and a timing unit for determining a duration of a reception of frame, and a control unit for controlling the communication slot number controller to either continue adjusting of the slot number if the determined duration of the reception is above a certain threshold or to continue adjusting of the slot number using the value obtained with the minislot counter if the determined duration of the reception is below a certain threshold, and a transmission suppression unit for suppressing transmission in dynamic slots that follow a dynamic slot in which the determined duration of the reception is below a certain threshold. | 07-07-2011 |
| 20110164624 | METHOD AND APPARATUS FOR TRANSMITTING DATA - A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data. | 07-07-2011 |
| 20110163782 | FLEXIBLE BUS DRIVER - A bus driver has a ground terminal and a first and a second terminal. In a first operation mode the bus driver provides at the first terminal a first output voltage comprising a first data signal; and at the second terminal the bus driver provides a second output voltage comprising a second data signal. In a second operation mode the bus driver provides at the first terminal a first output voltage comprising a third data signal; and at the second terminal the bus driver provides a second output voltage, wherein a curve of the second output voltage is synchronous however inverted in relation to a curve of the first output voltage. An engine comprises a bus driver as set out above. | 07-07-2011 |
| 20110163360 | METHOD FOR FORMING A TRANSISTOR HAVING GATE DIELECTRIC PROTECTION AND STRUCTURE - A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure. | 07-07-2011 |
| 20110158303 | WAKE-UP CONTROL SYSTEM AND METHOD FOR CONTROLLING RECEIVER WAKE-UP - A wake-up control system comprises a plurality of different signal analyzer units. The plurality of different signal analyzer units may process a value of a different parameter of an incoming signal received at an input of a receiver and provide a false wake-up indication for the parameter when the value of the parameter is outside an acceptance range for the value. The system further comprises an evaluation unit connected to the plurality of different signal analyzer units for receiving the false wake-up indications. The evaluation unit may provide a false wake-up parameter information identifying an identified parameter of the different parameters when a sum of the false wake-up indications is outside an occurrence range for the false wake-up indications for the identified parameter. | 06-30-2011 |
| 20110156752 | METHOD AND APPARATUS FOR GATING A CLOCK SIGNAL - A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic. The polarity comparison logic and the selector logic being further arranged such that, upon the enable signal transitioning from an active state to an inactive state, the selected clock signal provided to the clock freezing logic comprises a polarity substantially equivalent to that of the gated clock signal. | 06-30-2011 |
| 20110156266 | METHODS FOR FORMING THROUGH-SUBSTRATE CONDUCTOR FILLED VIAS, AND ELECTRONIC ASSEMBLIES FORMED USING SUCH METHODS - Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit. | 06-30-2011 |
| 20110156051 | SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTTKY CONTACTS - Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced. | 06-30-2011 |
| 20110154344 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DEBUGGING A SYSTEM - A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable. | 06-23-2011 |
| 20110151804 | SEMICONDUCTOR DEVICE, WIRELESS COMMUNICATION DEVICE AND METHOD FOR GENERATING A SYNTHESIZED FREQUENCY SIGNAL - A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto. | 06-23-2011 |
| 20110151659 | MULTILAYERED THROUGH A VIA - A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV. | 06-23-2011 |
| 20110150141 | COMPUTATIONAL GENERATION OF NARROW-BANDWIDTH DIGITAL SIGNALS - A signal shaper generates an output signal representing a binary sequence, the output signal being the time-dependence of a signal value F. The signal shaper is input a first signal value F | 06-23-2011 |
| 20110149082 | DATA PACKET FREQUENCY - A method of determining a representative frequency for data packets, each data packet having an associated time, the method comprising: receiving a sequence of time-differentials, wherein a time-differential represents a difference between the time associated with a corresponding first data packet and the time associated with a corresponding second data packet; and determining the representative frequency based on the steps of: grouping a predetermined number N of the time-differentials into one or more groups based on the magnitudes of the N time-differentials; selecting one or more of the one or more groups for use in determining a representative time-differential; determining the representative time-differential as a function of the time-differentials of the selected one or more groups; outputting an inverse of the representative time-differential as the representative frequency. | 06-23-2011 |
| 20110147893 | BIPOLAR TRANSISTORS WITH HUMP REGIONS - By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required. | 06-23-2011 |
| 20110147835 | SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE - Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface. | 06-23-2011 |
| 20110145623 | SYSTEM ON A CHIP WITH CLOCK CIRCUITS - An embodiment of a system on a chip includes a reference clock circuit configured to produce a reference clock signal, a first clock circuit configured to produce a first clock signal, and adjustment circuitry. The adjustment circuitry is configured to make a determination of whether a characteristic of the reference clock signal compares unfavorably with a characteristic of the first clock signal, and when the characteristic of the reference clock signal compares unfavorably with the characteristic of the first clock signal, to adjust a parameter of the first clock circuit that results in tuning the first clock signal. | 06-16-2011 |
| 20110142169 | ELECTRONIC DEVICE, INTEGRATED CIRCUIT AND METHOD FOR SELECTING OF AN OPTIMAL SAMPLING CLOCK PHASE - An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation. | 06-16-2011 |
| 20110140240 | VARACTOR DIODES - An improved varactor diode is obtained by providing a substrate having a first surface and in which are formed a first N region having a first peak dopant concentration located at a first depth beneath the surface, and a first P region having a second peak dopant concentration greater than the first peak dopant concentration located at a second depth beneath the surface less than the first depth, and a second P region having a third peak dopant concentration greater than the second peak dopant concentration and located at a third depth at or beneath the surface less than the second depth, so that the first P region provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge of the second P region up to the second peak dopant concentration. | 06-16-2011 |
| 20110138090 | COMMUNICATING ON AN ELECTRICAL BUS - Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time. | 06-09-2011 |
| 20110136452 | WIRELESS COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD OF POWER CONTROL OF A POWER AMPLIFIER THEREFOR - A wireless communication unit comprising a transmitter having a power amplifier, a controller logic module arranged to control a power control value of the power amplifier and a closed loop control system operably coupled to the power amplifier and arranged to monitor a level of peak PA compression, wherein in response to the identified level of peak PA compression the controller logic module is arranged to automatically adjust a power amplifier power control value of the PA to obtain a predetermined level of peak PA compression. | 06-09-2011 |
| 20110133709 | VOLTAGE REGULATOR WITH LOW AND HIGH POWER MODES - A voltage regulator comprising at least first and second regulator elements connected between an output node and a supply rail for supplying load current to a load connected to the output node. The voltage regulator comprises first and second control modules for controlling the first and second regulator elements respectively to maintain the output node at a regulated voltage in the presence of a variable impedance presented by the load to the output node, the second regulator element and the second control module having a smaller load current capacity and smaller leakage current than the first regulator element and the first control module. The voltage regulator also comprises a mode selector for de-activating the first regulator element and the first control module in a first operational mode in response to a load current less than a threshold value, for activating the first regulator element and the first control module in a second operational mode in response to a load current greater than a threshold value, and an additional current-carrying path for carrying supplementary current for the first control module at least during a transition from the first operational mode to the second operational mode. | 06-09-2011 |
| 20110131356 | METHOD AND SYSTEM FOR HIGH-SPEED DETECTION HANDSHAKE IN UNIVERSAL SERIAL BUS BASED DATA COMMUNICATION SYSTEM - A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation. | 06-02-2011 |
| 20110131004 | DIE TEMPERATURE ESTIMATOR - A temperature estimation circuit for estimating a temperature of an integrated circuit die comprises a temperature increase estimation circuit, the circuit has one or more inputs operable to receive one or more notification signals corresponding to command signals passed to the integrated circuit, and an output providing a sum of one or more temperature increase values, corresponding to temperature increase of the integrated circuit due to one of the command signals. The circuit may further have a temperature decrease estimation circuit, comprising an input operable to receive a calculated die temperature value, and an output providing a temperature decrease value depending on a mathematical model of temperature decrease when no command signal is applied. The circuit may have a temperature calculation circuit, comprising a first input connected to the output of the temperature increase estimation circuit, a second input connected to the output of the temperature decrease estimation circuit, and an output providing the calculated die temperature value. | 06-02-2011 |
| 20110128807 | MEMORY DEVICE AND SENSE CIRCUITRY THEREFOR - A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled to the timing circuitry. The reference word line formed in the strap region. | 06-02-2011 |
| 20110128080 | VOLTAGE CONTROLLED OSCILLATOR (VCO) CIRCUIT WITH INTEGRATED COMPENSATION OF THERMALLY CAUSED FREQUENCY DRIFT - A voltage controlled oscillator circuit comprises a VCO resonator circuit having a first plurality of varactors for varying a frequency of the VCO resonator circuit the VCO resonator circuit being symmetrical with respect to VCO circuit ground and providing a signal having a frequency, the frequency depending on a tuning voltage applied to the first plurality of varactors, and a second plurality of varactors for compensating a drift of the frequency depending on a compensation voltage, a temperature sensor circuit sensing an ambient temperature of the VCO resonator circuit and providing a temperature dependent signal, and a temperature compensation circuit providing the compensation voltage depending on the temperature dependent signal. Furthermore, a phase locked loop (PLL) circuit, an automotive radar device and a method for compensating a frequency drift of a VCO resonator circuit are presented. | 06-02-2011 |
| 20110128051 | Programmable Clock Divider - In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal. | 06-02-2011 |
| 20110126632 | LATERALLY INTEGRATED MEMS SENSOR DEVICE WITH MULTI-STIMULUS SENSING - A microelectromechanical systems (MEMS) sensor device ( | 06-02-2011 |
| 20110125945 | COMMUNICATIONS MODULE APPARATUS, INTEGRATED CIRCUIT AND METHOD OF COMMUNICATING DATA - A communications module apparatus for an automotive network comprises an input for receiving data to be transmitted. The apparatus also comprises a first output for coupling to a first bus line and a second output for coupling to a second bus line. An alternating voltage signal transmission circuit for transmitting at least part of the received data is also provided. The alternating voltage signal transmission circuit is coupled to the first output and the second output. | 05-26-2011 |
| 20110124309 | HETERODYNE RECEIVER - A down-conversion module for a heterodyne receiver comprises a first mixer circuit, a second mixer circuit and an interconnection. The first mixer circuit includes first and second differential control terminals and is arranged to produce a first down-converted differential voltage signal at a first down-converted frequency as a function of a first RF differential input signal applied to the first differential control terminals and of a first RF differential reference frequency signal applied to the second differential control terminals. The second mixer circuit includes two differential pairs of second amplifier elements and the second amplifier elements comprise second differential control terminals and cross-connected pairs of second amplifier output paths for producing a second down-converted differential voltage signal at a second down-converted frequency as a function of the first down-converted differential voltage signal and of a second RF differential reference frequency signal applied to the second differential control terminals. The interconnection includes transmission line elements and is arranged to apply a differential current signal which is a function of the first down-converted differential voltage signal to differential input terminals of the second mixer circuit common to respective pairs of the second amplifier elements. | 05-26-2011 |
| 20110122936 | INTEGRATED TESTING CIRCUITRY FOR HIGH-FREQUENCY RECEIVER INTEGRATED CIRCUITS - An integrated circuit comprises a receiver and an oscillator circuit. The receiver has a first input port for receiving a first oscillatory input signal, a second input port for receiving a second oscillatory input signal, and an output port for delivering an oscillatory output signal which is a function of both the first input signal and the second input signal. The oscillator circuit has a first output port for delivering a first oscillatory signal, and a second output port for delivering a second oscillatory signal. The first output port of the oscillator circuit is coupled to the HF port, and the second output port of the oscillator circuit is coupled to the LO port. The integrated circuit may be designed such that the HF port may be disconnected from the first output port of the oscillator circuit without affecting the operability of the receiver. An apparatus for testing the proper functioning of an integrated circuit as described above and a method of producing a receiver are also disclosed. The method may facilitate testing a receiver die during production. In particular it may avoid the need for feeding high-frequency signals from an external apparatus to the die. | 05-26-2011 |
| 20110122921 | LOW POWER, HIGH RESOLUTION TIMING GENERATOR FOR ULTRA-WIDE BANDWIDTH COMMUNICATION SYSTEMS - A data communication method is provided, comprising: processing high-speed digital data for communication to produce processed data; generating short impulse wavelets; constructing a digitally modulated ultra wideband signal from the short impulse wavelets in response to bits of the processed data, wherein the digitally modulated ultra wideband signal comprises a series of the short impulse wavelets, and the value of each bit of the processed data is digitally modulated onto the shape of at least one of the short impulse wavelets of the series, to produce a series of digitally shape modulated impulse wavelets; and transmitting the digitally modulated ultra wideband signal, including the series of digitally shape modulated impulse wavelets, via an antenna. | 05-26-2011 |
| 20110121872 | SEMICONDUCTOR DEVICE, WIRELESS COMMUNICATION DEVICE AND METHOD FOR GENERATING A SYNTHESIZED FREQUENCY SIGNAL - A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to generate a synthesized frequency signal from the reference signal. The synthesized frequency generation logic comprises programmable divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period substantially equal to N times that of the reference signal, where N comprises a programmable integer value. The synthesizer frequency generation logic is arranged to generate the synthesized frequency signal comprising a frequency with a period substantially equal to 1/M that of the divided signal, where M comprises a further programmable integer value. | 05-26-2011 |
| 20110121865 | SYSTEMS AND METHODS FOR DETECTING INTERFERENCE IN AN INTEGRATED CIRCUIT - Apparatus, systems and methods are provided for protecting a processing system from electromagnetic interference. An integrated circuit comprises a sensing arrangement configured to sense an interference signal and an interference detection module coupled to the sensing arrangement. The interference detection module is configured to detect when a power level associated with the interference signal is greater than a threshold value. In one embodiment, the interference detection module generates an interrupt for a processing system when the power level associated with the interference signal is greater than the threshold value. | 05-26-2011 |
| 20110121818 | INTEGRATED CIRCUIT DIE, AN INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR CONNECTING AN INTEGRATED CIRCUIT DIE TO AN EXTERNAL DEVICE - An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals. | 05-26-2011 |
| 20110121809 | VOLTAGE REFERENCE CIRCUIT - A bandgap voltage reference unit on an integrated circuit ( | 05-26-2011 |
| 20110121761 | SYNCHRONIZED PHASE-SHIFTED PULSE WIDTH MODULATION SIGNAL GENERATION - A pulse width modulation (PWM) signal generator generates multiple output PWM signals from an input PWM signal. The output PWM signals are synchronized to synchronization events. Each output PWM signal has a duty ratio substantially equal to the duty ratio of the input PWM signal, and each output PWM signal has a fixed phase-shift in relation to the other output PWM signals. The PWM signal generator samples an input PWM cycle to determine sample parameters representative of its duty ratio. The sample parameters are then used to generate a corresponding output PWM cycle for each of the output PWM signals. In response to a synchronization event, the PWM signal generator prematurely terminates the current PWM cycle and initiates the next PWM cycle while ensuring that the portion of the current output PWM cycle completed by the leading output PWM signal up to the point of the premature termination is replicated for the corresponding output PWM cycles of the other non-leading output PWM signals. | 05-26-2011 |
| 20110121656 | Systems and methods for delivering power in response to a connection event - Systems and methods are provided for delivering power from a first energy source to a second energy source. An electrical system for delivering power from a first energy source to a second energy source comprises an interface configured to be coupled to the second energy source, a switching element coupled between the first energy source and the interface, and a processing system coupled to the switching element and the interface. The processing system is configured to identify a connection event based on an electrical characteristic of the interface that is indicative of the interface being coupled to the second energy source and operate the switching element to provide a path for current from the first energy source in response to identifying the connection event. | 05-26-2011 |
| 20110121468 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING SAME - An improved semiconductor package includes thermal tape placed over a top side of a die that is attached to a substrate with an underfill material. The tape extends to the substrate. The tape deforms with heat and entraps the die and underfill material. Air bubbles are trapped between the tape and the die and underfill material. The tape can be weighted and lined with an adhesive material. The tape aids in preventing the die from cracking due to mishandling. | 05-26-2011 |
| 20110121428 | HIGH GAIN TUNABLE BIPOLAR TRANSISTOR - An improved bipolar transistor ( | 05-26-2011 |
| 20110120784 | Methods and apparatus for performing capacitive touch sensing and proximity detection - Embodiments include methods and apparatus for performing capacitive touch sensing and proximity detection. Electrode selection circuitry establishes a first connection with an individual electrode of a plurality of individual electrodes in order to receive one or more first signals indicating a state of the individual electrode, and establishes second connections with a proximity electrode that comprises multiple ones of the plurality of individual electrodes in order to receive one or more second signals indicating a state of the proximity electrode. A processing system performs a first analysis on the first signals to determine whether to perform a first updating process for an individual electrode baseline value, and performs a second analysis on the second signals to determine whether to perform a second updating process for a proximity electrode baseline value. In an embodiment, the first analysis and the second analysis are different from each other. | 05-26-2011 |
| 20110119910 | METHOD AND SYSTEM FOR RELEASING A MICROELECTRONIC ASSEMBLY FROM A CARRIER SUBSTRATE - Methods and system for forming a microelectronic assembly ( | 05-26-2011 |
| 20110119533 | PROGRAM TRACE MESSAGE GENERATION FOR PAGE CROSSING EVENTS FOR DEBUG - A data processing system has a trace message filtering circuit. A method includes: receiving a current page address corresponding to a current instruction in a sequence of instructions; determining that the current page address is for a different page of memory than a previous page address corresponding to a previous instruction in the sequence of instructions; comparing the current page address with a plurality of page addresses stored in a message filtering circuit; and when the current page address is determined to be different than any of the plurality of page addresses, storing the current page address in the message filtering circuit. | 05-19-2011 |
| 20110116577 | SEMICONDUCTOR DEVICE WIRELESS COMMUNICATION UNIT AND METHOD FOR RECEIVING A SIGNAL - A semiconductor device comprising receiver circuitry arranged to receive a dual carrier RF signal comprising a first wanted component and a second wanted component. The receiver circuitry is arranged to down convert the received dual carrier RF signal to create a Very Low Intermediate Frequency, VLIF signal whereby the first wanted component of the received dual carrier signal is subsequently located at a positive VLIF offset with respect to DC, zero hertz, and the second wanted component of the received dual carrier signal is subsequently located at a negative VLIF offset with respect to DC. The semiconductor device further comprises a signal processing logic module arranged to receive the VLIF signal and to separate the first and second wanted components of the received signal. | 05-19-2011 |
| 20110116539 | METHOD AND APPARATUS FOR VIDEO DECODING WITH REDUCED COMPLEXITY INVERSE TRANSFORM - A method of reducing processing of fast inverse transform of an input transform block by a video decoder includes determining whether a block type is one of zero, DC, left, and top. If not, the inverse transform is performed and a residual video block is provided as residual information. When the block type is zero, inverse transform is bypassed. When the block type is DC, reduced complexity inverse transform of a DC coefficient is performing and a single residual coefficient is provided as residual information. When the block type is left, reduced complexity inverse transform of a left column of the input transform block is performed and a single column of residual coefficients is provided as residual information. When the block type is top, reduced complexity inverse transform of a top row is performed and a single row of residual coefficients is provided as residual information. | 05-19-2011 |
| 20110116497 | METHOD AND APPARATUS FOR DETECTING ONE OR MORE PREDETERMINED TONES TRANSMITTED OVER A COMMUNICATION NETWORK - An apparatus for detecting one or more predetermined tones transmitted over a communication network, each predetermined tone having a predetermined frequency, comprises a data memory for storing data including the predetermined frequency of each of the one or more predetermined tones, an input for receiving a signal transmitted over the communication network, and a frequency divider for dividing the received signal into at least two frequency sub bands so as to provide at least two components of the received signal in different frequency sub bands. The different frequency sub bands are selected based on the predetermined frequencies of the one or more predetermined tones. A frequency discriminator is arranged to determine a frequency of each tone in the at least two components and a decision logic block is arranged to provide an indication that a predetermined tone has been detected when the determined frequency of a tone in a component corresponds to the predetermined frequency of one of the one or more predetermined tones. | 05-19-2011 |
| 20110116328 | MEMORY DEVICE AND METHOD THEREOF - An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements. | 05-19-2011 |
| 20110115125 | METHOD AND APPARATUS FOR MOLDING SUBSTRATE - A method for encapsulating a substrate includes placing a hardened encapsulant material in a container. The encapsulant material is then heated and stirred until it is in a liquid or gel state. The liquid encapsulant material is held in the container in a vacuum state and dispensed over semiconductor dies along a guide, which allows the liquid encapsulant material to cool slightly before it covers a die. | 05-19-2011 |
| 20110114049 | FOUR STROKE SINGLE CYLINDER COMBUSTION ENGINE STARTING SYSTEM - A four stroke single cylinder combustion engine starting system with an electrical machine is operable as both a generator and a motor. The starting system has a single cylinder four stroke combustion engine. A piston of the engine is coupled to a shaft of the electrical machine. The starting system also has a motor driver having outputs coupled to the electrical machine. A controller is coupled to the driver and an ignition switch is coupled to the controller. In response to the controller receiving an ignition signal from the ignition switch, the driver controls the electrical machine to operate as a motor so that the electrical machine rotates in a reverse direction to move the piston in a reverse stroke cycle. After the piston reverses to a power stroke position of the reverse stroke cycle the driver controls electrical machine to rotate in a forward direction to move the piston in a forward stroke cycle to attempt to ignite the combustion engine. | 05-19-2011 |
| 20110113891 | APPARATUS AND METHODS FOR APPLYING STRESS-INDUCED OFFSET COMPENSATION IN SENSOR DEVICES - Apparatus and methods for applying stress-induced offset compensation and/or scale factor correction in sensor devices are provided. One sensor device ( | 05-19-2011 |
| 20110109602 | FAULT DETECTION APPARATUS FOR ALPHANUMERIC DISPLAY SYSTEM AND METHOD OF DETECTING A FAULT - A fault detection apparatus comprises a signal translation stage having an input arranged to receive an input waveform derived from a signal for a capacitive load. The signal translation stage is arranged to generate a translated output signal representative of at least an aspect of the input waveform. The apparatus also comprises a detection stage arranged to receive the translated output signal from the signal translation stage and analyse a first part and a second part of the translated output signal respectively corresponding to a first step function and a second step function, the first and second step functions being opposite in direction of transition. The analysis performed by the detection stage is a comparison of the first and second parts of the translated output signal respectively with an expected first part and an expected second part of the translated output signal. | 05-12-2011 |
