| FOUNDATION FOR ADVANCEMENT OF INTERNATIONAL SCIENCE Patent applications |
| Patent application number | Title | Published |
|---|
| 20110140276 | INTERLAYER INSULATING FILM, INTERCONNECTION STRUCTURE, AND METHODS OF MANUFACTURING THE SAME - This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF | 06-16-2011 |
| 20100038722 | MIS TRANSISTOR AND CMOS TRANSISTOR - A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate ( | 02-18-2010 |
| 20090309138 | Transistor and semiconductor device - An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×10 | 12-17-2009 |
| 20090283901 | Semiconductor device and multilayer wiring board - A gas or an insulating material having a relative dielectric constant of not more than 2.5 on average is interposed between a first wiring layer and a second wiring layer included in a multilayer wiring structure. Between a wiring of the first wiring layer and a wiring of the second wiring layer, a conductive connector is arranged. Between a predetermined wiring of the first wiring layer and a predetermined wiring of the second wiring layer, an insulating heat conductor having a relative dielectric constant of not more than 5 is arranged. | 11-19-2009 |
| 20090267122 | Semiconductor device and method of manufacturing the semiconductor device - A semiconductor device has a substrate, an insulator, an yttrium oxide film, a ferroelectric film (STN film), and an upper electrode. | 10-29-2009 |
| 20090250755 | Semiconductor Device - A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer. | 10-08-2009 |
| 20090166739 | Semiconductor Device - In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. | 07-02-2009 |
| 20090023231 | Semiconductor Device Manufacturing Method and Method for Reducing Microroughness of Semiconductor Surface - Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved. | 01-22-2009 |
| 20090001471 | Semiconductor Device - For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. | 01-01-2009 |
