FIDELIX CO., LTD. Patent applications |
Patent application number | Title | Published |
20150039807 | NOR-TYPE FLASH MEMORY DEVICE CONFIGURED TO REDUCE PROGRAM MALFUNCTION - Embodiments of the present invention include a NOR-type flash memory device capable of reducing or eliminating program malfunctions. In some embodiments, the device includes a memory array, row selection circuit, column selection circuit, and program driver circuit. The memory array includes a memory sector having a first sector bit line and a second sector bit line. The memory array also includes a plurality of flash memory cells disposed on a matrix structure having a plurality of cell bit lines and a plurality of word lines arranged sequentially. The cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order. The first cell bit lines are connected to the first sector bit line in response to column selection signals thereof, and the second cell bit lines are connected to the second sector bit line in response to column selection signals thereof. | 02-05-2015 |
20140233313 | FLASH MEMORY DEVICE REDUCING LAYOUT AREA - A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably. | 08-21-2014 |
20080276053 | Portable Device and Method for Controlling Deep Power Down Mode of Shared Memory - The memory device may include a first determination unit for determining whether entry into a DPD mode is to be made by interpreting signals received from a first processor, and generating and outputting a corresponding first DPD entry signal; a second determination unit for determining whether entry into the DPD mode is to be made by interpreting signals received from a second processor, and generating and outputting a corresponding second DPD entry signal; and a DPD determination unit for performing control for operation in the DPD mode only when the first DPD entry signal and the second DPD entry signal are respectively received from the first determination unit and the second determination unit. In accordance with the present invention, a single piece of memory operates in the DPD mode even when a plurality of processors shares the memory, so that power consumption can be minimized. | 11-06-2008 |