FCI INC. Patent applications |
Patent application number | Title | Published |
20130230129 | METHOD FOR COARSE FREQUENCY SYNCHRONIZATION IN OFDM RECEIVER - The present invention provides a method for coarse frequency synchronization in an OFDM receiver. Even if the maximum variation of crystal oscillator (X-TAL) frequency disturbance is maximized and most of the variation in crystal oscillator (X-TAL) frequency disturbance is vary small, the estimation or search method of the present invention is capable of rapidly and effectively terminating the estimation of the integral multiple frequency offset (IFO). The integral multiple frequency offset (IFO) candidate is ascendingly increased and descendingly reduced at one value interval. In the estimation IFO, the correlation peak value in the intermediate status is compared to the thresholds, the coarse frequency synchronization (CFS) acquisition directly is ended and ensured when the correlation peak value is greater than the threshold, and a confidence check is not performed when correlation peak value is less than the threshold for considerably reducing the acquisition time of the CFS. | 09-05-2013 |
20130107695 | ODFM RECEIVER | 05-02-2013 |
20120033764 | METHOD AND APPARATUS FOR AUDIO NOISE REDUCTION OF FREQUENCY MODULATION (FM) RECEIVER - A method and an apparatus for audio noise reduction of frequency modulation (FM) receiver are described. After receiving FM signal having pilot tone, pilot carrier sync detector performs pilot carrier synchronization detection of FM signal, FM demodulator demodulates synchronized FM signal, multiplex decoder decodes audio signal of demodulated FM signal for outputting the decoded audio signal, and noise reduction controls multiplex decoder for controlling noise attenuation associated with the decoded audio signal according to RSSI, the method comprising the steps: (a) performing phase error detection for detecting phase error of phase-locked loop (PLL) of pilot carrier sync detector; (b) determining whether noise exists by comparing the phase error with threshold value to determine whether noise exists in the phase error; and (c) performing noise reduction step by outputting noise reduction control signal to noise reduction based on determination in step (b) for reducing noise in the noise existence interval. | 02-09-2012 |
20120007754 | METHOD AND APPARATUS FOR DECODING TRANSMITTED/RECEIVED DATA - The present invention discloses a transmitted/received data decoding method and apparatus, which achieve effects of decoding performance improvement and synchronous detection. The decoding method includes setting a coded edge pattern, and filtering a received data by using the set coded edge pattern as a window; respectively computing absolute values of filtered values filtered by using the coded edge pattern windows; detecting a maximum absolute value from the computed absolute values; determining a sign (+/−) for the detected maximum absolute value; outputting an intermediate bit value of the corresponding original data as a resultant decoded value according to the determined sign and a window type (i.e. coded edge patter) with the selected maximum absolute value. | 01-12-2012 |
20110304367 | APPARATUS AND METHOD FOR FREQUENCY CALIBRATION IN FREQUENCY SYNTHESIZER - An apparatus and a method for frequency calibration in a frequency synthesizer are disclosed. The present invention includes an up/down processor. The up/down processor is utilized for outputting one of a GND voltage and a VDD voltage to a voltage-controlled oscillator via a loop filter in an open loop status, or outputting one of a step-up voltage and a step-down voltage in accordance with a phase difference to the voltage-controlled oscillator via the loop filter in a close loop status. When the up/down processor outputs one of the GND voltage and the VDD voltage in the open loop status, a memory bank selector compares frequencies for selecting a value of a memory bank and then adds an offset to the value of the memory bank so as to determine a final value of a VCO memory bank in the phase locked loop. | 12-15-2011 |
20110169591 | FILTER CUT-OFF FREQUENCY CORRECTION CIRCUIT - A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment. | 07-14-2011 |
20110103518 | DC OFFSET SUPPRESSION CIRCUIT FOR A COMPLEX FILTER - The present invention relates to a direct current (DC) offset suppression circuit to suppress DC offsets occurring when a communication circuit where a complex filter is adopted performs self-mixing. The DC offset is suppressed by a DC feedback circuit adopted by a filter which is substituted for a complex filter in the communication circuit. But, the DC offset cannot be suppressed when a complex filter is used in the communication circuit. It is because phase changes of the complex filter cause output signal fed back to the input of the complex filter to generate phase differences. The present invention includes a phase compensation unit and a DC feedback unit. The phase compensation unit compensates a change in frequency between input and output of the complex filter for phase compensation. The DC feedback unit inverses and feeds back the compensated phase to an input of the complex filter. | 05-05-2011 |
20110063013 | MIXER CIRCUIT - The present invention discloses a mixer circuit for mixing two input signals by source-coupled MOS transistors and outputting a mixed result. A duty cycle controlling MOS transistor is connected to a source of each source-coupled MOS transistor in series. A duty cycle controlling pulse is applied to a gate of the duty cycle controlling MOS transistor. The duty cycle controlling pulse has a phase shift of −90 degrees with respect to a controlling pulse applied to the gate of the source-coupled MOS transistor connected with the duty cycle controlling MOS transistor in series. An AND-combination of the duty cycles of the two controlling pulses applied to the gates of the two MOS transistors connected in series can be controlled at 25%. Comparing to the conventional mixer circuit having a switch control duty cycle of 50%, the present invention achieves the effects of increasing the gain and reducing the noise figure. | 03-17-2011 |
20100329400 | ESTIMATING METHOD FOR MAXIMUM CHANNEL DELAY AND CYCLIC PREFIX (CP) AVERAGING METHOD IN OFDM RECEIVER - An estimating method for maximum channel delay and cyclic prefix (CP) averaging method in orthogonal frequency division multiplexing (OFDM) receiver are described. Specifically, the estimating method performs the estimation of the maximum channel delay by adding the CP and the main OFDM signal for increasing the signal-to-noise ratio (SNR) and for reducing the inter-carrier interference (ICI). The CP averaging method is used to acquire a portion of the CP by using the maximum channel delay so as to increase the performance of the OFDM receiver. | 12-30-2010 |
20100134087 | LOW NOISE REFERENCE CIRCUIT OF IMPROVING FREQUENCY VARIATION OF RING OSCILLATOR - A low noise reference voltage circuit without using an amplifier inside is capable of transforming a current I | 06-03-2010 |
20100073033 | PEAK DETECTOR - A peak detector capable of rapidly detecting a peak value of a signal is provided. The peak detector includes first and second operational amplifiers and an auxiliary current source to detect two rail to rail signals. The first operational amplifier outputs a detection signal by buffering a first rail to rail input signal. The second operational amplifier outputs a control signal in response to a second rail to rail input signal and the detection signal. The auxiliary current source includes a terminal connected to an output terminal of the first operational amplifier and the other terminal connected to the first or second source voltage. The auxiliary current source operates in response to the control signal. The auxiliary current source supplies a current from the first source voltage to the output terminal in response to the control signal or supplies a path for discharging a current from the output terminal to the second source voltage. | 03-25-2010 |
20090302946 | VARIABLE GAIN AMPLIFIER HAVING LINEAR-IN-dB GAIN CHARACTERISTIC - A variable gain amplifier (VGA) with a linear-in-dB gain characteristic is provided. The VGA includes: a control signal converter which converts an input gain control signal V | 12-10-2009 |
20090051453 | VOLTAGE-CONTROLLED OSCILLATOR USING LC RESONATOR - Provided is a voltage-controlled oscillator (VCO) using an LC resonator circuit which includes a first resonance circuit in which two serially connected varactor diodes and an inductor are connected in parallel, a second resonance circuit in which one or more inductor L | 02-26-2009 |
20080315953 | Variable Gain Mixer - There is provided a variable gain mixer capable of controlling a gain at a low source voltage in a wide range without additional current consumption. | 12-25-2008 |
20080299902 | MULTI-CHANNEL RECEIVER AND METHOD OF REDUCING INTERFERENCE OF THE SAME - A multi-channel receiver capable of minimizing an interference effect occurring among mounted receivers and a method of reducing interference of the multi-channel receiver capable of minimizing the interference effect occurring among the mounted receivers are provided. The multi-channel receiver includes an antenna, a first receiver, and a second receiver. The antenna receives an RF signal in a predetermined frequency band. The first receiver down-converts the RF signal received through the antenna into a first IF signal. The second receiver down-converts the RF signal received through the antenna into a second IF signal. Here, the first and second receivers down-convert the RF signal by exclusively using a local oscillation frequency signal generated by using a low side LO injection method or a local oscillation frequency signal generated by using a high side LO injection method. | 12-04-2008 |
20080231369 | VARIABLE-GAIN LOW-NOISE AMPLIFIER - A variable-gain low-noise amplifier is provided. The variable-gain low-noise amplifier includes a first load, a second load, an input transistor, a pole/zero control circuit, and a gain control circuit. A first terminal of the first load is connected to a power-source voltage, and a second terminal thereof is connected to an output terminal. The second load is operated in response to a bias voltage, and a first terminal thereof is connected to the output terminal. A first terminal of the input transistor is connected to the second terminal of the second load, and a gate thereof is connected to an input terminal. The pole/zero control circuit adjusts frequency characteristics and a gain in response to at least one pole/zero control signal. A first terminal of the pole/zero control circuit is connected to the input terminal, and a second terminal thereof is connected to the output terminal. The gain control circuit adjusts the gain in response to at least one gain control signal. A first terminal of the gain control circuit is connected to a common terminal of the second load and the input transistor, and a second terminal thereof is connected to the input terminal, and a third terminal thereof of is connected to a ground voltage. | 09-25-2008 |