| Fairchild Semiconductor Corporation Patent applications |
| Patent application number | Title | Published |
|---|
| 20120100670 | WAFER LEVEL BUCK CONVERTER - A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die. | 04-26-2012 |
| 20120094458 | HYBRID-MODE LDMOS - An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode. | 04-19-2012 |
| 20120094436 | EMBEDDED DIE PACKAGE ON PACKAGE (POP) WITH PRE-MOLDED LEADFRAME - A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other. | 04-19-2012 |
| 20120086051 | SEMICONDUCTOR DEVICE WITH (110)-ORIENTED SILICON - A vertical semiconductor device includes a bottom metal layer and a first P-type semiconductor layer overlying the bottom metal layer. The first P-type semiconductor layer is characterized by a surface crystal orientation of (110) and a first conductivity. The first P-type semiconductor layer is heavily doped. The vertical semiconductor device also includes a second P-type semiconductor layer overlying the first P-type semiconductor layer. The second semiconductor layer has a surface crystal orientation of (110) and is characterized by a lower conductivity than the first conductivity. The vertical semiconductor device also has a top metal layer overlying the second P-type semiconductor layer. A current conduction from the top metal layer to the bottom metal layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane. | 04-12-2012 |
| 20120001610 | BUCK-BOOST REGULATOR WITH DEAD BAND - This document provides methods and apparatus configured to efficiently regulate an output voltage near a desired voltage level, for example, under varying input or load conditions. An example apparatus can include a regulator having a boost controller configured to provide voltage to an output of the regulator when at least one of the output voltage or the input voltage is below a first threshold voltage and a buck controller configured to provide voltage to the output of the regulator when at least one of the output voltage or the input voltage is above a second threshold voltage. Further, the regulator can be configured to provide the input voltage at the output of the regulator when at least one of the input voltage or the output voltage is between the first and second threshold voltages. In some examples, the first threshold is below the second threshold. | 01-05-2012 |
| 20120001313 | SEMICONDUCTOR PACKAGE WITH AN EMBEDDED PRINTED CIRCUIT BOARD AND STACKED DIE - A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module. | 01-05-2012 |
| 20110318920 | LOW TEMPERATURE, LONG TERM ANNEALING OF NICKEL CONTACTS TO LOWER INTERFACIAL RESISTANCE - A method of annealing semiconductor devices to form substantially ohmic contact regions between a layer of wide band-gap semiconductor material and contact areas disposed thereon includes exposing the semiconductor devices to an annealing temperature less than approximately 900 degrees Celsius for an annealing duration of greater than approximately two hours. | 12-29-2011 |
| 20110316078 | SHIELDED LEVEL SHIFT TRANSISTOR - A semiconductor device can include a transistor and an isolation region. The transistor is formed in a semiconductor substrate having a first conductivity type. The transistor includes a drift region extending from a drain region toward a source region and having a second conductivity type. The drift region includes a first resurf region near a working top surface and having the first conductivity type. The high voltage isolation island region includes a first well region laterally offset from the drift region. The first well region has the second conductivity type. An isolation region is located laterally between the drain region and the first well region. The isolation region comprises a portion of the semiconductor substrate extending to the top working surface. | 12-29-2011 |
| 20110293100 | AUDIO AMPLIFIER PERFORMANCE WHILE MAINTAINING USB COMPLIANCE AND POWER DOWN PROTECTION - An apparatus comprises a first audio amplifier circuit configured to provide an analog audio signal and an analog switch circuit including a first input configured to receive the analog audio signal, a second input configured to receive a first digital data signal, and a first output configured to provide one of the digital data signal or the analog audio signal. The apparatus also includes a first feedback circuit coupled to the first audio amplifier circuit and the analog switch circuit output, the feedback circuit configured to bias the first audio amplifier circuit. | 12-01-2011 |
| 20110284955 | FIELD EFFECT TRANSISTOR WITH TRENCH FILLED WITH INSULATING MATERIAL AND STRIPS OF SEMI-INSULATING MATERIAL ALONG TRENCH SIDEWALLS - In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material may be insulated from the first semiconductor region. | 11-24-2011 |
| 20110275208 | SHIELD CONTACTS IN A SHIELDED GATE MOSFET - A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region. | 11-10-2011 |
| 20110255203 | CHARGE PUMP SWITCH POWER DOWN PROTECTION - This application discusses, among other things, switch circuit apparatus having power down protection and not requiring power up sequencing. An apparatus embodiment can include a first supply node coupled to a first input of a level shifting circuit via a protection circuit, a second supply node coupled to a second input of the level shifting circuit via a single pull-up transistor, and a switch including a control input, a first node, and a second node controllably isolated from the first node, wherein the control input is coupled to the level shifting circuit. The first and second inputs of the level shifting circuit can be coupled via a rectifier, and the protection circuit can be configured to power the first and second supply nodes to controllably isolate the first and second nodes from each other when a voltage of one of the first or second nodes exceeds a threshold. | 10-20-2011 |
| 20110204960 | Fully Featured Control Pin Powered Analog Switch - An apparatus comprises at least one input connection, at least one output connection, at least one control connection, a voltage converter circuit having an input coupled to the control connection and an output, wherein the voltage converter circuit is configured to provide a voltage at its output that is greater than a voltage present at its input, and at least one switch circuit coupled to the input connection, the output connection, and the output of the voltage converter circuit. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by the voltage converter output. Power to the voltage converter circuit is provided via the control connection, and power to the switch circuit is provided via the output of the voltage converter circuit. | 08-25-2011 |
| 20110204955 | CONTROL PIN POWERED ANALOG SWITCH - An apparatus comprises at least one input connection, at least one output connection, and at least one control connection, and at least one switch circuit coupled to the input, the output, and the control connections. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by a control signal received at the control connection. Power to the switch circuit is provided via the control connection. | 08-25-2011 |
| 20110199123 | MULTIPLE DETECTION CIRCUIT FOR ACCESSORY JACKS - This document discusses, among other things, a multiple accessory detection apparatus and methods for identifying accessories coupled to a multi-pin connector of an electronic device. The apparatus can include a first reference generator, a second reference generator, a plurality of switches to couple an output of the second generator to an accessory device and a comparator. The comparator can generate identifying information about the accessory device using the reference information received from the first reference generator and test information received using the second reference generator. | 08-18-2011 |
| 20110163391 | WAFER LEVEL STACK DIE PACKAGE - This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components. | 07-07-2011 |
| 20110161532 | TRANSCEIVER FOR WIRED SERIAL COMMUNICATION - This document discusses, among other things, transceiver apparatus and methods for wired serial communication to a remote device. The transceiver can be configured to generate an output signal using received compensation information to maintain a specified signal quality at the remote device. The transceiver can include an input for receiving first information, a compensation input for receiving the compensation information and an output to transmit the output signal including the first information to a component coupled between the transceiver and the remote device. | 06-30-2011 |
| 20110148510 | REDUCED CURRENT CHARGE PUMP - This document discusses, among other things, a charge pump having a plurality of switching devices, coupled in parallel, and configured to selectively provide a variable available drive current for a capacitor using a comparison of an output voltage to at least one reference voltage. | 06-23-2011 |
| 20110148386 | FAST RECOVERY VOLTAGE REGULATOR - This document discusses, among other things, a voltage regulator having a plurality of switching devices, coupled in parallel, and configured to selectively provide a variable available drive current using a comparison of a regulated Dc output voltage to at least one reference voltage. | 06-23-2011 |
| 20110148385 | SELECTIVELY ACTIVATED THREE-STATE CHARGE PUMP - This document discusses, among other things, a device for providing a DC output voltage, including a first output voltage and a second output voltage, from an input voltage. The device can include a first voltage regulator configured to provide the first output voltage when the input voltage is below a threshold voltage, and a charge pump configured to provide the second output voltage from the first output voltage in a two-state mode when the input voltage is below the threshold voltage, and to provide the first output voltage and the second output voltage in a three-state mode when the input voltage is above the threshold voltage. | 06-23-2011 |
| 20110147917 | INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED COMPONENTS - This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second discrete components and the plurality of conductive regions. | 06-23-2011 |
| 20110133318 | SiP SUBSTRATE - Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace. | 06-09-2011 |
| 20110127607 | STEPPED-SOURCE LDMOS ARCHITECTURE - A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate. | 06-02-2011 |
| 20110124197 | METHOD TO IMPROVE THE RELIABILITY OF THE BREAKDOWN VOLTAGE IN HIGH VOLTAGE DEVICES - A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device. | 05-26-2011 |
| 20110124158 | THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE - A semiconductor package includes a semiconductor device | 05-26-2011 |
| 20110099300 | CAMERA SHUTTER CONTROL THROUGH A USB PORT OR AUDIO/VIDEO PORT - An apparatus comprises a digital image sensor, a communication port, a detection circuit and a processor. The detection circuit is configured to detect a change in electrical resistance at a connector of the communication port. The processor is configured to initiate an operation of the apparatus according to the detected change in resistance. | 04-28-2011 |
| 20110099298 | METHOD OF DETECTING ACCESSORIES ON AN AUDIO JACK - An apparatus comprises an audio or video jack connector configured to receive an audio or video jack plug of a separate device, a detection circuit in electrical communication with the connector, and a processor communicatively coupled to the detection circuit. The connector includes an electrical contact for connection to a conducting terminal of the plug. The detection circuit is configured to determine a resistance at the conducting terminal. The resistance is a resistive load of the separate device at the conducting terminal of the plug. The processor is configured to identify a function of the separate device according to the determined resistance, and configure an operation of the apparatus according to the determined function. | 04-28-2011 |
| 20110095417 | LEADLESS SEMICONDUCTOR DEVICE TERMINAL - This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area. | 04-28-2011 |
| 20110095410 | WAFER LEVEL SEMICONDUCTOR DEVICE CONNECTOR - This document discusses, among other things, a semiconductor connector including a conductive pad in a recessed pad area on a surface of a dielectric, the dielectric material configured to be activated to conductive plating deposition using laser ablation. | 04-28-2011 |
| 20110089432 | WIDE BANDGAP DEVICE IN PARALLEL WITH A DEVICE THAT HAS A LOWER AVALANCHE BREAKDOWN VOLTAGE AND A HIGHER FORWARD VOLTAGE DROP THAN THE WIDE BANDGAP DEVICE - An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer. | 04-21-2011 |
| 20110070699 | 3D SMART POWER MODULE - A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a direct bonded copper substrate which has a bottom surface exposed in the molded package. In one embodiment the module has 27 external connectors attached to one side of the PC board and arranged in the form of a ball grid array. | 03-24-2011 |
| 20110068461 | EMBEDDED DIE PACKAGE AND PROCESS FLOW USING A PRE-MOLDED CARRIER - An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings. | 03-24-2011 |
| 20110042717 | INTEGRATED LOW LEAKAGE DIODE - An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on. | 02-24-2011 |
| 20110042013 | METHOD AND APPARATUS FOR BONDED SUBSTRATES - An apparatus for bonding substrates includes a base member having a top surface and a recessed region which is configured for receiving at least a first substrate. The apparatus also has a plurality of support members disposed over the top surface for supporting a second substrate peripherally over the first substrate. Each support member is configured to vary a separation between the first substrate and the second substrate. Moreover, a pressure bar is configured to cause a center portion of the second substrate to contact the first substrate while the support members maintain peripheral separation between the first substrate and the second substrate. In operation, a bonded region between the first and the second substrates is expanded radially from the center portion when the support members are positioned to reduce the separation between the first and the second substrates. | 02-24-2011 |
| 20110031979 | IGNITION SYSTEM OPEN SECONDARY DETECTION - This document discusses, among other things, a system and method for detecting an open secondary condition in a secondary coil of an ignition coil using a control signal received from a control input of a switch configured to control the flow of current to a primary coil of the ignition coil. In an example, the flow of current in the primary coil of the ignition coil can be controlled using an insulated gate bipolar junction transistor (IGBT), and the open secondary condition in the secondary coil of the ignition coil can be detected using a received gate voltage of the IGBT. | 02-10-2011 |
| 20110010750 | NO POP SWITCH - A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold. | 01-13-2011 |
| 20110008935 | SEMICONDUCTOR DIE PACKAGE INCLUDING LEADFRAME WITH DIE ATTACH PAD WITH FOLDED EDGE - A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad. A semiconductor die comprising a first surface and a second surface is attached to the semiconductor die, and a molding material is around at least a portion of the leadframe structure and at least a portion of the semiconductor die. The opposite surface is exposed through the molding material and terminal ends of the leads do not extend past lateral edges of the molding material. | 01-13-2011 |
| 20110003432 | FLIP CHIP MLP WITH FOLDED HEAT SINK - A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar member in a direction towards the lower surface of the MLP. These heat sink leads may provide the emitter connection to a printed circuit (PC) board. | 01-06-2011 |
| 20100323485 | PN JUNCTION AND MOS CAPACITOR HYBRID RESURF TRANSISTOR - A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack. | 12-23-2010 |
| 20100318704 | UNIVERSAL SERIAL BUS (USB) TO DIGITAL VIDEO - This document discusses, among other things, a system and method for switching serialized video information (e.g., non-packet-based video information) and Universal Serial Bus (USB) information (e.g., packet-based information) to a common output (e.g., to a physical USB interface). | 12-16-2010 |
| 20100318697 | UNIVERSAL SERIAL BUS (USB) TO DIGITAL VIDEO - This document discusses, among other things, a system and method for deserializing non-packet-based video information received using a physical Universal Serial Bus (USB) interface and providing a high definition output signal to a video port (e.g., an HD video port, such as HDMI, DisplayPort, etc.) using the deserialized video information. | 12-16-2010 |
| 20100315155 | HIGH SPEED, LOW POWER CONSUMPTION, ISOLATED ANALOG CMOS UNIT - A semiconductor device including: a low threshold PMOS device formed over an N-type region, the source and drain of the low threshold PMOS formed in P-regions surrounded by N-regions; a low threshold NMOS device formed in a P-type region, the source and drain of the low threshold NMOS formed in N-regions surrounded by P-regions; first and second substrate bias generators, each connected to one of the low threshold devices for generating a substrate bias; a voltage source for generating substrate bias during a standby mode to reduce leakage current; wherein a low voltage threshold is established by the source and drain regions of the low threshold devices and their respective surrounding regions of opposite polarity. | 12-16-2010 |
| 20100267213 | SELF-ALIGNED COMPLEMENTARY LDMOS - The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage. | 10-21-2010 |
| 20100233862 | INTEGRATED LOW LEAKAGE SCHOTTKY DIODE - An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N− layer over a P− layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N− and P− layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P− layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P− layer through a P well. | 09-16-2010 |
| 20100219790 | PERIPHERAL DEVICE HOST CHARGING - This document discusses, among other things, a charging emulator configured to be coupled to an electrical interface, the charging emulator including a control circuit configured to receive information about a peripheral device coupled to the electrical interface and a charger circuit configured to provide power to the electrical interface using the received peripheral device information. In an example, the charging emulator can include a component of a host device including a low-power state, and the charger circuit can be configured to provide power to the electrical interface when the host device is in the low-power state. | 09-02-2010 |
| 20100219471 | QUASI-RESURF LDMOS - A semiconductor device can include a drift region, at least a portion of the drift region located laterally between a drain region and a source region. The drift region can include a first layer having a first doping concentration and a second layer having a second higher doping concentration than the first layer. The second layer of the drift region be configured to allow drift current between the source region and the drain region when a depletion region is formed in at least a portion of the first layer between the source region and the drain region. | 09-02-2010 |
| 20100194467 | Devices, Methods, and Systems With MOS-Gated Trench-to-Trench Lateral Current Flow - A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the device was fabricated on just the surface of the wafer. Masking is avoided while open trenches are present. A transistor with a very low on-resistance per unit area is obtained. | 08-05-2010 |
| 20100148328 | POWER QUAD FLAT NO-LEAD SEMICONDUCTOR DIE PACKAGES WITH ISOLATED HEAT SINK FOR HIGH-VOLTAGE, HIGH-POWER APPLICATIONS, SYSTEMS USING THE SAME, AND METHODS OF MAKING THE SAME - Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the molding material of the package. The heat sink member has an electrically insulating substrate with a high breakdown voltage, and one or more conductive layers disposed on a first surface of the substrate that electrically interconnect the semiconductor to one or more leads of the leadframe. | 06-17-2010 |
| 20100052046 | SEMICONDUCTOR STRUCTURES FORMED ON SUBSTRATES AND METHODS OF MANUFACTURING THE SAME - A semiconductor apparatus includes a metal substrate, a doped silicon layer on the metal substrate, a semiconductor layer overlying the doped silicon layer, and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. In an embodiment, the doped silicon layer comprises a heavily doped silicon layer. In another embodiment, the doped silicon region has a thickness that is less than a thickness of a cleavable region formed by ion implantation. In a specific embodiment, the thickness of the cleavable region is about 1-2 um. In another embodiment, the semiconductor layer has a thickness of approximately 10 um. In another embodiment, the semiconductor structures includes a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region. | 03-04-2010 |
| 20100001799 | AMPLIFIER CURRENT DRIVE REVERSAL - A drive current direction between first and second amplifiers can be selected using a received indication of an output current in an at least partially reactive load, and an amplified output signal can be produced using the selected drive current direction and the first and second amplifiers. Further, the first and second amplifiers can be configured to alternate between a pull-up mode and a pull-down mode, each amplifying half of a full wave output signal. | 01-07-2010 |
| 20090072362 | THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE - A semiconductor package includes a semiconductor device | 03-19-2009 |
| 20080227275 | METHOD AND DEVICE WITH DURABLE CONTACT ON SILICON CARBIDE - A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact | 09-18-2008 |
| 20080211014 | ULTRA DENSE TRENCH-GATED POWER DEVICE WITH THE REDUCED DRAIN-SOURCE FEEDBACK CAPACITANCE AND MILLER CHARGE - The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate. | 09-04-2008 |
| 20080210974 | High voltage LDMOS - A power semiconductor device having high avalanche capability comprises an N | 09-04-2008 |
