| Fairchild Korea Semiconductor Ltd. Patent applications |
| Patent application number | Title | Published |
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| 20110073984 | SEMICONDUCTOR POWER MODULE PACKAGE WITH TEMPERATURE SENSOR MOUNTED THEREON AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal. | 03-31-2011 |
| 20100320537 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode. | 12-23-2010 |
| 20100289137 | HEAT SINK PACKAGE - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 11-18-2010 |
| 20100271079 | POWER SEMICONDUCTOR DEVICE - Disclosed is a power semiconductor device including a bootstrap circuit. The power semiconductor device includes a high voltage unit that provides a high voltage control signal so that a high voltage is output; a low voltage unit that provides a low voltage control signal so that a ground voltage is output, and is spaced apart from the high voltage unit; a charge enable unit that is electrically connected to the low voltage unit and charges a bootstrap capacitor for supplying power to the high voltage unit when the high voltage is output, when the ground voltage is output; and a high voltage cut-off unit that cuts off the high voltage when the high voltage is output so that the high voltage is not applied to the charge enable unit, and includes a first terminal electrically connected to the charge enable unit and a second terminal electrically connected to the high voltage unit. | 10-28-2010 |
| 20100203684 | SEMICONDUCTOR PACKAGE FORMED WITHIN AN ENCAPSULATION - Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns. | 08-12-2010 |
| 20100176498 | POWER MODULE PACKAGE HAVING EXCELLENT HEAT SINK EMISSION CAPABILITY AND METHOD FOR MANUFACTURING THE SAME - A power module package includes a power circuit element, a control circuit element, a lead frame, an aluminum oxide substrate having a heat sink and an insulation layer, and a sealing resin. The control circuit element is electrically connected with the power circuit element to control chips within the power circuit element. The lead frame has external connection terminal leads in its edge and has a first surface to which the power circuit element and the control circuit element are attached and a second surface which is used as a heat transmission path. The heat sink is a plate made of metal such as aluminum and the electrical insulation layer is formed at least on an upper surface of the heat sink and made of aluminum oxide. The electrical insulation layer may be formed over an entire surface of the heat sink. Here, the insulation layer is attached to the second surface by an adhesive, on a region below where the power circuit element is attached, to the first surface of the lead frame. In addition, the sealing resin encloses the power circuit element and the control circuit element, the lead frame, and the metal oxide substrate and exposes the external connection terminals of the lead frame. | 07-15-2010 |
| 20100167470 | POWER MODULE FOR LOW THERMAL RESISTANCE AND METHOD OF FABRICATING THE SAME - A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented. | 07-01-2010 |
| 20100165576 | POWER SYSTEM MODULE AND METHOD OF FABRICATING THE SAME - Provided are a power system module allowing a user's requirements to be easily met, and having economic practicality and high integration, and a manufacturing method thereof. The power system module includes a plastic case, a molding type power module package, a control circuit board, and at least one external terminal. The plastic case defines a bottom and a side wall. The molding type power module package is fixed to the bottom of the plastic case and includes at least a power device therein. The control circuit board is fixed to the side wall of the plastic case, includes at least a control device mounted thereon which is electrically connected to the power module package. The external terminal protrudes to outside the plastic case and is electrically connected to the control circuit board. | 07-01-2010 |
| 20100140786 | SEMICONDUCTOR POWER MODULE PACKAGE HAVING EXTERNAL BONDING AREA - Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more semiconductor chips and exposed from the sealing member; and an external bonding member electrically connected to the one or more semiconductor chips and electrically connecting an external circuit board exposed from the sealing member. | 06-10-2010 |
| 20100093134 | SEMICONDUCTOR PACKAGE HAVING INSULATED METAL SUBSTRATE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns. | 04-15-2010 |
| 20100019809 | Switch Controller, Switch Control Method, And Converter Using The Same - Disclosed are a switch controller, a switch control method, and a converter based thereon. The switch controller generates an input sensing voltage corresponding to the input voltage of the converter, and compares the input sensing voltage with a predetermined first reference value. The switch controller generates a zero cross detection signal with a first level or a second level depending upon the comparison result, and generates a reference clock signal varying in frequency in accordance with one cycle of the zero cross detection signal. The switch controller generates digital signals by using the reference clock signal and the zero cross detection signal. The digital signals synchronize with the zero cross detection signal, and increase in accordance with the reference clock signal during a half of one cycle of the zero cross detection signal, while decreasing in accordance with the reference clock signal during the other half cycle of the zero cross detection signal. The switch controller generates a reference signal with a voltage level corresponding to the digital signal. | 01-28-2010 |
| 20100019688 | Inverter And Lamp Driver Including The Same - The present invention relates to an inverter and a lamp driver having the same. The inverter includes a first switch having a first body diode, a second switch having a second body diode, a transformer including a first side coil in which a first current and a first voltage are generated according to switching operations of the first switch and the second switch and a second side coil having a predetermined winding ratio with respect to the first side coil, and a controller for controlling each switching operation of the first switch and the second switch. The controller turns on one of the first switch and the second switch corresponding to one of the first body diode and the second body diode, and a current flows through the first switch and the second switch during a dead time. | 01-28-2010 |
| 20100001343 | HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING FIELD SHAPING LAYER AND METHOD OF FABRICATING THE SAME - Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer. | 01-07-2010 |
| 20090323374 | Switch Control Device And Converter Including The Same - The present invention relates to a switch control device and a converter including the same. According to an exemplary embodiment of the present invention, the switch control device includes a PWM controller for forcing a power switch to turn on when the power switch is turned off during a predetermined period, a current sensor for determining whether a current flows through the power switch, and a conditional counter for determining that an input voltage is input to a power transmission element by using a sense result of the current sensor and a number of times that the PWM controller turns on the power switch by force. | 12-31-2009 |
| 20090296437 | Converter - A converter is provided including: a first switch; an energy transmitting element for converting input energy into output energy according to the switching of the first switch; and a switching controller for detecting a time when a voltage between a first terminal and a second terminal of the first switch reaches a valley of a resonance waveform, and actuating the first switch corresponding to one of the detected valleys of the resonance waveform. The switching controller includes: a valley detector for changing the state of the output signal whenever a voltage between a first terminal and a second terminal of the first switch reaches a valley of the resonance waveform; and a PWM controller for actuating the first switch corresponding to an output signal of the valley detector. | 12-03-2009 |
| 20090295358 | Driving Device - The present invention relates to a driving device. The driving device according to the present invention includes a main transistor that supplies a current to a load by using a power supply, an auxiliary transistor that drops a predetermined voltage of the voltage of the power supply and transmits the dropped voltage to the main transistor in a turn-on state, and a bypass switch that transmits the voltage of the power supply to the main transistor when the auxiliary transistor is turned off. | 12-03-2009 |
| 20090251929 | Convertor and Driving Method Thereof - A converter and a driving method thereof are provided. The converter includes first and second switches, and generates a square wave signal according to operations of the first and second switches. The converter includes a first capacitor and a primary coil, and resonates a driving voltage by using a driving voltage with the first capacitor and the primary coil so as to generate a driving current. The converter includes a secondary coil that forms the primary coil and the transformer, and generates output power by rectifying a current and a voltage generated in the secondary coil. In addition, the converter detects the phase of the driving current, and increases switching frequencies of the first and second switches if a phase difference of the phase of the driving current and that of the driving voltage is smaller than a predetermined value. | 10-08-2009 |
| 20090250753 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode. | 10-08-2009 |
| 20090243696 | HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING SHIFTERS AND METHOD OF FABRICATING THE SAME - Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters. | 10-01-2009 |
| 20090230481 | SEMICONDUCTOR DEVICE FORMED USING SINGLE POLYSILICON PROCESS AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions. | 09-17-2009 |
| 20090194869 | HEAT SINK PACKAGE - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 08-06-2009 |
| 20090194859 | SEMICONDUCTOR PACKAGE AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor package having a power device and methods of fabricating the same. The semiconductor package includes a lead frame, a polymer layer component on the lead frame, a metal layer component on the polymer layer component, and a semiconductor chip on the metal layer component. The polymer layer component may include a material formed by adding alumina Al | 08-06-2009 |
| 20090184406 | SEMICONDUCTOR PACKAGE HAVING INSULATED METAL SUBSTRATE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns. | 07-23-2009 |
| 20090127681 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first die-pad on which a semiconductor chip is mounted on a bottom surface of the first die-pad, a support plate disposed adjacent to a lateral surface of the first die-pad, a support prop protruding from the support plate, and supporting the first die-pad, and a package body that encapsulates the first die-pad, the semiconductor chip, and the support plate. | 05-21-2009 |
| 20080211053 | Superjunction Semiconductor Device - In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the boundary between the active region and the termination region. The active and termination regions include columns of first and second conductivity type material alternately arranged along a horizontal direction in a semiconductor region having top and bottom surfaces. At least one of the columns of the first conductivity type material in the termination region has a different width than a width of the columns of the first conductivity type material in the active region. | 09-04-2008 |
