| EXEGY INCORPORATED Patent applications |
| Patent application number | Title | Published |
|---|
| 20120095893 | METHOD AND APPARATUS FOR HIGH-SPEED PROCESSING OF FINANCIAL MARKET DEPTH DATA - A variety of embodiments for hardware-accelerating the processing of financial market depth data are disclosed. A coprocessor, which may be resident in a ticker plant, can be configured to update order books based on financial market depth data at extremely low latency. Such a coprocessor can also be configured to enrich a stream of limit order events pertaining to financial instruments with data from a plurality of updated order books. | 04-19-2012 |
| 20120089497 | Method and Apparatus for High-Speed Processing of Financial Market Depth Data - A variety of embodiments for hardware-accelerating the processing of financial market depth data are disclosed. A coprocessor, which may be resident in a ticker plant, can be configured to update order books based on financial market depth data at extremely low latency. Such a coprocessor can also be configured to generate a quote event in response to a limit order event being determined to modify the top of an order book. | 04-12-2012 |
| 20120089496 | Method and Apparatus for High-Speed Processing of Financial Market Depth Data - A variety of embodiments for hardware-accelerating the processing of financial market depth data are disclosed. A coprocessor, which may be resident in a ticker plant, can be configured to update order books based on financial market depth data at extremely low latency. Such a coprocessor can also be configured to enrich a stream of limit order events pertaining to financial instruments with data from a plurality of updated order books. | 04-12-2012 |
| 20110184844 | High Speed Processing of Financial Information Using FPGA Devices - A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a record memory is employed to store a plurality of records for a plurality of financial instruments, and a reconfigurable logic device is employed to (1) receive financial market data messages, (2) retrieve from the record memory the records for the messages' associated financial instruments, (3) process each received financial market data message to update the record for the financial instrument associated with that message, and wherein each record comprises an interest list that identifies whether any of a plurality of entities have expressed an interest in being notified of data relating to the updated record. | 07-28-2011 |
| 20110179050 | High Speed Processing of Financial Information Using FPGA Devices - A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to (1) receive the financial market data messages, and (2) parse each received financial market data message into its constituent data fields. | 07-21-2011 |
| 20110178957 | High Speed Processing of Financial Information Using FPGA Devices - Methods and systems for processing financial market data using a reconfigurable logic device are disclosed. Various operations such as basket calculation and volume weighted average price (VWAP) operations can be performed on the financial market data using firmware logic deployed on the reconfigurable logic device to accelerate the speed of processing. | 07-21-2011 |
| 20110178919 | High Speed Processing of Financial Information Using FPGA Devices - A high speed apparatus and method for processing financial instrument order books are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to (1) process streaming financial market data, the streaming financial market data comprising a plurality of messages representative of a plurality of offers to buy and sell a plurality of financial instruments, and (2) maintain in real-time a plurality of financial instrument order books based on the messages | 07-21-2011 |
| 20110178918 | High Speed Processing of Financial Information Using FPGA Devices - A high speed system and method for processing financial instrument order data are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to monitor a financial instrument order based on a risk profile to determine whether the order is appropriate. If determined appropriate, a financial instrument order can be routed to a trading venue. With respect to another exemplary embodiment, a reconfigurable logic device is employed to maintain a financial instrument order book. | 07-21-2011 |
| 20110178917 | High Speed Processing of Financial Information Using FPGA Devices - A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to map the symbols present in the financial market data messages to another symbology. | 07-21-2011 |
| 20110178912 | High Speed Processing of Financial Information Using FPGA Devices - A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to (1) receive the financial market data messages, and (2) process each received financial market data message to update a stored record for the financial instrument associated with that message. | 07-21-2011 |
| 20110178911 | High Speed Processing of Financial Information Using FPGA Devices - Methods and systems for processing financial market data using reconfigurable logic are disclosed. Various functional operations to be performed on the financial market data can be implemented in firmware pipelines to accelerate the speed of processing. Also, a combination of software logic and firmware logic can be used to efficiently control and manage the high speed flow of financial market data to and from the reconfigurable logic. | 07-21-2011 |
| 20110040701 | Method and System for High Speed Options Pricing - A high speed technique for options pricing in the financial industry is disclosed that can provide both high throughput and low latency. Parallel/pipelined architectures are disclosed for computing an option's theoretical fair price. Preferably these parallel/pipelined architectures are deployed in hardware, and more preferably reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) to accelerate the options pricing operations relative to conventional software-based options pricing operations. | 02-17-2011 |
| 20100198850 | Method and Device for High Performance Regular Expression Pattern Matching - Disclosed herein is an improved architecture for regular expression pattern matching. Improvements to pattern matching deterministic finite automatons (DFAs) that are described by the inventors include a pipelining strategy that pushes state-dependent feedback to a final pipeline stage to thereby enhance parallelism and throughput, augmented state transitions that track whether a transition is indicative of a pattern match occurring thereby reducing the number of necessary states for the DFA, augmented state transition that track whether a transition is indicative of a restart to the matching process, compression of the DFA's transition table, alphabet encoding for input symbols to equivalence class identifiers, the use of an indirection table to allow for optimized transition table memory, and enhanced scalability to facilitate the ability of the improved DFA to process multiple input symbols per cycle. | 08-05-2010 |
| 20100094858 | Method and System for High Performance Integration, Processing and Searching of Structured and Unstructured Data Using Coprocessors - Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. Queries can be directed toward both an enterprise's structured and unstructured data using standardized database query formats such as SQL commands. A coprocessor can be used to hardware-accelerate data processing tasks (such as full-text searching) on unstructured data as necessary to handle a query. Furthermore, traditional relational database techniques can be used to access structured data stored by a relational database to determine which portions of the enterprise's unstructured data should be delivered to the coprocessor for hardware-accelerated data processing. | 04-15-2010 |
| 20090287628 | Method and System for Accelerated Stream Processing - Disclosed herein is a method and system for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams. | 11-19-2009 |
| 20090182683 | Method and System for Low Latency Basket Calculation - A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA). | 07-16-2009 |
| 20090060197 | Method and Apparatus for Hardware-Accelerated Encryption/Decryption - An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. A preferred embodiment of the integrated circuit includes a symmetric block cipher that may be scaled to strike a favorable balance among processing throughput and power consumption. The modular architecture also supports multiple encryption modes and key management functions such as one-way cryptographic hash and random number generator functions that leverage the scalable symmetric block cipher. The integrated circuit may also include a key management processor that can be programmed to support a wide variety of asymmetric key cryptography functions for secure key exchange with remote key storage devices and enterprise key management servers. Internal data and key buffers enable the device to re-key encrypted data without exposing data. The key management functions allow the device to function as a cryptographic domain bridge in a federated security architecture. | 03-05-2009 |
| 20080243675 | High Speed Processing of Financial Information Using FPGA Devices - Methods and systems for processing financial market data using reconfigurable logic are disclosed. Various functional operations to be performed on the financial market data can be implemented in firmware pipelines to accelerate the speed of processing. Also, a combination of software logic and firmware logic can be used to efficiently control and manage the high speed flow of financial market data to and from the reconfigurable logic. | 10-02-2008 |
