| Exar Corporation Patent applications |
| Patent application number | Title | Published |
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| 20120081094 | REFERENCE VOLTAGE BASED EQUIVALENT SERIES RESISTANCE (ESR) EMULATION FOR CONSTANT ON-TIME (COT) CONTROL OF BUCK REGULATORS - The present invention uses a reference voltage that varies within a Pulse Width Modulation (PWM) cycle to generate the PWM signal. This allows for stability in the feedback of Constant On-Time (COT) control for buck controllers when low Equivalent Series Resistance (ESR) capacitors are used as the output capacitor. The reference voltage is adjusted using features of a PWM cycle in a voltage mode without using external inductor current information. | 04-05-2012 |
| 20110276543 | VIRTUAL BLOCK DEVICE - A virtual block device is an interface with applications that appears to the applications as a memory device, such as a standard block device. The virtual block device interacts with additional elements to do data deduplication to files at the block level such that one or more files accessed using the virtual block device have at least one block which is shared by the one or more files. | 11-10-2011 |
| 20110204988 | GLUE-LOGIC BASED METHOD AND SYSTEM FOR MINIMIZING LOSSES IN OVERSAMPLED DIGITALLY CONTROLLED DC-DC CONVERTERS - A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor. | 08-25-2011 |
| 20110204862 | DIGITAL CONTROL METHOD FOR IMPROVING HEAVY-TO-LIGHT (STEP DOWN) LOAD TRANSIENT RESPONSE OF SWITCH MODE POWER SUPPLIES - A method for improving heavy-to-light load transient response in low-power switch-mode power supplies is described. It uses a negative voltage input power rail and a digital controller with an extended duty ratio control value to provide faster discharging current slew rate in the switched mode power supplies (SMPS) inductor. | 08-25-2011 |
| 20110199164 | EXTENDABLE N-CHANNEL DIGITAL PULSE-WIDTH/PULSE-FREQUENCY MODULATOR - A multichannel digital pulse width modulator/digital pulse frequency modulator uses a single ring oscillator that is shared by multiple channels. The ring oscillator has taps that can be used for least significant bit (LSB) precision of the generated PWM signal. The ring oscillator also produces a ring clock that is used to synchronize logic in the channels. Since the logic in the channels are synchronized by the ring clock, the channels can each independently produce different frequency PWM (or PFM) signals and still share the same ring oscillator. | 08-18-2011 |
| 20110185337 | METHODOLOGY FOR STORING AND UPDATING ON-CHIP REVISION LEVEL - Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa. | 07-28-2011 |
| 20100156482 | MEANS TO DETECT A MISSING PULSE AND REDUCE THE ASSOCIATED PLL PHASE BUMP - A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop. | 06-24-2010 |
| 20100141349 | UNIVERSAL AND FAULT-TOLERANT MULTIPHASE DIGITAL PWM CONTROLLER FOR HIGH-FREQUENCY DC-DC CONVERTERS - A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line. | 06-10-2010 |
| 20100141230 | SELF-TUNING SENSORLESS DIGITAL CURRENT-MODE CONTROLLER WITH ACCURATE CURRENT SHARING FOR MULTIPHASE DC-DC CONVERTERS - Embodiments of the present invention concern a multiphase switch-mode power supply. The multiple phase switch-mode power supply can have at least one switch and a digital controller to control the switching of the at least one switch. During a calibration period, the digital controller can freeze the current of all of the multiple phases except for a phase being calibrated. This can be done by fixing the current reference of the phases except for the phase being calibrated. | 06-10-2010 |
| 20100127762 | OPEN-DRAIN OUTPUT BUFFER FOR SINGLE-VOLTAGE-SUPPLY CMOS - An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages. By electrical coupling across maximal voltages, the voltage dividers generate reference voltages that induce proper selection of well-bias voltages to the floating wells. | 05-27-2010 |
| 20100117752 | MULTI-CHANNEL DIGITAL PULSE WIDTH MODULATOR (DPWM) - A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers. | 05-13-2010 |
| 20100117615 | ESR ZERO ESTIMATION AND AUTO-COMPENSATION IN DIGITALLY CONTROLLED BUCK CONVERTERS - One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the estimate. | 05-13-2010 |
| 20100066579 | GRAY CODE CURRENT MODE ANALOG-TO-DIGITAL CONVERTER - One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital converter can have a 65 ns conversion time and consume only 10 mW of power with a single +5.0V supply. | 03-18-2010 |
| 20090278522 | LOW POWER METHOD OF RESPONSIVELY INITIATING FAST RESPONSE TO A DETECTED CHANGE OF CONDITION - A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state without boost. | 11-12-2009 |
| 20090273498 | INTERRUPT BASED MULTIPLEXED CURRENT LIMIT CIRCUIT - A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value. | 11-05-2009 |
| 20090267582 | SELF-TUNING DIGITAL CURRENT ESTIMATOR FOR LOW-POWER SWITCHING CONVERTERS - A switched mode power can use a digital controller to control the switching of the at least one switch of the switched mode power supply. The current through the power inductor can be estimated using a self-tuning digital current estimator. | 10-29-2009 |
| 20090262474 | LOW-VOLTAGE CMOS SPACE-EFFICIENT 15 KV ESD PROTECTION FOR COMMON-MODE HIGH-VOLTAGE RECEIVERS - An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each of the p-type contact dopant regions is configured to form back-to-back diodes connected in series with cathodes in common. In protecting common mode receivers, current from an ESD event is channeled to ground rather than to the complementary receiver node. The diode stacks are capable of withstanding a 15 kV incident and save up to 25% in area compared to a fully parallel configuration for differential signal pairs. | 10-22-2009 |
| 20090231029 | COMBINATION OFFSET VOLTAGE AND BIAS CURRENT AUTO-ZERO CIRCUIT - A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier. | 09-17-2009 |
| 20090180227 | AUTO-DETECTING CMOS INPUT CIRCUIT FOR SINGLE-VOLTAGE-SUPPLY CMOS - An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input biasing transistors to ensure that no gate oxide exposed to external voltages sustains a voltage greater than a predefined value. Bias selectors select an available highest voltage to reverse bias corresponding floating wells and ensure transistors are not electrically overstressed. As input-related terminals experience switching related voltages, the bias selectors select alternate terminals to continue selection of the highest voltage available and provide correct reverse biasing conditions. A resistor and clamp generate translated output voltage levels limited to the native supply voltage range. A latch is triggered by a first input signal excursion above the native supply voltage. The latch output enables pull-down transistors to provide a correct low-level output signal. | 07-16-2009 |
| 20080297381 | METHODS OF USING PREDICTIVE ANALOG TO DIGITAL CONVERTERS - Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal and to thereby provide fairly good guesses. | 12-04-2008 |
| 20080273648 | Means To Reduce The PLL Phase Bump Caused By A Missing Clock Pulse - A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods. | 11-06-2008 |
| 20080272808 | Means To Detect A Missing Pulse And Reduce The Associated PLL Phase Bump - A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop. | 11-06-2008 |
| 20080225938 | DIGITAL PULSE FREQUENCY/PULSE AMPLITUDE (DPFM/DPAM) CONTROLLER FOR LOW-POWER SWITCHING-POWER SUPPLIES - A digital controller for dc-dc switching converters can operate under light load conditions. The controller can be suitable for the use in switch-mode power supplies providing regulated output voltage for handheld devices and other low-power electronics. To create long time intervals, compared to the propagation time of digital logic a DPFM/DPAM can use a ring oscillator with two sets of delay cells and two signals racing around the ring. | 09-18-2008 |
| 20080224756 | DIGITAL PULSE-WIDTH MODULATOR BASED ON NON-SYMMETRIC SELF-OSCILLATING CIRCUIT - A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures. | 09-18-2008 |
| 20080218278 | MEANS TO CONTROL PLL PHASE SLEW RATE - A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin. | 09-11-2008 |
| 20080218276 | MEANS TO CONTROL PLL PHASE SLEW RATE - A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin. | 09-11-2008 |
| 20080204296 | Wide-input windowed nonlinear analog-to-digital converter for high-frequency digitally controlled SMPS - In embodiments, a new analog-to-digital converter (ADC) architecture can be used with switch-mode power supplies (SMPS) operating at switching frequencies higher than 10 MHz. Analog-to-digital converter embodiments can achieve very low power consumption, fast conversion time, and can be implemented with a simple hardware. Another noteworthy benefit is that certain ADC embodiments feature a non-linear gain characteristic that provides improved load transient response for digital controllers. | 08-28-2008 |
