| Etron Technology Inc. Patent applications |
| Patent application number | Title | Published |
|---|
| 20130091315 | HIGH SPEED MEMORY CHIP MODULE AND ELECTRONICS SYSTEM DEVICE WITH A HIGH SPEED MEMORY CHIP MODULE - A high speed memory chip module includes a type of memory cell array group and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs), and each of the memory cell array ICs has a data bus and at least one memory cell array, and corresponds to first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length corresponding to a first MOSFET process. The logic unit accesses the type of memory cell array group through a first transmission bus, where bus width of the first transmission bus is wider than bus width of the data bus of each of the memory cell array ICs. Corresponding to a second MOSFET process, the logic unit has a second MOSFET gate length which is shorter than the first MOSFET gate length. | 04-11-2013 |
| 20130091312 | RECONFIGURABLE HIGH SPEED MEMORY CHIP MODULE AND ELECTRONICS SYSTEM DEVICE - A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus. | 04-11-2013 |
| 20130088907 | TRANSISTOR CIRCUIT LAYOUT STRUCTURE - A transistor circuit layout structure includes a transistor disposed on a substrate and including a source terminal, a drain terminal and a split gate including an independent first block and an independent second block, a bit line disposed on the source terminal and on the drain terminal or embedded in the substrate, a word line disposed on the first block, and a back line disposed on the second block. The horizontal level of the back line is different from that of the bit line and the word line. | 04-11-2013 |
| 20130087839 | DYNAMIC MEMORY STRUCTURE - A DRAM memory structure at least includes a strip semiconductive material disposed on a substrate and extending along a first direction, a split gate disposed on the substrate and extending along a second direction, a dielectric layer at least sandwiched between the split gate and the substrate, a gate dielectric layer at least sandwiched between the split gate and the strip semiconductive material, and a capacitor unit. The split gate independently includes a first block and a second block to divide the strip semiconductive material into a source terminal, a drain terminal and a channel. The capacitor unit is electrically connected to the source terminal. | 04-11-2013 |
| 20100327921 | CIRCUIT ARCHITECTURE FOR EFFECTIVE COMPENSATING THE TIME SKEW OF CIRCUIT - A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuits are the duplicates of the required compensation circuit. A differential of logic 0 and logic 1 signals are simultaneously inputted into two duplicated circuits to output a first detection signal and a second detection signal, then the time skew detection and compensation circuit detects the time skew between a first detection signal and a second detection signal so as to generate a compensation signal to the required compensation circuit. Accordingly, the time skew existed in the required compensation circuit can be reduced or eliminated. | 12-30-2010 |
