| ET INTERNATIONAL, INC. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110289507 | RUNSPACE METHOD, SYSTEM AND APPARATUS - The present invention, known as runspace, relates to the field of computing system management, data processing and data communications, and specifically to synergistic methods and systems which provide resource-efficient computation, especially for decomposable many-component tasks executable on multiple processing elements, by using a metric space representation of code and data locality to direct allocation and migration of code and data, by performing analysis to mark code areas that provide opportunities for runtime improvement, and by providing a low-power, local, secure memory management system suitable for distributed invocation of compact sections of code accessing local memory. Runspace provides mechanisms supporting hierarchical allocation, optimization, monitoring and control, and supporting resilient, energy efficient large-scale computing. | 11-24-2011 |
| 20110246823 | TASK-ORIENTED NODE-CENTRIC CHECKPOINTING (TONCC) - Node-centric checkpointing may be used in a multi-node computing system to provide fault-tolerance. Such checkpointing may involve storage of input and/or output data prior to and/or after execution of a task on a node. | 10-06-2011 |
| 20100286976 | Systems and Methods for Logic Verification - Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT. | 11-11-2010 |
| 20090222252 | DATA DRIVEN LOGIC SIMULATION CHIP AND TOOLCHAIN - An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip. | 09-03-2009 |
| 20080294411 | Systems and Methods for Logic Verification - Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT. | 11-27-2008 |
