# ESS Technology, Inc.

ESS Technology, Inc. Patent applications | ||

Patent application number | Title | Published |
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20140105269 | FIR Filter Using Unclocked Delay Elements - A system and method for filtering an analog signal with a finite impulse response (FIR) filter that does not require analog delay elements are disclosed. An analog signal is pulse-width encoded, and the pulse-width encoded signal passed to a delay line comprising unclocked delay elements, such as logic gates, rather than clocked delay elements such as are used in conventional FIR filters. The propagation of the input signal is thus due only to the delay inherent in each gate, and occurs based upon when a signal reaches the gate rather than being caused by a clock signal. As with a conventional FIR filter, weighting elements having impedance are used to weigh the output of each delay element, and the resulting outputs summed to obtain a filtered output signal. For certain signals, such a circuit and method provides a simpler way of filtering than conventional filters. | 04-17-2014 |

20140103977 | Use of Frequency Addition in a PLL Control Loop - A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added, to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal. | 04-17-2014 |

20140073279 | Minimizing Bandwidth in Down-Conversion of Multiple RF Channels - A method and system is disclosed for simultaneously down-converting multiple selected signals, such as RF signals, into adjacent ranges in an intermediate frequency band so that the total resulting bandwidth, and thus the sampling rate required to digitize the signal, is minimized. A first signal is down-converted into a range starting at a lowest selected frequency in the IF band. The next signal is down-converted, into a range higher than, but near or adjacent to, the down-converted range of the first signal, and so on. A guard band may be left between the signals if desired. In this way, the selected signals occupy the minimum bandwidth required. When the selection of signals to be down-converted is changed, the frequency ranges are dynamically adjusted so that the signals being down-converted always occupy the lowest ranges of the IF band. | 03-13-2014 |

20130254253 | Buffer-less Rotating Coefficient Filter - A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements, devices providing for adjustable impedances, or buffers is described. An input signal is sampled in a round robin fashion by a plurality of switches and capacitors. The capacitors are connected directly to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter, adjusted to compensate for the decay of samples in the capacitors between samples. The impedance devices in each set are connected to the capacitors in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the capacitor contains a new sample of the input signal. Switches connect the sets of impedance devices to an output and a virtual ground, only one switch being connected to the output at a time to provide the output signal. | 09-26-2013 |

20130241647 | Distortion Correction in Class-D Amplifiers - The present application describes an apparatus and method for reducing distortion in a class-D amplifier. The power output section of the amplifier is driven by an adjusted PWM signal, rather than by a PWM signal created directly from the input analog signal. A reference output, designed to closely track the input analog signal, is compared to the amplifier output. The resulting difference is an error signal which is inverted and summed with a second analog signal corresponding to the directly created PWM signal and changes the timing of the voltage transitions of the second analog signal. The changed voltage transitions are used to create the adjusted PWM signal. The inversion of the error signal causes negative feedback which results in the adjustment of the PWM signal being in a direction which reduces the error signal and thus the distortion of the amplifier. | 09-19-2013 |

20130115906 | Down-Conversion of Multiple RF Channels - A method and system is disclosed for designing a radio for down-converting RF signals to IF signals by sampling the signals in a round-robin sampling circuit and multiplying the samples by coefficients that are changed at a fixed rate equal to the rate of operation of each of the sampling circuits. The circuit is able to down-convert multiple channels simultaneously to adjacent positions in the IF band, while rejecting unwanted image signals. The method and system avoids the difficulty and cost of directly digitizing the RF signal, allowing each component to operate at a greatly reduced speed. The coefficients are selected to provide the desired transfer function while keeping the output signal centered at a desired frequency. | 05-09-2013 |

20130106486 | Feedback in Noise Shaping Control Loop | 05-02-2013 |

20130015995 | IMPEDANCE NETWORK FOR PRODUCING A WEIGHTED SUM OF INPUTSAANM Mallinson; MartinAACI KelownaAACO CAAAGP Mallinson; Martin Kelowna CA - A dynamically selectable resistor network is provided in a star configuration for producing a weighted sum of input values, without attenuation from near zero contributions. Each branch of the star connected network comprises sets of impedance components, preferably resistors, that are actively selectable to produce permutated combinations of effective weighting values. The resistors code digital control bits and the outputs of sets of resistors in respective branches that correspond to the least significant control bits provide their outputs to the summing output node independently of the sets of resistors corresponding to control bits of other significance. | 01-17-2013 |

20120300888 | VIRTUAL WEAVER ARCHITECTURE FILTER - A virtual Weaver architecture filter is implemented using a sampling mixer that successively processes samples of the input signal in round-robin fashion and provides a sum of the samples as multiplied by coefficients emulating quadrature sinusoidal waveforms. A virtual rather than actual local oscillator is reliably implemented without mismatch. Filtering between the Weaver mixers is eliminated in favour of filtering at the sampling input and effective time division multiplexing is achieved by selecting between resistor combinations that implement different scaling coefficients, resulting in an efficient analog implementation of a virtual Weaver architecture. | 11-29-2012 |

20120246607 | System and Method for Series and Parallel Combinations of Electrical Elements - A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve compound values having constant ratios to the initial elements and to each other is disclosed. The ratios between compound values can be held constant to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the ratios between values depend primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process. | 09-27-2012 |

20120246208 | FIR Filter with Reduced Element Count - A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal. | 09-27-2012 |

20120245901 | Finite Impulse Response Filter For Producing Outputs Having Different Phases - A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal. | 09-27-2012 |

20110231695 | DIGITAL FORCED OSCILLATION BY DIRECT DIGITAL SYNTHESIS - An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter. | 09-22-2011 |

20110140757 | Analog Processing Elements In A Sum of Products - The technology relates to analog processing of a sum of products. | 06-16-2011 |

20110140743 | Digital Frequency Generator - A digital frequency generator is described. | 06-16-2011 |

20110140738 | Multi-Phase Integrators in Control Systems - Multi-phase integrators in control systems are described. | 06-16-2011 |

20100118173 | Method and apparatus for controlling charge transfer in CMOS sensors with an implant by the transfer gate - An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable description' s of the circuit. | 05-13-2010 |

20080285698 | DIGITAL FORCED OSCILLATION BY DIRECT DIGITAL SYNTHESIS - An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter. | 11-20-2008 |