| EON SILICON SOLUTION INC. Patent applications |
| Patent application number | Title | Published |
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| 20120094450 | MANUFACTURING METHOD OF MULTI-LEVEL CELL NOR FLASH MEMORY - A manufacturing method of a multi-level cell NOR flash memory includes the steps of forming a memory cell area and a peripheral circuit area with the same depth of a shallow trench isolation structure, and the depth ranges from 2400 Å to 2700 Å; forming a non-self-aligned gate structure; performing a self-alignment source manufacturing process; and forming a common source area and a plurality of drain areas. The manufacturing method achieves a high integration density between components and provides a better thermal budget and a better dosage control to the multi-level cell NOR flash memory to improve the production yield rate. | 04-19-2012 |
| 20120057406 | FLASH MEMORY APPARATUS - A flash memory apparatus includes a plurality of memory sectors and a plurality of path transistors, and each memory sector has a local low voltage line, and each path transistor corresponds to one of the memory sectors, and the path transistors are installed in an alignment direction of the memory sectors. One of the path transistors is installed between two adjacent memory sectors, whose gate is connected to a sector select signal line, and whose drain is connected to the local low voltage line of the corresponding memory sector, and whose source is connected to a global low voltage line, and the global low voltage line is installed at an angle substantially equal to 90 degrees across the gate, so as to save the area occupied by peripheral circuits in the path transistors, and lower the manufacturing cost of the flash memory apparatus. | 03-08-2012 |
| 20110070710 | METHOD FOR FABRICATING NOR SEMICONDUCTOR MEMORY STRUCTURE - A method for fabricating a NOR semiconductor memory structure includes: performing a deeply doped source ion implantation process and a lightly doped drain ion implantation process; forming oxide layer walls on two said sides of a gate structure, respectively; performing a pocket implant process with control of an incident angle thereof; and performing a deeply doped drain ion implantation process. Characteristics of the NOR semiconductor memory structure are improved by controllably changing the position of a pocket implant region. | 03-24-2011 |
| 20110070707 | METHOD OF MANUFACTURING NOR FLASH MEMORY - In a method of manufacturing a NOR flash memory, two times of tilt ion implantation process are conducted to form a tilt-implanted source region, so as to improve the distribution of the source region in a semiconductor substrate and reduce the probability of short channel effect (SCE) between the drain regions and the source region in the NOR flash memory. | 03-24-2011 |
| 20100197108 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE STRUCTURE - A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density. | 08-05-2010 |
| 20100171161 | DOUBLE-IMPLANT NOR FLASH MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved. | 07-08-2010 |
| 20100065893 | SEMICONDUCTOR MEMORY STRUCTURE WITH STRESS REGIONS - A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability. | 03-18-2010 |
| 20090086548 | FLASH MEMORY - A flash memory applied in NAND and/or NOR flash memory has a silicon-oxide-nitride-oxide-silicon cell structure, uses channel-hot-electron injection as a write mechanism thereof to have a localized trapping characteristic, and uses hot-hole injection as an erase mechanism thereof. The flash memory uses an oxide-nitride-oxide structure to replace a floating gate, and thereby solves the problem of an entire leakage caused by a local leakage of the floating gate. The flash memory may be miniaturized without the problem of data mutual interference, and may be easily integrated into the CMOS process to largely reduce the manufacturing cost thereof. Meanwhile, the flash memory also enables faster program time and erase time. | 04-02-2009 |
| 20080273399 | SINGLE-POLY NON-VOLATILE MEMORY - A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate. | 11-06-2008 |
