| ENDICOTT INTERCONNECT TECHNOLOGIES, INC. Patent applications |
| Patent application number | Title | Published |
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| 20120112345 | HIGH BANDWIDTH SEMICONDUCTOR BALL GRID ARRAY PACKAGE - A high bandwidth semiconductor printed circuit board assembly (PCBA) providing a layer of dielectric substrate containing plated vias with an upper and lower surface plated with etched copper, mated with a second layer of etched copper plated dielectric containing plated vias that is placed on the top surface of the first layer. A third layer of etched copper plated dielectric containing plated vias may be placed on the bottom layer of etched copper foil. A base layer of etched copper plated thick dielectric containing plated vias is laminated simultaneously with the preceding layers to provide the high bandwidth digital and RF section of the assembly. | 05-10-2012 |
| 20120069531 | CONDUCTING PASTE FOR DEVICE LEVEL INTERCONNECTS - A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance. | 03-22-2012 |
| 20120069288 | LIQUID CRYSTAL POLYMER LAYER FOR ENCAPSULATION AND IMPROVED HERMITICITY OF CIRCUITIZED SUBSTRATES - A substrate and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of polytetrafluoroethylene (PTFE) placed upon both sides of the CIC. A layer of etched copper foil is placed on the outer surface of each PTFE layer. A layer of liquid crystal polymer (LCP) is placed on both layers of etched copper foil. An external layer of etched copper foil is placed on the external surface of the LCP layers. | 03-22-2012 |
| 20120068326 | ANTI-TAMPER MICROCHIP PACKAGE BASED ON THERMAL NANOFLUIDS OR FLUIDS - A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling. | 03-22-2012 |
| 20120031649 | CORELESS LAYER BUILDUP STRUCTURE WITH LGA AND JOINING LAYER - A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging. | 02-09-2012 |
| 20120017437 | CIRCUITIZED SUBSTRATE WITH CONDUCTIVE PASTE, ELECTRICAL ASSEMBLY INCLUDING SAID CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAID SUBSTRATE - A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto. | 01-26-2012 |
| 20120015532 | HIGH DENSITY DECAL AND METHOD FOR ATTACHING SAME - A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal. | 01-19-2012 |
| 20120012553 | METHOD OF FORMING FIBROUS LAMINATE CHIP CARRIER STRUCTURES - A method for making a leadless chip carrier (LCC) for use in electronic packages having a core layer stripped of copper cladding, containing drilled clearance holes within, a layer of resin coated copper (RCC) placed on the upper surface of the core layer and a second layer of RCC placed on the lower surface of the core layer. The layers are laminated together with the RCC filling the clearance holes during lamination. A pattern is etched on the RCC and vias are drilled through the filled clearance holes and pre-plated with seed copper layers. The seed copper layers in the vias are then covered by a layer of copper plating to meet the requirements of the core buildup layer, and resin inhibiting conductive anodic filament (CAF) growth within the structure. | 01-19-2012 |
| 20110284273 | POWER CORE FOR USE IN CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAME - A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core. | 11-24-2011 |
| 20110260299 | METHOD FOR VIA PLATING IN ELECTRONIC PACKAGES CONTAINING FLUOROPOLYMER DIELECTRIC LAYERS - A semiconductor printed circuit board assembly (PCBA) and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of dielectric substrate placed on the core layer. A second layer of dielectric substrate is placed on the lower surface of the core layer of CIC. The layers are laminated together. Blind vias are laser drilled into the layers of dielectric substrate. The partially completed PCBA is subjected to a reactive ion etch (RIE) plasma as a first step to clean blind vias in the PCBA. After the plasma etch, an acidic etchant liquid solution is used on the blind vias. Pre-plating cleaning of blind vias removes a majority of oxides from the blind vias. Seed copper layers are then applied to the PCBA, followed by a layer of copper plating that can be etched to meet the requirements of the PCBA. | 10-27-2011 |
| 20110197430 | SPRING ACTUATED CLAMPING MECHANISM - A spring actuated clamping mechanism has a backer plate with an upper surface and a lower surface. A set of apertures is formed along the periphery of the backer plate. The upper surface of the backer plate has at least one backer plate recess, and preferably four recesses, formed therein. A threaded aperture is also formed in the backer plate. A compression plate is also provided. A second set of apertures is formed along the periphery of the compression plate. The lower surface of the compression plate has at least one compression plate recess, and at least one compression plate aperture. At least one compression spring is disposed between the backer plate and the compression plate. A screw tension release mechanism is screwed into the backer plate threaded aperture and inserted through the compression plate aperture. When the release mechanism is loosened, backer plate is forced downwardly, applying a uniform force to all electrical contacts on the printed circuit board or card to which the clamping mechanism is attached. | 08-18-2011 |
| 20100328868 | CIRCUITIZED SUBSTRATES UTILIZING SMOOTH-SIDED CONDUCTIVE LAYERS AS PART THEREOF - A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided. | 12-30-2010 |
| 20100323558 | HIGH DENSITY CONNECTOR FOR INTERCONNECTING FINE PITCH CIRCUIT PACKAGING STRUCTURES - A pinned interposer and mating sockets to facilitate removable mounting of high connection density micro devices between a pair of substrates in compact electronic circuit packages. The pinned interposer has an inner set of contacts, typically in a rectangular array, that, in cooperation with a mating socket, allows pluggable connection of a micro device such as a MEMS device connected to a first printed circuit substrate. An outer set of contacts on the interposer provides electrical interconnection between the first substrate and a second substrate located atop the high connection density micro device, thereby effectively sandwiching the micro device between the first and second substrates. The outer set of contacts may be disposed in a circular array. | 12-23-2010 |
| 20100167210 | MULTI-LAYER EMBEDDED CAPACITANCE AND RESISTANCE SUBSTRATE CORE - A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser. | 07-01-2010 |
| 20090109624 | Circuitized substrate with internal cooling structure and electrical assembly utilizing same - An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation. The thermal cooling structure is adapted for having cooling fluid pass there-through during operation of the assembly. A method of making the substrate is also provided. | 04-30-2009 |
| 20090093073 | Method of making circuitized substrate with internal optical pathway using photolithography - A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side of the optical core and an adjacent upstanding member such that the opening is defined by at least one angular sidewall. Light passing through the optical core material (or into the core from above) is reflected off this angular sidewall. The medium (e.g., air) within the opening thus also serves as a reflecting medium due to its own reflective index in comparison to that of the adjacent optical core material. The method utilizes many processes used in conventional PCB manufacturing, thereby keeping costs to a minimum. The formed substrate is capable of being both optically and electrically coupled to one or more other substrates possessing similar capabilities, thereby forming an electro-optical assembly of such substrates. | 04-09-2009 |
| 20090092353 | Method of making circuitized substrate with internal optical pathway - A circuitized substrate (e.g., PCB) including an internal optical pathway as part thereof such that the substrate is capable of transmitting and/or receiving both electrical and optical signals. The substrate includes an angular reflector on one of the cladding layers such that optical signals passing through the optical core will impinge on the angled reflecting surfaces of the angular reflector and be reflected up through an opening (including one with optically transparent material therein), e.g., to a second circuitized substrate also having at least one internal optical pathway as part thereof, to thus interconnect the two substrates optically. A method of making the substrate is also provided. | 04-09-2009 |
| 20090035455 | Adhesive bleed prevention method and product produced from same - A method of preventing adhesive bleed onto the metal (e.g., gold) surfaces of a plurality of electrical conductors (e.g., wire-bond pads) positioned on a dielectric substrate when positioning an electronic component onto the dielectric substrate and electrically coupling (e.g., wire-bonding) the component to the metal surfaces. The method includes contacting the metal surfaces with a chemical composition which comprises a minor amount of a surface active agent (e.g., a thiol) and the remainder substantially being a non-reactive solvent (e.g., methanol). A circuitized substrate produced using this method is also provided. | 02-05-2009 |
| 20080301933 | Method of providing a printed circuit board with an edge connection portion - A method of making a printed circuit board in which at least two circuitized substrates are aligned and bonded together (e.g., using lamination). A gasket is provided on one of these and a facing circuitized portion on the other. The gasket forms an effective seal about the circuitized portion to prevent heated dielectric material from contacting the circuitry. After bonding, parts of the bonded structure, including the gasket, are removed to leave a projecting edge portion having circuitry thereon. This edge portion is then adapted for being positioned within an edge connector. | 12-11-2008 |
| 20080248596 | Method of making a circuitized substrate having at least one capacitor therein - A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels. | 10-09-2008 |
| 20080244902 | Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same - A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof. | 10-09-2008 |
| 20080241359 | Method of making circuitized substrate with selected conductors having solder thereon - A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure. | 10-02-2008 |
| 20080238323 | LED lighting assembly and lamp utilizing same - An LED lighting assembly including a plurality of individual LEDs mounted on a common, bendable heat sinking member designed to remove heat from the LEDs during operation and also to be formed (bent) to provide the desired light direction and intensity. Several such assemblies may be used within an LED lamp, as also provided herein. The lamp is ideal for use within medical and dental environments to assure optimal light onto a patient located at a specified distance from the lamp. | 10-02-2008 |
| 20080237840 | Flexible circuit electronic package with standoffs - A flexible circuit electronic package including a heat sink, a flexible circuit having a semiconductor chip positioned thereon and electrically coupled thereto, and a quantity of heat shrunk adhesive securing the flexible circuit to the heat sink such that the flexible circuit is planar. This package is then adapted for being positioned on and electrically coupled to a circuitized substrate such as a printed circuit board. A method of making this package is also provided. | 10-02-2008 |
