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EMULATION AND VERIFICATION ENGINEERING
| EMULATION AND VERIFICATION ENGINEERING Patent applications | ||
| Patent application number | Title | Published |
|---|---|---|
| 20100161306 | METHOD AND SYSTEM FOR EMULATING A DESIGN UNDER TEST ASSOCIATED WITH A TEST ENVIRONMENT - The method of emulating the design under test associated with a test environment comprises two distinct generating phases comprising a first phase of generating ( | 06-24-2010 |